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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
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33 | 33 | USE gaisler.uart.ALL; |
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34 | 34 | USE gaisler.misc.ALL; |
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35 | 35 | USE gaisler.spacewire.ALL; |
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36 | 36 | LIBRARY esa; |
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37 | 37 | USE esa.memoryctrl.ALL; |
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | USE lpp.lpp_lfr_pkg.ALL; |
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42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_management.ALL; |
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46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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47 | 47 | |
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48 | 48 | ENTITY MINI_LFR_top IS |
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49 | 49 | |
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50 | 50 | PORT ( |
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51 | 51 | clk100MHz : IN STD_LOGIC; |
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52 | 52 | clk49_152MHz : IN STD_LOGIC; |
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53 | 53 | reset : IN STD_LOGIC; |
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54 | 54 | --BPs |
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55 | 55 | BP0 : IN STD_LOGIC; |
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56 | 56 | BP1 : IN STD_LOGIC; |
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57 | 57 | --LEDs |
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58 | 58 | LED0 : OUT STD_LOGIC; |
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59 | 59 | LED1 : OUT STD_LOGIC; |
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60 | 60 | LED2 : OUT STD_LOGIC; |
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61 | 61 | --UARTs |
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62 | 62 | TXD1 : IN STD_LOGIC; |
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63 | 63 | RXD1 : OUT STD_LOGIC; |
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64 | 64 | nCTS1 : OUT STD_LOGIC; |
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65 | 65 | nRTS1 : IN STD_LOGIC; |
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66 | 66 | |
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67 | 67 | TXD2 : IN STD_LOGIC; |
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68 | 68 | RXD2 : OUT STD_LOGIC; |
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69 | 69 | nCTS2 : OUT STD_LOGIC; |
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70 | 70 | nDTR2 : IN STD_LOGIC; |
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71 | 71 | nRTS2 : IN STD_LOGIC; |
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72 | 72 | nDCD2 : OUT STD_LOGIC; |
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73 | 73 | |
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74 | 74 | --EXT CONNECTOR |
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75 | 75 | IO0 : INOUT STD_LOGIC; |
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76 | 76 | IO1 : INOUT STD_LOGIC; |
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77 | 77 | IO2 : INOUT STD_LOGIC; |
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78 | 78 | IO3 : INOUT STD_LOGIC; |
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79 | 79 | IO4 : INOUT STD_LOGIC; |
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80 | 80 | IO5 : INOUT STD_LOGIC; |
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81 | 81 | IO6 : INOUT STD_LOGIC; |
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82 | 82 | IO7 : INOUT STD_LOGIC; |
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83 | 83 | IO8 : INOUT STD_LOGIC; |
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84 | 84 | IO9 : INOUT STD_LOGIC; |
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85 | 85 | IO10 : INOUT STD_LOGIC; |
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86 | 86 | IO11 : INOUT STD_LOGIC; |
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87 | 87 | |
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88 | 88 | --SPACE WIRE |
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89 | 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
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90 | 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
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91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
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92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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94 | 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
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95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
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96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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98 | 98 | -- MINI LFR ADC INPUTS |
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99 | 99 | ADC_nCS : OUT STD_LOGIC; |
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100 | 100 | ADC_CLK : OUT STD_LOGIC; |
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101 | 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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102 | 102 | |
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103 | 103 | -- SRAM |
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104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
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105 | 105 | SRAM_CE : OUT STD_LOGIC; |
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106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
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107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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110 | 110 | ); |
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111 | 111 | |
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112 | 112 | END MINI_LFR_top; |
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113 | 113 | |
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114 | 114 | |
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115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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116 | 116 | |
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117 | 117 | --========================================================================== |
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118 | 118 | -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board |
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119 | 119 | -- when enabled, chip enable polarity should be reversed and bank size also |
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120 | 120 | -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 |
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121 | 121 | -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 |
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122 | 122 | --========================================================================== |
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123 | 123 | CONSTANT USE_IAP_MEMCTRL : integer := 1; |
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124 | 124 | --========================================================================== |
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125 | 125 | |
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126 | 126 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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127 | 127 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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128 | 128 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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129 | 129 | ----------------------------------------------------------------------------- |
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130 | 130 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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131 | 131 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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132 | 132 | -- |
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133 | 133 | SIGNAL errorn : STD_LOGIC; |
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134 | 134 | -- |
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135 | 135 | SIGNAL I00_s : STD_LOGIC; |
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136 | 136 | |
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137 | 137 | -- CONSTANTS |
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138 | 138 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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139 | 139 | -- |
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140 | 140 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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141 | 141 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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142 | 142 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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143 | 143 | |
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144 | 144 | SIGNAL apbi_ext : apb_slv_in_type; |
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145 | 145 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); |
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146 | 146 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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147 | 147 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); |
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148 | 148 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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149 | 149 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); |
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150 | 150 | |
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151 | 151 | -- Spacewire signals |
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152 | 152 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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153 | 153 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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154 | 154 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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155 | 155 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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156 | 156 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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157 | 157 | SIGNAL spw_clk : STD_LOGIC; |
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158 | 158 | SIGNAL swni : grspw_in_type; |
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159 | 159 | SIGNAL swno : grspw_out_type; |
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160 | 160 | |
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161 | 161 | --GPIO |
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162 | 162 | SIGNAL gpioi : gpio_in_type; |
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163 | 163 | SIGNAL gpioo : gpio_out_type; |
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164 | 164 | |
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165 | 165 | -- AD Converter ADS7886 |
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166 | 166 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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167 | 167 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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168 | 168 | SIGNAL sample_val : STD_LOGIC; |
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169 | 169 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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170 | 170 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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171 | 171 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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172 | 172 | |
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173 | 173 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
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174 | 174 | |
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175 | 175 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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176 | 176 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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177 | 177 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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178 | 178 | ----------------------------------------------------------------------------- |
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179 | 179 | |
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180 | 180 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
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181 | 181 | SIGNAL LFR_rstn : STD_LOGIC; |
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182 | 182 | |
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183 | 183 | |
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184 | 184 | SIGNAL rstn_25 : STD_LOGIC; |
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185 | 185 | SIGNAL rstn_25_d1 : STD_LOGIC; |
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186 | 186 | SIGNAL rstn_25_d2 : STD_LOGIC; |
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187 | 187 | SIGNAL rstn_25_d3 : STD_LOGIC; |
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188 | 188 | |
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189 | 189 | SIGNAL rstn_24 : STD_LOGIC; |
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190 | 190 | SIGNAL rstn_24_d1 : STD_LOGIC; |
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191 | 191 | SIGNAL rstn_24_d2 : STD_LOGIC; |
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192 | 192 | SIGNAL rstn_24_d3 : STD_LOGIC; |
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193 | 193 | |
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194 | 194 | SIGNAL rstn_50 : STD_LOGIC; |
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195 | 195 | SIGNAL rstn_50_d1 : STD_LOGIC; |
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196 | 196 | SIGNAL rstn_50_d2 : STD_LOGIC; |
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197 | 197 | SIGNAL rstn_50_d3 : STD_LOGIC; |
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198 | 198 | |
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199 | 199 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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200 | 200 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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201 | 201 | |
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202 | 202 | -- |
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203 | 203 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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204 | 204 | |
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205 | 205 | -- |
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206 | 206 | SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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207 | 207 | SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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208 | 208 | |
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209 | 209 | SIGNAL nSRAM_READY : STD_LOGIC; |
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210 | 210 | |
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211 | 211 | BEGIN -- beh |
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212 | 212 | |
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213 | 213 | ----------------------------------------------------------------------------- |
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214 | 214 | PROCESS (clk100MHz, reset) |
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215 | 215 | BEGIN -- PROCESS |
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216 | 216 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge |
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217 | 217 | clk_50_s <= NOT clk_50_s; |
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218 | 218 | END IF; |
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219 | 219 | END PROCESS; |
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220 | 220 | ----------------------------------------------------------------------------- |
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221 | 221 | |
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222 | 222 | PROCESS (clk_50_s, reset) |
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223 | 223 | BEGIN -- PROCESS |
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224 | 224 | IF reset = '0' THEN -- asynchronous reset (active low) |
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225 | 225 | clk_25 <= '0'; |
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226 | 226 | rstn_25 <= '0'; |
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227 | 227 | rstn_25_d1 <= '0'; |
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228 | 228 | rstn_25_d2 <= '0'; |
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229 | 229 | rstn_25_d3 <= '0'; |
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230 | 230 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge |
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231 | 231 | clk_25 <= NOT clk_25; |
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232 | 232 | rstn_25_d1 <= '1'; |
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233 | 233 | rstn_25_d2 <= rstn_25_d1; |
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234 | 234 | rstn_25_d3 <= rstn_25_d2; |
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235 | 235 | rstn_25 <= rstn_25_d3; |
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236 | 236 | END IF; |
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237 | 237 | END PROCESS; |
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238 | 238 | |
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239 | 239 | PROCESS (clk49_152MHz, reset) |
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240 | 240 | BEGIN -- PROCESS |
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241 | 241 | IF reset = '0' THEN -- asynchronous reset (active low) |
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242 | 242 | clk_24 <= '0'; |
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243 | 243 | rstn_24_d1 <= '0'; |
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244 | 244 | rstn_24_d2 <= '0'; |
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245 | 245 | rstn_24_d3 <= '0'; |
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246 | 246 | rstn_24 <= '0'; |
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247 | 247 | ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge |
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248 | 248 | clk_24 <= NOT clk_24; |
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249 | 249 | rstn_24_d1 <= '1'; |
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250 | 250 | rstn_24_d2 <= rstn_24_d1; |
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251 | 251 | rstn_24_d3 <= rstn_24_d2; |
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252 | 252 | rstn_24 <= rstn_24_d3; |
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253 | 253 | END IF; |
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254 | 254 | END PROCESS; |
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255 | 255 | |
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256 | 256 | ----------------------------------------------------------------------------- |
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257 | 257 | |
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258 | 258 | PROCESS (clk_25, rstn_25) |
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259 | 259 | BEGIN -- PROCESS |
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260 | 260 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
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261 | 261 | LED0 <= '0'; |
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262 | 262 | LED1 <= '0'; |
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263 | 263 | LED2 <= '0'; |
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264 | 264 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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265 | 265 | LED0 <= '0'; |
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266 | 266 | LED1 <= '1'; |
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267 | 267 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
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268 | 268 | END IF; |
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269 | 269 | END PROCESS; |
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270 | 270 | |
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271 | 271 | PROCESS (clk49_152MHz, rstn_24) |
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272 | 272 | BEGIN -- PROCESS |
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273 | 273 | IF rstn_24 = '0' THEN -- asynchronous reset (active low) |
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274 | 274 | I00_s <= '0'; |
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275 | 275 | ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge |
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276 | 276 | I00_s <= NOT I00_s; |
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277 | 277 | END IF; |
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278 | 278 | END PROCESS; |
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279 | 279 | |
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280 | 280 | --UARTs |
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281 | 281 | nCTS1 <= '1'; |
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282 | 282 | nCTS2 <= '1'; |
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283 | 283 | nDCD2 <= '1'; |
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284 | 284 | -- No AHB UART |
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285 | 285 | RXD1 <= TXD1; |
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286 | 286 | |
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287 | 287 | -- |
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288 | 288 | |
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289 | 289 | leon3_soc_1 : leon3_soc |
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290 | 290 | GENERIC MAP ( |
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291 | 291 | fabtech => apa3e, |
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292 | 292 | memtech => apa3e, |
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293 | 293 | padtech => inferred, |
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294 | 294 | clktech => inferred, |
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295 | 295 | disas => 0, |
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296 | 296 | dbguart => 0, |
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297 | 297 | pclow => 2, |
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298 | 298 | clk_freq => 25000, |
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299 | 299 | IS_RADHARD => 0, |
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300 | 300 | NB_CPU => 1, |
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301 | 301 | ENABLE_FPU => 1, |
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302 | 302 | FPU_NETLIST => 0, |
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303 | 303 | ENABLE_DSU => 1, |
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304 | 304 | ENABLE_AHB_UART => 0, |
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305 | 305 | ENABLE_APB_UART => 1, |
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306 | 306 | ENABLE_IRQMP => 1, |
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307 | 307 | ENABLE_GPT => 1, |
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308 | 308 | NB_AHB_MASTER => NB_AHB_MASTER, |
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309 | 309 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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310 | 310 | NB_APB_SLAVE => NB_APB_SLAVE, |
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311 | 311 | ADDRESS_SIZE => 20, |
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312 | 312 | USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, |
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313 | 313 | BYPASS_EDAC_MEMCTRLR => '0', |
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314 | 314 | SRBANKSZ => 9) |
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315 | 315 | PORT MAP ( |
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316 | 316 | clk => clk_25, |
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317 | 317 | reset => rstn_25, |
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318 | 318 | errorn => errorn, |
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319 | 319 | ahbrxd => OPEN,--TXD1, |
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320 | 320 | ahbtxd => OPEN,--RXD1, |
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321 | 321 | urxd1 => TXD2, |
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322 | 322 | utxd1 => RXD2, |
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323 | 323 | address => SRAM_A, |
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324 | 324 | data => SRAM_DQ, |
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325 | 325 | nSRAM_BE0 => SRAM_nBE(0), |
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326 | 326 | nSRAM_BE1 => SRAM_nBE(1), |
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327 | 327 | nSRAM_BE2 => SRAM_nBE(2), |
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328 | 328 | nSRAM_BE3 => SRAM_nBE(3), |
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329 | 329 | nSRAM_WE => SRAM_nWE, |
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330 | 330 | nSRAM_CE => SRAM_CE_s, |
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331 | 331 | nSRAM_OE => SRAM_nOE, |
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332 | 332 | nSRAM_READY => nSRAM_READY, |
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333 | 333 | SRAM_MBE => OPEN, |
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334 | 334 | apbi_ext => apbi_ext, |
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335 | 335 | apbo_ext => apbo_ext, |
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336 | 336 | ahbi_s_ext => ahbi_s_ext, |
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337 | 337 | ahbo_s_ext => ahbo_s_ext, |
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338 | 338 | ahbi_m_ext => ahbi_m_ext, |
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339 | 339 | ahbo_m_ext => ahbo_m_ext); |
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340 | 340 | |
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341 | 341 | PROCESS (clk_25, rstn_25) |
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342 | 342 | BEGIN -- PROCESS |
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343 | 343 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
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344 | 344 | nSRAM_READY <= '1'; |
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345 | 345 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
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346 | 346 | nSRAM_READY <= '1'; |
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347 | 347 | IF IO0 = '1' THEN |
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348 | 348 | nSRAM_READY <= '0'; |
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349 | 349 | END IF; |
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350 | 350 | END IF; |
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351 | 351 | END PROCESS; |
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352 | 352 | |
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353 | 353 | |
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354 | 354 | |
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355 | 355 | IAP:if USE_IAP_MEMCTRL = 1 GENERATE |
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356 | 356 | SRAM_CE <= not SRAM_CE_s(0); |
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357 | 357 | END GENERATE; |
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358 | 358 | |
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359 | 359 | NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE |
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360 | 360 | SRAM_CE <= SRAM_CE_s(0); |
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361 | 361 | END GENERATE; |
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362 | 362 | ------------------------------------------------------------------------------- |
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363 | 363 | -- APB_LFR_MANAGEMENT --------------------------------------------------------- |
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364 | 364 | ------------------------------------------------------------------------------- |
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365 | 365 | apb_lfr_management_1 : apb_lfr_management |
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366 | 366 | GENERIC MAP ( |
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367 | 367 | tech => apa3e, |
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368 | 368 | pindex => 6, |
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369 | 369 | paddr => 6, |
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370 | 370 | pmask => 16#fff#, |
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371 | 371 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
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372 | 372 | PORT MAP ( |
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373 | 373 | clk25MHz => clk_25, |
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374 | 374 | resetn_25MHz => rstn_25, |
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375 | 375 | grspw_tick => swno.tickout, |
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376 | 376 | apbi => apbi_ext, |
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377 | 377 | apbo => apbo_ext(6), |
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378 | 378 | HK_sample => sample_hk, |
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379 | 379 | HK_val => sample_val, |
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380 | 380 | HK_sel => HK_SEL, |
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381 | 381 | DAC_SDO => OPEN, |
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382 | 382 | DAC_SCK => OPEN, |
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383 | 383 | DAC_SYNC => OPEN, |
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384 | 384 | DAC_CAL_EN => OPEN, |
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385 | 385 | coarse_time => coarse_time, |
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386 | 386 | fine_time => fine_time, |
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387 | 387 | LFR_soft_rstn => LFR_soft_rstn |
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388 | 388 | ); |
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389 | 389 | |
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390 | 390 | ----------------------------------------------------------------------- |
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391 | 391 | --- SpaceWire -------------------------------------------------------- |
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392 | 392 | ----------------------------------------------------------------------- |
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393 | 393 | |
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394 | 394 | SPW_EN <= '1'; |
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395 | 395 | |
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396 | 396 | spw_clk <= clk_50_s; |
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397 | 397 | spw_rxtxclk <= spw_clk; |
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398 | 398 | spw_rxclkn <= NOT spw_rxtxclk; |
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399 | 399 | |
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400 | 400 | -- PADS for SPW1 |
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401 | 401 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
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402 | 402 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
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403 | 403 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
404 | 404 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
405 | 405 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
406 | 406 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
407 | 407 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
408 | 408 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
409 | 409 | -- PADS FOR SPW2 |
|
410 | 410 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
411 | 411 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
412 | 412 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
413 | 413 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
414 | 414 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
415 | 415 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
416 | 416 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
417 | 417 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
418 | 418 | |
|
419 | 419 | -- GRSPW PHY |
|
420 | 420 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
421 | 421 | spw_phy0 : grspw_phy |
|
422 | 422 | GENERIC MAP( |
|
423 | 423 | tech => apa3e, |
|
424 | 424 | rxclkbuftype => 1, |
|
425 | 425 | scantest => 0) |
|
426 | 426 | PORT MAP( |
|
427 | 427 | rxrst => swno.rxrst, |
|
428 | 428 | di => dtmp(j), |
|
429 | 429 | si => stmp(j), |
|
430 | 430 | rxclko => spw_rxclk(j), |
|
431 | 431 | do => swni.d(j), |
|
432 | 432 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
433 | 433 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
434 | 434 | END GENERATE spw_inputloop; |
|
435 | 435 | |
|
436 | 436 | swni.rmapnodeaddr <= (OTHERS => '0'); |
|
437 | 437 | |
|
438 | 438 | -- SPW core |
|
439 | 439 | sw0 : grspwm GENERIC MAP( |
|
440 | 440 | tech => apa3e, |
|
441 | 441 | hindex => 1, |
|
442 | 442 | pindex => 5, |
|
443 | 443 | paddr => 5, |
|
444 | 444 | pirq => 11, |
|
445 | 445 | sysfreq => 25000, -- CPU_FREQ |
|
446 | 446 | rmap => 1, |
|
447 | 447 | rmapcrc => 1, |
|
448 | 448 | fifosize1 => 16, |
|
449 | 449 | fifosize2 => 16, |
|
450 | 450 | rxclkbuftype => 1, |
|
451 | 451 | rxunaligned => 0, |
|
452 | 452 | rmapbufs => 4, |
|
453 | 453 | ft => 0, |
|
454 | 454 | netlist => 0, |
|
455 | 455 | ports => 2, |
|
456 | 456 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
457 | 457 | memtech => apa3e, |
|
458 | 458 | destkey => 2, |
|
459 | 459 | spwcore => 1 |
|
460 | 460 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
461 | 461 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
462 | 462 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
463 | 463 | ) |
|
464 | 464 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
465 | 465 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
466 | 466 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
467 | 467 | swni, swno); |
|
468 | 468 | |
|
469 | 469 | swni.tickin <= '0'; |
|
470 | 470 | swni.rmapen <= '1'; |
|
471 | 471 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
472 | 472 | swni.tickinraw <= '0'; |
|
473 | 473 | swni.timein <= (OTHERS => '0'); |
|
474 | 474 | swni.dcrstval <= (OTHERS => '0'); |
|
475 | 475 | swni.timerrstval <= (OTHERS => '0'); |
|
476 | 476 | |
|
477 | 477 | ------------------------------------------------------------------------------- |
|
478 | 478 | -- LFR ------------------------------------------------------------------------ |
|
479 | 479 | ------------------------------------------------------------------------------- |
|
480 | 480 | |
|
481 | 481 | |
|
482 | 482 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
483 | 483 | |
|
484 | 484 | lpp_lfr_1 : lpp_lfr |
|
485 | 485 | GENERIC MAP ( |
|
486 | 486 | Mem_use => use_RAM, |
|
487 | 487 | nb_data_by_buffer_size => 32, |
|
488 | 488 | nb_snapshot_param_size => 32, |
|
489 | 489 | delta_vector_size => 32, |
|
490 | 490 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
491 | 491 | pindex => 15, |
|
492 | 492 | paddr => 15, |
|
493 | 493 | pmask => 16#fff#, |
|
494 | 494 | pirq_ms => 6, |
|
495 | 495 | pirq_wfp => 14, |
|
496 | 496 | hindex => 2, |
|
497 |
top_lfr_version => LPP_LFR_BOARD_MINI_LFR & X"015 |
|
|
497 | top_lfr_version => LPP_LFR_BOARD_MINI_LFR & X"015B", | |
|
498 | DATA_SHAPING_SATURATION => 1) -- aa.bb.cc version | |
|
498 | 499 | PORT MAP ( |
|
499 | 500 | clk => clk_25, |
|
500 | 501 | rstn => LFR_rstn, |
|
501 | 502 | sample_B => sample_s(2 DOWNTO 0), |
|
502 | 503 | sample_E => sample_s(7 DOWNTO 3), |
|
503 | 504 | sample_val => sample_val, |
|
504 | 505 | apbi => apbi_ext, |
|
505 | 506 | apbo => apbo_ext(15), |
|
506 | 507 | ahbi => ahbi_m_ext, |
|
507 | 508 | ahbo => ahbo_m_ext(2), |
|
508 | 509 | coarse_time => coarse_time, |
|
509 | 510 | fine_time => fine_time, |
|
510 | 511 | data_shaping_BW => bias_fail_sw_sig, |
|
511 | 512 | debug_vector => lfr_debug_vector, |
|
512 | 513 | debug_vector_ms => lfr_debug_vector_ms |
|
513 | 514 | ); |
|
514 | 515 | |
|
515 | 516 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; |
|
516 | 517 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); |
|
517 | 518 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; |
|
518 | 519 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; |
|
519 | 520 | |
|
520 | 521 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid |
|
521 | 522 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready |
|
522 | 523 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full |
|
523 | 524 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full |
|
524 | 525 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 |
|
525 | 526 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 |
|
526 | 527 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 |
|
527 | 528 | |
|
528 | 529 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
529 | 530 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
530 | 531 | END GENERATE all_sample; |
|
531 | 532 | |
|
532 | 533 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
533 | 534 | GENERIC MAP( |
|
534 | 535 | ChannelCount => 8, |
|
535 | 536 | SampleNbBits => 14, |
|
536 | 537 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
537 | 538 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
538 | 539 | PORT MAP ( |
|
539 | 540 | -- CONV |
|
540 | 541 | cnv_clk => clk_24, |
|
541 | 542 | cnv_rstn => rstn_24, |
|
542 | 543 | cnv => ADC_nCS_sig, |
|
543 | 544 | -- DATA |
|
544 | 545 | clk => clk_25, |
|
545 | 546 | rstn => rstn_25, |
|
546 | 547 | sck => ADC_CLK_sig, |
|
547 | 548 | sdo => ADC_SDO_sig, |
|
548 | 549 | -- SAMPLE |
|
549 | 550 | sample => sample, |
|
550 | 551 | sample_val => sample_val); |
|
551 | 552 | |
|
552 | 553 | ADC_nCS <= ADC_nCS_sig; |
|
553 | 554 | ADC_CLK <= ADC_CLK_sig; |
|
554 | 555 | ADC_SDO_sig <= ADC_SDO; |
|
555 | 556 | |
|
556 | 557 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE |
|
557 | 558 | "0010001000100010" WHEN HK_SEL = "01" ELSE |
|
558 | 559 | "0100010001000100" WHEN HK_SEL = "10" ELSE |
|
559 | 560 | (OTHERS => '0'); |
|
560 | 561 | |
|
561 | 562 | |
|
562 | 563 | ---------------------------------------------------------------------- |
|
563 | 564 | --- GPIO ----------------------------------------------------------- |
|
564 | 565 | ---------------------------------------------------------------------- |
|
565 | 566 | |
|
566 | 567 | grgpio0 : grgpio |
|
567 | 568 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
568 | 569 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
569 | 570 | |
|
570 | 571 | gpioi.sig_en <= (OTHERS => '0'); |
|
571 | 572 | gpioi.sig_in <= (OTHERS => '0'); |
|
572 | 573 | gpioi.din <= (OTHERS => '0'); |
|
573 | 574 | PROCESS (clk_25, rstn_25) |
|
574 | 575 | BEGIN -- PROCESS |
|
575 | 576 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
576 | 577 | IO8 <= '0'; |
|
577 | 578 | IO9 <= '0'; |
|
578 | 579 | IO10 <= '0'; |
|
579 | 580 | IO11 <= '0'; |
|
580 | 581 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
581 | 582 | CASE gpioo.dout(2 DOWNTO 0) IS |
|
582 | 583 | WHEN "011" => |
|
583 | 584 | IO8 <= observation_reg(8); |
|
584 | 585 | IO9 <= observation_reg(9); |
|
585 | 586 | IO10 <= observation_reg(10); |
|
586 | 587 | IO11 <= observation_reg(11); |
|
587 | 588 | WHEN "001" => |
|
588 | 589 | IO8 <= observation_reg(8 + 12); |
|
589 | 590 | IO9 <= observation_reg(9 + 12); |
|
590 | 591 | IO10 <= observation_reg(10 + 12); |
|
591 | 592 | IO11 <= observation_reg(11 + 12); |
|
592 | 593 | WHEN "010" => |
|
593 | 594 | IO8 <= '0'; |
|
594 | 595 | IO9 <= '0'; |
|
595 | 596 | IO10 <= '0'; |
|
596 | 597 | IO11 <= '0'; |
|
597 | 598 | WHEN "000" => |
|
598 | 599 | IO8 <= observation_vector_0(8); |
|
599 | 600 | IO9 <= observation_vector_0(9); |
|
600 | 601 | IO10 <= observation_vector_0(10); |
|
601 | 602 | IO11 <= observation_vector_0(11); |
|
602 | 603 | WHEN "100" => |
|
603 | 604 | IO8 <= observation_vector_1(8); |
|
604 | 605 | IO9 <= observation_vector_1(9); |
|
605 | 606 | IO10 <= observation_vector_1(10); |
|
606 | 607 | IO11 <= observation_vector_1(11); |
|
607 | 608 | WHEN OTHERS => NULL; |
|
608 | 609 | END CASE; |
|
609 | 610 | |
|
610 | 611 | END IF; |
|
611 | 612 | END PROCESS; |
|
612 | 613 | ----------------------------------------------------------------------------- |
|
613 | 614 | -- |
|
614 | 615 | ----------------------------------------------------------------------------- |
|
615 | 616 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE |
|
616 | 617 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE |
|
617 | 618 | apbo_ext(I) <= apb_none; |
|
618 | 619 | END GENERATE apbo_ext_not_used; |
|
619 | 620 | END GENERATE all_apbo_ext; |
|
620 | 621 | |
|
621 | 622 | |
|
622 | 623 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE |
|
623 | 624 | ahbo_s_ext(I) <= ahbs_none; |
|
624 | 625 | END GENERATE all_ahbo_ext; |
|
625 | 626 | |
|
626 | 627 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE |
|
627 | 628 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE |
|
628 | 629 | ahbo_m_ext(I) <= ahbm_none; |
|
629 | 630 | END GENERATE ahbo_m_ext_not_used; |
|
630 | 631 | END GENERATE all_ahbo_m_ext; |
|
631 | 632 | |
|
632 | END beh; No newline at end of file | |
|
633 | END beh; |
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