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add cic_lfr (without the R2 param) subsystem into lpp_lfr_filter
pellion -
r493:3815063a3eb6 (MINI-LFR) WFP_MS-0-1-40 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
195
196 --
196 --
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198
198
199 BEGIN -- beh
199 BEGIN -- beh
200
200
201 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
202 -- CLK
202 -- CLK
203 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
204
204
205 --PROCESS(clk_50)
205 --PROCESS(clk_50)
206 --BEGIN
206 --BEGIN
207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
208 -- clk_50_s <= NOT clk_50_s;
208 -- clk_50_s <= NOT clk_50_s;
209 -- END IF;
209 -- END IF;
210 --END PROCESS;
210 --END PROCESS;
211
211
212 --PROCESS(clk_50_s)
212 --PROCESS(clk_50_s)
213 --BEGIN
213 --BEGIN
214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
215 -- clk_25 <= NOT clk_25;
215 -- clk_25 <= NOT clk_25;
216 -- END IF;
216 -- END IF;
217 --END PROCESS;
217 --END PROCESS;
218
218
219 --PROCESS(clk_49)
219 --PROCESS(clk_49)
220 --BEGIN
220 --BEGIN
221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
222 -- clk_24 <= NOT clk_24;
222 -- clk_24 <= NOT clk_24;
223 -- END IF;
223 -- END IF;
224 --END PROCESS;
224 --END PROCESS;
225
225
226 --PROCESS(clk_25)
226 --PROCESS(clk_25)
227 --BEGIN
227 --BEGIN
228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
229 -- rstn_25 <= reset;
229 -- rstn_25 <= reset;
230 -- END IF;
230 -- END IF;
231 --END PROCESS;
231 --END PROCESS;
232
232
233 PROCESS (clk_50, reset)
233 PROCESS (clk_50, reset)
234 BEGIN -- PROCESS
234 BEGIN -- PROCESS
235 IF reset = '0' THEN -- asynchronous reset (active low)
235 IF reset = '0' THEN -- asynchronous reset (active low)
236 clk_50_s <= '0';
236 clk_50_s <= '0';
237 rstn_50 <= '0';
237 rstn_50 <= '0';
238 rstn_50_d1 <= '0';
238 rstn_50_d1 <= '0';
239 rstn_50_d2 <= '0';
239 rstn_50_d2 <= '0';
240 rstn_50_d3 <= '0';
240 rstn_50_d3 <= '0';
241
241
242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
243 clk_50_s <= NOT clk_50_s;
243 clk_50_s <= NOT clk_50_s;
244 rstn_50_d1 <= '1';
244 rstn_50_d1 <= '1';
245 rstn_50_d2 <= rstn_50_d1;
245 rstn_50_d2 <= rstn_50_d1;
246 rstn_50_d3 <= rstn_50_d2;
246 rstn_50_d3 <= rstn_50_d2;
247 rstn_50 <= rstn_50_d3;
247 rstn_50 <= rstn_50_d3;
248 END IF;
248 END IF;
249 END PROCESS;
249 END PROCESS;
250
250
251 PROCESS (clk_50_s, rstn_50)
251 PROCESS (clk_50_s, rstn_50)
252 BEGIN -- PROCESS
252 BEGIN -- PROCESS
253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
254 clk_25 <= '0';
254 clk_25 <= '0';
255 rstn_25 <= '0';
255 rstn_25 <= '0';
256 rstn_25_d1 <= '0';
256 rstn_25_d1 <= '0';
257 rstn_25_d2 <= '0';
257 rstn_25_d2 <= '0';
258 rstn_25_d3 <= '0';
258 rstn_25_d3 <= '0';
259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
260 clk_25 <= NOT clk_25;
260 clk_25 <= NOT clk_25;
261 rstn_25_d1 <= '1';
261 rstn_25_d1 <= '1';
262 rstn_25_d2 <= rstn_25_d1;
262 rstn_25_d2 <= rstn_25_d1;
263 rstn_25_d3 <= rstn_25_d2;
263 rstn_25_d3 <= rstn_25_d2;
264 rstn_25 <= rstn_25_d3;
264 rstn_25 <= rstn_25_d3;
265 END IF;
265 END IF;
266 END PROCESS;
266 END PROCESS;
267
267
268 PROCESS (clk_49, reset)
268 PROCESS (clk_49, reset)
269 BEGIN -- PROCESS
269 BEGIN -- PROCESS
270 IF reset = '0' THEN -- asynchronous reset (active low)
270 IF reset = '0' THEN -- asynchronous reset (active low)
271 clk_24 <= '0';
271 clk_24 <= '0';
272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
273 clk_24 <= NOT clk_24;
273 clk_24 <= NOT clk_24;
274 END IF;
274 END IF;
275 END PROCESS;
275 END PROCESS;
276
276
277 -----------------------------------------------------------------------------
277 -----------------------------------------------------------------------------
278
278
279 PROCESS (clk_25, rstn_25)
279 PROCESS (clk_25, rstn_25)
280 BEGIN -- PROCESS
280 BEGIN -- PROCESS
281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
282 LED0 <= '0';
282 LED0 <= '0';
283 LED1 <= '0';
283 LED1 <= '0';
284 LED2 <= '0';
284 LED2 <= '0';
285 --IO1 <= '0';
285 --IO1 <= '0';
286 --IO2 <= '1';
286 --IO2 <= '1';
287 --IO3 <= '0';
287 --IO3 <= '0';
288 --IO4 <= '0';
288 --IO4 <= '0';
289 --IO5 <= '0';
289 --IO5 <= '0';
290 --IO6 <= '0';
290 --IO6 <= '0';
291 --IO7 <= '0';
291 --IO7 <= '0';
292 --IO8 <= '0';
292 --IO8 <= '0';
293 --IO9 <= '0';
293 --IO9 <= '0';
294 --IO10 <= '0';
294 --IO10 <= '0';
295 --IO11 <= '0';
295 --IO11 <= '0';
296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
297 LED0 <= '0';
297 LED0 <= '0';
298 LED1 <= '1';
298 LED1 <= '1';
299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
300 --IO1 <= '1';
300 --IO1 <= '1';
301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
302 --IO3 <= ADC_SDO(0);
302 --IO3 <= ADC_SDO(0);
303 --IO4 <= ADC_SDO(1);
303 --IO4 <= ADC_SDO(1);
304 --IO5 <= ADC_SDO(2);
304 --IO5 <= ADC_SDO(2);
305 --IO6 <= ADC_SDO(3);
305 --IO6 <= ADC_SDO(3);
306 --IO7 <= ADC_SDO(4);
306 --IO7 <= ADC_SDO(4);
307 --IO8 <= ADC_SDO(5);
307 --IO8 <= ADC_SDO(5);
308 --IO9 <= ADC_SDO(6);
308 --IO9 <= ADC_SDO(6);
309 --IO10 <= ADC_SDO(7);
309 --IO10 <= ADC_SDO(7);
310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
311 END IF;
311 END IF;
312 END PROCESS;
312 END PROCESS;
313
313
314 PROCESS (clk_24, rstn_25)
314 PROCESS (clk_24, rstn_25)
315 BEGIN -- PROCESS
315 BEGIN -- PROCESS
316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
317 I00_s <= '0';
317 I00_s <= '0';
318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
319 I00_s <= NOT I00_s;
319 I00_s <= NOT I00_s;
320 END IF;
320 END IF;
321 END PROCESS;
321 END PROCESS;
322 -- IO0 <= I00_s;
322 -- IO0 <= I00_s;
323
323
324 --UARTs
324 --UARTs
325 nCTS1 <= '1';
325 nCTS1 <= '1';
326 nCTS2 <= '1';
326 nCTS2 <= '1';
327 nDCD2 <= '1';
327 nDCD2 <= '1';
328
328
329 --EXT CONNECTOR
329 --EXT CONNECTOR
330
330
331 --SPACE WIRE
331 --SPACE WIRE
332
332
333 leon3_soc_1 : leon3_soc
333 leon3_soc_1 : leon3_soc
334 GENERIC MAP (
334 GENERIC MAP (
335 fabtech => apa3e,
335 fabtech => apa3e,
336 memtech => apa3e,
336 memtech => apa3e,
337 padtech => inferred,
337 padtech => inferred,
338 clktech => inferred,
338 clktech => inferred,
339 disas => 0,
339 disas => 0,
340 dbguart => 0,
340 dbguart => 0,
341 pclow => 2,
341 pclow => 2,
342 clk_freq => 25000,
342 clk_freq => 25000,
343 NB_CPU => 1,
343 NB_CPU => 1,
344 ENABLE_FPU => 1,
344 ENABLE_FPU => 1,
345 FPU_NETLIST => 0,
345 FPU_NETLIST => 0,
346 ENABLE_DSU => 1,
346 ENABLE_DSU => 1,
347 ENABLE_AHB_UART => 1,
347 ENABLE_AHB_UART => 1,
348 ENABLE_APB_UART => 1,
348 ENABLE_APB_UART => 1,
349 ENABLE_IRQMP => 1,
349 ENABLE_IRQMP => 1,
350 ENABLE_GPT => 1,
350 ENABLE_GPT => 1,
351 NB_AHB_MASTER => NB_AHB_MASTER,
351 NB_AHB_MASTER => NB_AHB_MASTER,
352 NB_AHB_SLAVE => NB_AHB_SLAVE,
352 NB_AHB_SLAVE => NB_AHB_SLAVE,
353 NB_APB_SLAVE => NB_APB_SLAVE,
353 NB_APB_SLAVE => NB_APB_SLAVE,
354 ADDRESS_SIZE => 20,
354 ADDRESS_SIZE => 20,
355 USES_IAP_MEMCTRLR => 0)
355 USES_IAP_MEMCTRLR => 0)
356 PORT MAP (
356 PORT MAP (
357 clk => clk_25,
357 clk => clk_25,
358 reset => rstn_25,
358 reset => rstn_25,
359 errorn => errorn,
359 errorn => errorn,
360 ahbrxd => TXD1,
360 ahbrxd => TXD1,
361 ahbtxd => RXD1,
361 ahbtxd => RXD1,
362 urxd1 => TXD2,
362 urxd1 => TXD2,
363 utxd1 => RXD2,
363 utxd1 => RXD2,
364 address => SRAM_A,
364 address => SRAM_A,
365 data => SRAM_DQ,
365 data => SRAM_DQ,
366 nSRAM_BE0 => SRAM_nBE(0),
366 nSRAM_BE0 => SRAM_nBE(0),
367 nSRAM_BE1 => SRAM_nBE(1),
367 nSRAM_BE1 => SRAM_nBE(1),
368 nSRAM_BE2 => SRAM_nBE(2),
368 nSRAM_BE2 => SRAM_nBE(2),
369 nSRAM_BE3 => SRAM_nBE(3),
369 nSRAM_BE3 => SRAM_nBE(3),
370 nSRAM_WE => SRAM_nWE,
370 nSRAM_WE => SRAM_nWE,
371 nSRAM_CE => SRAM_CE_s,
371 nSRAM_CE => SRAM_CE_s,
372 nSRAM_OE => SRAM_nOE,
372 nSRAM_OE => SRAM_nOE,
373 nSRAM_READY => '0',
373 nSRAM_READY => '0',
374 SRAM_MBE => OPEN,
374 SRAM_MBE => OPEN,
375 apbi_ext => apbi_ext,
375 apbi_ext => apbi_ext,
376 apbo_ext => apbo_ext,
376 apbo_ext => apbo_ext,
377 ahbi_s_ext => ahbi_s_ext,
377 ahbi_s_ext => ahbi_s_ext,
378 ahbo_s_ext => ahbo_s_ext,
378 ahbo_s_ext => ahbo_s_ext,
379 ahbi_m_ext => ahbi_m_ext,
379 ahbi_m_ext => ahbi_m_ext,
380 ahbo_m_ext => ahbo_m_ext);
380 ahbo_m_ext => ahbo_m_ext);
381
381
382 SRAM_CE <= SRAM_CE_s(0);
382 SRAM_CE <= SRAM_CE_s(0);
383 -------------------------------------------------------------------------------
383 -------------------------------------------------------------------------------
384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
385 -------------------------------------------------------------------------------
385 -------------------------------------------------------------------------------
386 apb_lfr_time_management_1 : apb_lfr_time_management
386 apb_lfr_time_management_1 : apb_lfr_time_management
387 GENERIC MAP (
387 GENERIC MAP (
388 pindex => 6,
388 pindex => 6,
389 paddr => 6,
389 paddr => 6,
390 pmask => 16#fff#,
390 pmask => 16#fff#,
391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
393 PORT MAP (
393 PORT MAP (
394 clk25MHz => clk_25,
394 clk25MHz => clk_25,
395 clk24_576MHz => clk_24, -- 49.152MHz/2
395 clk24_576MHz => clk_24, -- 49.152MHz/2
396 resetn => rstn_25,
396 resetn => rstn_25,
397 grspw_tick => swno.tickout,
397 grspw_tick => swno.tickout,
398 apbi => apbi_ext,
398 apbi => apbi_ext,
399 apbo => apbo_ext(6),
399 apbo => apbo_ext(6),
400 coarse_time => coarse_time,
400 coarse_time => coarse_time,
401 fine_time => fine_time,
401 fine_time => fine_time,
402 LFR_soft_rstn => LFR_soft_rstn
402 LFR_soft_rstn => LFR_soft_rstn
403 );
403 );
404
404
405 -----------------------------------------------------------------------
405 -----------------------------------------------------------------------
406 --- SpaceWire --------------------------------------------------------
406 --- SpaceWire --------------------------------------------------------
407 -----------------------------------------------------------------------
407 -----------------------------------------------------------------------
408
408
409 SPW_EN <= '1';
409 SPW_EN <= '1';
410
410
411 spw_clk <= clk_50_s;
411 spw_clk <= clk_50_s;
412 spw_rxtxclk <= spw_clk;
412 spw_rxtxclk <= spw_clk;
413 spw_rxclkn <= NOT spw_rxtxclk;
413 spw_rxclkn <= NOT spw_rxtxclk;
414
414
415 -- PADS for SPW1
415 -- PADS for SPW1
416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_DIN, dtmp(0));
417 PORT MAP (SPW_NOM_DIN, dtmp(0));
418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
419 PORT MAP (SPW_NOM_SIN, stmp(0));
419 PORT MAP (SPW_NOM_SIN, stmp(0));
420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
424 -- PADS FOR SPW2
424 -- PADS FOR SPW2
425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
426 PORT MAP (SPW_RED_SIN, dtmp(1));
426 PORT MAP (SPW_RED_SIN, dtmp(1));
427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 PORT MAP (SPW_RED_DIN, stmp(1));
428 PORT MAP (SPW_RED_DIN, stmp(1));
429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
430 PORT MAP (SPW_RED_DOUT, swno.d(1));
430 PORT MAP (SPW_RED_DOUT, swno.d(1));
431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
432 PORT MAP (SPW_RED_SOUT, swno.s(1));
432 PORT MAP (SPW_RED_SOUT, swno.s(1));
433
433
434 -- GRSPW PHY
434 -- GRSPW PHY
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
437 spw_phy0 : grspw_phy
437 spw_phy0 : grspw_phy
438 GENERIC MAP(
438 GENERIC MAP(
439 tech => apa3e,
439 tech => apa3e,
440 rxclkbuftype => 1,
440 rxclkbuftype => 1,
441 scantest => 0)
441 scantest => 0)
442 PORT MAP(
442 PORT MAP(
443 rxrst => swno.rxrst,
443 rxrst => swno.rxrst,
444 di => dtmp(j),
444 di => dtmp(j),
445 si => stmp(j),
445 si => stmp(j),
446 rxclko => spw_rxclk(j),
446 rxclko => spw_rxclk(j),
447 do => swni.d(j),
447 do => swni.d(j),
448 ndo => swni.nd(j*5+4 DOWNTO j*5),
448 ndo => swni.nd(j*5+4 DOWNTO j*5),
449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
450 END GENERATE spw_inputloop;
450 END GENERATE spw_inputloop;
451
451
452 swni.rmapnodeaddr <= (OTHERS => '0');
452 swni.rmapnodeaddr <= (OTHERS => '0');
453
453
454 -- SPW core
454 -- SPW core
455 sw0 : grspwm GENERIC MAP(
455 sw0 : grspwm GENERIC MAP(
456 tech => apa3e,
456 tech => apa3e,
457 hindex => 1,
457 hindex => 1,
458 pindex => 5,
458 pindex => 5,
459 paddr => 5,
459 paddr => 5,
460 pirq => 11,
460 pirq => 11,
461 sysfreq => 25000, -- CPU_FREQ
461 sysfreq => 25000, -- CPU_FREQ
462 rmap => 1,
462 rmap => 1,
463 rmapcrc => 1,
463 rmapcrc => 1,
464 fifosize1 => 16,
464 fifosize1 => 16,
465 fifosize2 => 16,
465 fifosize2 => 16,
466 rxclkbuftype => 1,
466 rxclkbuftype => 1,
467 rxunaligned => 0,
467 rxunaligned => 0,
468 rmapbufs => 4,
468 rmapbufs => 4,
469 ft => 0,
469 ft => 0,
470 netlist => 0,
470 netlist => 0,
471 ports => 2,
471 ports => 2,
472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
473 memtech => apa3e,
473 memtech => apa3e,
474 destkey => 2,
474 destkey => 2,
475 spwcore => 1
475 spwcore => 1
476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
479 )
479 )
480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
483 swni, swno);
483 swni, swno);
484
484
485 swni.tickin <= '0';
485 swni.tickin <= '0';
486 swni.rmapen <= '1';
486 swni.rmapen <= '1';
487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
488 swni.tickinraw <= '0';
488 swni.tickinraw <= '0';
489 swni.timein <= (OTHERS => '0');
489 swni.timein <= (OTHERS => '0');
490 swni.dcrstval <= (OTHERS => '0');
490 swni.dcrstval <= (OTHERS => '0');
491 swni.timerrstval <= (OTHERS => '0');
491 swni.timerrstval <= (OTHERS => '0');
492
492
493 -------------------------------------------------------------------------------
493 -------------------------------------------------------------------------------
494 -- LFR ------------------------------------------------------------------------
494 -- LFR ------------------------------------------------------------------------
495 -------------------------------------------------------------------------------
495 -------------------------------------------------------------------------------
496
496
497
497
498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
499 --LFR_rstn <= rstn_25;
499 --LFR_rstn <= rstn_25;
500
500
501 lpp_lfr_1 : lpp_lfr
501 lpp_lfr_1 : lpp_lfr
502 GENERIC MAP (
502 GENERIC MAP (
503 Mem_use => use_RAM,
503 Mem_use => use_RAM,
504 nb_data_by_buffer_size => 32,
504 nb_data_by_buffer_size => 32,
505 nb_snapshot_param_size => 32,
505 nb_snapshot_param_size => 32,
506 delta_vector_size => 32,
506 delta_vector_size => 32,
507 delta_vector_size_f0_2 => 7, -- log2(96)
507 delta_vector_size_f0_2 => 7, -- log2(96)
508 pindex => 15,
508 pindex => 15,
509 paddr => 15,
509 paddr => 15,
510 pmask => 16#fff#,
510 pmask => 16#fff#,
511 pirq_ms => 6,
511 pirq_ms => 6,
512 pirq_wfp => 14,
512 pirq_wfp => 14,
513 hindex => 2,
513 hindex => 2,
514 top_lfr_version => X"000127") -- aa.bb.cc version
514 top_lfr_version => X"000128") -- aa.bb.cc version
515 PORT MAP (
515 PORT MAP (
516 clk => clk_25,
516 clk => clk_25,
517 rstn => LFR_rstn,
517 rstn => LFR_rstn,
518 sample_B => sample_s(2 DOWNTO 0),
518 sample_B => sample_s(2 DOWNTO 0),
519 sample_E => sample_s(7 DOWNTO 3),
519 sample_E => sample_s(7 DOWNTO 3),
520 sample_val => sample_val,
520 sample_val => sample_val,
521 apbi => apbi_ext,
521 apbi => apbi_ext,
522 apbo => apbo_ext(15),
522 apbo => apbo_ext(15),
523 ahbi => ahbi_m_ext,
523 ahbi => ahbi_m_ext,
524 ahbo => ahbo_m_ext(2),
524 ahbo => ahbo_m_ext(2),
525 coarse_time => coarse_time,
525 coarse_time => coarse_time,
526 fine_time => fine_time,
526 fine_time => fine_time,
527 data_shaping_BW => bias_fail_sw_sig,
527 data_shaping_BW => bias_fail_sw_sig,
528 debug_vector => lfr_debug_vector,
528 debug_vector => lfr_debug_vector,
529 debug_vector_ms => lfr_debug_vector_ms
529 debug_vector_ms => lfr_debug_vector_ms
530 );
530 );
531
531
532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
536 IO0 <= rstn_25;
536 IO0 <= rstn_25;
537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
544
544
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
547 END GENERATE all_sample;
547 END GENERATE all_sample;
548
548
549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
550 GENERIC MAP(
550 GENERIC MAP(
551 ChannelCount => 8,
551 ChannelCount => 8,
552 SampleNbBits => 14,
552 SampleNbBits => 14,
553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
555 PORT MAP (
555 PORT MAP (
556 -- CONV
556 -- CONV
557 cnv_clk => clk_24,
557 cnv_clk => clk_24,
558 cnv_rstn => rstn_25,
558 cnv_rstn => rstn_25,
559 cnv => ADC_nCS_sig,
559 cnv => ADC_nCS_sig,
560 -- DATA
560 -- DATA
561 clk => clk_25,
561 clk => clk_25,
562 rstn => rstn_25,
562 rstn => rstn_25,
563 sck => ADC_CLK_sig,
563 sck => ADC_CLK_sig,
564 sdo => ADC_SDO_sig,
564 sdo => ADC_SDO_sig,
565 -- SAMPLE
565 -- SAMPLE
566 sample => sample,
566 sample => sample,
567 sample_val => sample_val);
567 sample_val => sample_val);
568
568
569 --IO10 <= ADC_SDO_sig(5);
569 --IO10 <= ADC_SDO_sig(5);
570 --IO9 <= ADC_SDO_sig(4);
570 --IO9 <= ADC_SDO_sig(4);
571 --IO8 <= ADC_SDO_sig(3);
571 --IO8 <= ADC_SDO_sig(3);
572
572
573 ADC_nCS <= ADC_nCS_sig;
573 ADC_nCS <= ADC_nCS_sig;
574 ADC_CLK <= ADC_CLK_sig;
574 ADC_CLK <= ADC_CLK_sig;
575 ADC_SDO_sig <= ADC_SDO;
575 ADC_SDO_sig <= ADC_SDO;
576
576
577 ----------------------------------------------------------------------
577 ----------------------------------------------------------------------
578 --- GPIO -----------------------------------------------------------
578 --- GPIO -----------------------------------------------------------
579 ----------------------------------------------------------------------
579 ----------------------------------------------------------------------
580
580
581 grgpio0 : grgpio
581 grgpio0 : grgpio
582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
584
584
585 gpioi.sig_en <= (OTHERS => '0');
585 gpioi.sig_en <= (OTHERS => '0');
586 gpioi.sig_in <= (OTHERS => '0');
586 gpioi.sig_in <= (OTHERS => '0');
587 gpioi.din <= (OTHERS => '0');
587 gpioi.din <= (OTHERS => '0');
588 --pio_pad_0 : iopad
588 --pio_pad_0 : iopad
589 -- GENERIC MAP (tech => CFG_PADTECH)
589 -- GENERIC MAP (tech => CFG_PADTECH)
590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
591 --pio_pad_1 : iopad
591 --pio_pad_1 : iopad
592 -- GENERIC MAP (tech => CFG_PADTECH)
592 -- GENERIC MAP (tech => CFG_PADTECH)
593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
594 --pio_pad_2 : iopad
594 --pio_pad_2 : iopad
595 -- GENERIC MAP (tech => CFG_PADTECH)
595 -- GENERIC MAP (tech => CFG_PADTECH)
596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
597 --pio_pad_3 : iopad
597 --pio_pad_3 : iopad
598 -- GENERIC MAP (tech => CFG_PADTECH)
598 -- GENERIC MAP (tech => CFG_PADTECH)
599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
600 --pio_pad_4 : iopad
600 --pio_pad_4 : iopad
601 -- GENERIC MAP (tech => CFG_PADTECH)
601 -- GENERIC MAP (tech => CFG_PADTECH)
602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
603 --pio_pad_5 : iopad
603 --pio_pad_5 : iopad
604 -- GENERIC MAP (tech => CFG_PADTECH)
604 -- GENERIC MAP (tech => CFG_PADTECH)
605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
606 --pio_pad_6 : iopad
606 --pio_pad_6 : iopad
607 -- GENERIC MAP (tech => CFG_PADTECH)
607 -- GENERIC MAP (tech => CFG_PADTECH)
608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
609 --pio_pad_7 : iopad
609 --pio_pad_7 : iopad
610 -- GENERIC MAP (tech => CFG_PADTECH)
610 -- GENERIC MAP (tech => CFG_PADTECH)
611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
612
612
613 PROCESS (clk_25, rstn_25)
613 PROCESS (clk_25, rstn_25)
614 BEGIN -- PROCESS
614 BEGIN -- PROCESS
615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
616 -- --IO0 <= '0';
616 -- --IO0 <= '0';
617 -- IO1 <= '0';
617 -- IO1 <= '0';
618 -- IO2 <= '0';
618 -- IO2 <= '0';
619 -- IO3 <= '0';
619 -- IO3 <= '0';
620 -- IO4 <= '0';
620 -- IO4 <= '0';
621 -- IO5 <= '0';
621 -- IO5 <= '0';
622 -- IO6 <= '0';
622 -- IO6 <= '0';
623 -- IO7 <= '0';
623 -- IO7 <= '0';
624 IO8 <= '0';
624 IO8 <= '0';
625 IO9 <= '0';
625 IO9 <= '0';
626 IO10 <= '0';
626 IO10 <= '0';
627 IO11 <= '0';
627 IO11 <= '0';
628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
629 CASE gpioo.dout(2 DOWNTO 0) IS
629 CASE gpioo.dout(2 DOWNTO 0) IS
630 WHEN "011" =>
630 WHEN "011" =>
631 -- --IO0 <= observation_reg(0 );
631 -- --IO0 <= observation_reg(0 );
632 -- IO1 <= observation_reg(1 );
632 -- IO1 <= observation_reg(1 );
633 -- IO2 <= observation_reg(2 );
633 -- IO2 <= observation_reg(2 );
634 -- IO3 <= observation_reg(3 );
634 -- IO3 <= observation_reg(3 );
635 -- IO4 <= observation_reg(4 );
635 -- IO4 <= observation_reg(4 );
636 -- IO5 <= observation_reg(5 );
636 -- IO5 <= observation_reg(5 );
637 -- IO6 <= observation_reg(6 );
637 -- IO6 <= observation_reg(6 );
638 -- IO7 <= observation_reg(7 );
638 -- IO7 <= observation_reg(7 );
639 IO8 <= observation_reg(8);
639 IO8 <= observation_reg(8);
640 IO9 <= observation_reg(9);
640 IO9 <= observation_reg(9);
641 IO10 <= observation_reg(10);
641 IO10 <= observation_reg(10);
642 IO11 <= observation_reg(11);
642 IO11 <= observation_reg(11);
643 WHEN "001" =>
643 WHEN "001" =>
644 -- --IO0 <= observation_reg(0 + 12);
644 -- --IO0 <= observation_reg(0 + 12);
645 -- IO1 <= observation_reg(1 + 12);
645 -- IO1 <= observation_reg(1 + 12);
646 -- IO2 <= observation_reg(2 + 12);
646 -- IO2 <= observation_reg(2 + 12);
647 -- IO3 <= observation_reg(3 + 12);
647 -- IO3 <= observation_reg(3 + 12);
648 -- IO4 <= observation_reg(4 + 12);
648 -- IO4 <= observation_reg(4 + 12);
649 -- IO5 <= observation_reg(5 + 12);
649 -- IO5 <= observation_reg(5 + 12);
650 -- IO6 <= observation_reg(6 + 12);
650 -- IO6 <= observation_reg(6 + 12);
651 -- IO7 <= observation_reg(7 + 12);
651 -- IO7 <= observation_reg(7 + 12);
652 IO8 <= observation_reg(8 + 12);
652 IO8 <= observation_reg(8 + 12);
653 IO9 <= observation_reg(9 + 12);
653 IO9 <= observation_reg(9 + 12);
654 IO10 <= observation_reg(10 + 12);
654 IO10 <= observation_reg(10 + 12);
655 IO11 <= observation_reg(11 + 12);
655 IO11 <= observation_reg(11 + 12);
656 WHEN "010" =>
656 WHEN "010" =>
657 -- --IO0 <= observation_reg(0 + 12 + 12);
657 -- --IO0 <= observation_reg(0 + 12 + 12);
658 -- IO1 <= observation_reg(1 + 12 + 12);
658 -- IO1 <= observation_reg(1 + 12 + 12);
659 -- IO2 <= observation_reg(2 + 12 + 12);
659 -- IO2 <= observation_reg(2 + 12 + 12);
660 -- IO3 <= observation_reg(3 + 12 + 12);
660 -- IO3 <= observation_reg(3 + 12 + 12);
661 -- IO4 <= observation_reg(4 + 12 + 12);
661 -- IO4 <= observation_reg(4 + 12 + 12);
662 -- IO5 <= observation_reg(5 + 12 + 12);
662 -- IO5 <= observation_reg(5 + 12 + 12);
663 -- IO6 <= observation_reg(6 + 12 + 12);
663 -- IO6 <= observation_reg(6 + 12 + 12);
664 -- IO7 <= observation_reg(7 + 12 + 12);
664 -- IO7 <= observation_reg(7 + 12 + 12);
665 IO8 <= '0';
665 IO8 <= '0';
666 IO9 <= '0';
666 IO9 <= '0';
667 IO10 <= '0';
667 IO10 <= '0';
668 IO11 <= '0';
668 IO11 <= '0';
669 WHEN "000" =>
669 WHEN "000" =>
670 -- --IO0 <= observation_vector_0(0 );
670 -- --IO0 <= observation_vector_0(0 );
671 -- IO1 <= observation_vector_0(1 );
671 -- IO1 <= observation_vector_0(1 );
672 -- IO2 <= observation_vector_0(2 );
672 -- IO2 <= observation_vector_0(2 );
673 -- IO3 <= observation_vector_0(3 );
673 -- IO3 <= observation_vector_0(3 );
674 -- IO4 <= observation_vector_0(4 );
674 -- IO4 <= observation_vector_0(4 );
675 -- IO5 <= observation_vector_0(5 );
675 -- IO5 <= observation_vector_0(5 );
676 -- IO6 <= observation_vector_0(6 );
676 -- IO6 <= observation_vector_0(6 );
677 -- IO7 <= observation_vector_0(7 );
677 -- IO7 <= observation_vector_0(7 );
678 IO8 <= observation_vector_0(8);
678 IO8 <= observation_vector_0(8);
679 IO9 <= observation_vector_0(9);
679 IO9 <= observation_vector_0(9);
680 IO10 <= observation_vector_0(10);
680 IO10 <= observation_vector_0(10);
681 IO11 <= observation_vector_0(11);
681 IO11 <= observation_vector_0(11);
682 WHEN "100" =>
682 WHEN "100" =>
683 -- --IO0 <= observation_vector_1(0 );
683 -- --IO0 <= observation_vector_1(0 );
684 -- IO1 <= observation_vector_1(1 );
684 -- IO1 <= observation_vector_1(1 );
685 -- IO2 <= observation_vector_1(2 );
685 -- IO2 <= observation_vector_1(2 );
686 -- IO3 <= observation_vector_1(3 );
686 -- IO3 <= observation_vector_1(3 );
687 -- IO4 <= observation_vector_1(4 );
687 -- IO4 <= observation_vector_1(4 );
688 -- IO5 <= observation_vector_1(5 );
688 -- IO5 <= observation_vector_1(5 );
689 -- IO6 <= observation_vector_1(6 );
689 -- IO6 <= observation_vector_1(6 );
690 -- IO7 <= observation_vector_1(7 );
690 -- IO7 <= observation_vector_1(7 );
691 IO8 <= observation_vector_1(8);
691 IO8 <= observation_vector_1(8);
692 IO9 <= observation_vector_1(9);
692 IO9 <= observation_vector_1(9);
693 IO10 <= observation_vector_1(10);
693 IO10 <= observation_vector_1(10);
694 IO11 <= observation_vector_1(11);
694 IO11 <= observation_vector_1(11);
695 WHEN OTHERS => NULL;
695 WHEN OTHERS => NULL;
696 END CASE;
696 END CASE;
697
697
698 END IF;
698 END IF;
699 END PROCESS;
699 END PROCESS;
700 -----------------------------------------------------------------------------
700 -----------------------------------------------------------------------------
701 --
701 --
702 -----------------------------------------------------------------------------
702 -----------------------------------------------------------------------------
703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
705 apbo_ext(I) <= apb_none;
705 apbo_ext(I) <= apb_none;
706 END GENERATE apbo_ext_not_used;
706 END GENERATE apbo_ext_not_used;
707 END GENERATE all_apbo_ext;
707 END GENERATE all_apbo_ext;
708
708
709
709
710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
711 ahbo_s_ext(I) <= ahbs_none;
711 ahbo_s_ext(I) <= ahbs_none;
712 END GENERATE all_ahbo_ext;
712 END GENERATE all_ahbo_ext;
713
713
714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
716 ahbo_m_ext(I) <= ahbm_none;
716 ahbo_m_ext(I) <= ahbm_none;
717 END GENERATE ahbo_m_ext_not_used;
717 END GENERATE ahbo_m_ext_not_used;
718 END GENERATE all_ahbo_m_ext;
718 END GENERATE all_ahbo_m_ext;
719
719
720 END beh;
720 END beh;
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@@ -1,386 +1,376
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
1 LIBRARY ieee;
23 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
4
26
5 LIBRARY lpp;
27 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
28 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
29 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
30 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
31 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
32 USE lpp.lpp_waveform_pkg.ALL;
33 USE lpp.cic_pkg.ALL;
34 USE data_type_pkg.ALL;
11
35
12 LIBRARY techmap;
36 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
14
38
15 LIBRARY grlib;
39 LIBRARY grlib;
16 USE grlib.amba.ALL;
40 USE grlib.amba.ALL;
17 USE grlib.stdlib.ALL;
41 USE grlib.stdlib.ALL;
18 USE grlib.devices.ALL;
42 USE grlib.devices.ALL;
19 USE GRLIB.DMA2AHB_Package.ALL;
43 USE GRLIB.DMA2AHB_Package.ALL;
20
44
21 ENTITY lpp_lfr_filter IS
45 ENTITY lpp_lfr_filter IS
22 GENERIC(
46 GENERIC(
23 Mem_use : INTEGER := use_RAM
47 Mem_use : INTEGER := use_RAM
24 );
48 );
25 PORT (
49 PORT (
26 sample : IN Samples(7 DOWNTO 0);
50 sample : IN Samples(7 DOWNTO 0);
27 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
28 --
52 --
29 clk : IN STD_LOGIC;
53 clk : IN STD_LOGIC;
30 rstn : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
31 --
55 --
32 data_shaping_SP0 : IN STD_LOGIC;
56 data_shaping_SP0 : IN STD_LOGIC;
33 data_shaping_SP1 : IN STD_LOGIC;
57 data_shaping_SP1 : IN STD_LOGIC;
34 data_shaping_R0 : IN STD_LOGIC;
58 data_shaping_R0 : IN STD_LOGIC;
35 data_shaping_R1 : IN STD_LOGIC;
59 data_shaping_R1 : IN STD_LOGIC;
36 data_shaping_R2 : IN STD_LOGIC;
60 data_shaping_R2 : IN STD_LOGIC;
37 --
61 --
38 sample_f0_val : OUT STD_LOGIC;
62 sample_f0_val : OUT STD_LOGIC;
39 sample_f1_val : OUT STD_LOGIC;
63 sample_f1_val : OUT STD_LOGIC;
40 sample_f2_val : OUT STD_LOGIC;
64 sample_f2_val : OUT STD_LOGIC;
41 sample_f3_val : OUT STD_LOGIC;
65 sample_f3_val : OUT STD_LOGIC;
42 --
66 --
43 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
67 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
44 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
45 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
46 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
70 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
47 );
71 );
48 END lpp_lfr_filter;
72 END lpp_lfr_filter;
49
73
50 ARCHITECTURE tb OF lpp_lfr_filter IS
74 ARCHITECTURE tb OF lpp_lfr_filter IS
51
75
52 COMPONENT Downsampling
76 COMPONENT Downsampling
53 GENERIC (
77 GENERIC (
54 ChanelCount : INTEGER;
78 ChanelCount : INTEGER;
55 SampleSize : INTEGER;
79 SampleSize : INTEGER;
56 DivideParam : INTEGER);
80 DivideParam : INTEGER);
57 PORT (
81 PORT (
58 clk : IN STD_LOGIC;
82 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
60 sample_in_val : IN STD_LOGIC;
84 sample_in_val : IN STD_LOGIC;
61 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
85 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
62 sample_out_val : OUT STD_LOGIC;
86 sample_out_val : OUT STD_LOGIC;
63 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
87 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
64 END COMPONENT;
88 END COMPONENT;
65
89
66 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
67 CONSTANT ChanelCount : INTEGER := 8;
91 CONSTANT ChanelCount : INTEGER := 8;
68
92
69 -----------------------------------------------------------------------------
93 -----------------------------------------------------------------------------
70 SIGNAL sample_val_delay : STD_LOGIC;
94 SIGNAL sample_val_delay : STD_LOGIC;
71 -----------------------------------------------------------------------------
95 -----------------------------------------------------------------------------
72 CONSTANT Coef_SZ : INTEGER := 9;
96 CONSTANT Coef_SZ : INTEGER := 9;
73 CONSTANT CoefCntPerCel : INTEGER := 6;
97 CONSTANT CoefCntPerCel : INTEGER := 6;
74 CONSTANT CoefPerCel : INTEGER := 5;
98 CONSTANT CoefPerCel : INTEGER := 5;
75 CONSTANT Cels_count : INTEGER := 5;
99 CONSTANT Cels_count : INTEGER := 5;
76
100
77 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
101 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
78 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
102 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
79 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
103 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
80 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
104 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
81 --
105 --
82 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
106 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
83 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
107 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
84 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
85 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
109 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
86 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
110 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
87 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
111 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
88 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
112 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
89 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
113 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
90 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
114 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
91 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
115 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
92 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
93 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
117 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
94 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
118 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
95 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
96 -- SIGNAL sample_f0_val : STD_LOGIC;
120 -- SIGNAL sample_f0_val : STD_LOGIC;
97 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
121 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
98 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
122 SIGNAL sample_f0_s : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
99 --
123 --
100 -- SIGNAL sample_f1_val : STD_LOGIC;
124 -- SIGNAL sample_f1_val : STD_LOGIC;
101 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
125 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
102 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
126 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
103 --
127 --
104 -- SIGNAL sample_f2_val : STD_LOGIC;
128 -- SIGNAL sample_f2_val : STD_LOGIC;
105 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
129 SIGNAL sample_f2 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
106 --
130 SIGNAL sample_f3 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
107 -- SIGNAL sample_f3_val : STD_LOGIC;
108 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
109
131
110 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
111 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
133 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
134 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
135 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
114 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
136 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
115 -----------------------------------------------------------------------------
137 -----------------------------------------------------------------------------
116
138
117 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
139 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
140 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
141 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
142 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
121
143
122 SIGNAL sample_f0_val_s : STD_LOGIC;
144 SIGNAL sample_f0_val_s : STD_LOGIC;
123 SIGNAL sample_f1_val_s : STD_LOGIC;
145 SIGNAL sample_f1_val_s : STD_LOGIC;
124 BEGIN
146 BEGIN
125
147
126 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
127 PROCESS (clk, rstn)
149 PROCESS (clk, rstn)
128 BEGIN -- PROCESS
150 BEGIN -- PROCESS
129 IF rstn = '0' THEN -- asynchronous reset (active low)
151 IF rstn = '0' THEN -- asynchronous reset (active low)
130 sample_val_delay <= '0';
152 sample_val_delay <= '0';
131 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
153 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
132 sample_val_delay <= sample_val;
154 sample_val_delay <= sample_val;
133 END IF;
155 END IF;
134 END PROCESS;
156 END PROCESS;
135
157
136 -----------------------------------------------------------------------------
158 -----------------------------------------------------------------------------
137 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
159 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
138 SampleLoop : FOR j IN 0 TO 15 GENERATE
160 SampleLoop : FOR j IN 0 TO 15 GENERATE
139 sample_filter_in(i, j) <= sample(i)(j);
161 sample_filter_in(i, j) <= sample(i)(j);
140 END GENERATE;
162 END GENERATE;
141
163
142 sample_filter_in(i, 16) <= sample(i)(15);
164 sample_filter_in(i, 16) <= sample(i)(15);
143 sample_filter_in(i, 17) <= sample(i)(15);
165 sample_filter_in(i, 17) <= sample(i)(15);
144 END GENERATE;
166 END GENERATE;
145
167
146 coefs_v2 <= CoefsInitValCst_v2;
168 coefs_v2 <= CoefsInitValCst_v2;
147
169
148 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
170 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
149 GENERIC MAP (
171 GENERIC MAP (
150 tech => 0,
172 tech => 0,
151 Mem_use => Mem_use, -- use_RAM
173 Mem_use => Mem_use, -- use_RAM
152 Sample_SZ => 18,
174 Sample_SZ => 18,
153 Coef_SZ => Coef_SZ,
175 Coef_SZ => Coef_SZ,
154 Coef_Nb => 25,
176 Coef_Nb => 25,
155 Coef_sel_SZ => 5,
177 Coef_sel_SZ => 5,
156 Cels_count => Cels_count,
178 Cels_count => Cels_count,
157 ChanelsCount => ChanelCount)
179 ChanelsCount => ChanelCount)
158 PORT MAP (
180 PORT MAP (
159 rstn => rstn,
181 rstn => rstn,
160 clk => clk,
182 clk => clk,
161 virg_pos => 7,
183 virg_pos => 7,
162 coefs => coefs_v2,
184 coefs => coefs_v2,
163 sample_in_val => sample_val_delay,
185 sample_in_val => sample_val_delay,
164 sample_in => sample_filter_in,
186 sample_in => sample_filter_in,
165 sample_out_val => sample_filter_v2_out_val,
187 sample_out_val => sample_filter_v2_out_val,
166 sample_out => sample_filter_v2_out);
188 sample_out => sample_filter_v2_out);
167
189
168 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
169 -- DATA_SHAPING
191 -- DATA_SHAPING
170 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
171 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
193 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
172 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
194 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
173 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
195 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
174 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
196 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
175 END GENERATE all_data_shaping_in_loop;
197 END GENERATE all_data_shaping_in_loop;
176
198
177 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
199 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
178 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
200 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
179
201
180 PROCESS (clk, rstn)
202 PROCESS (clk, rstn)
181 BEGIN -- PROCESS
203 BEGIN -- PROCESS
182 IF rstn = '0' THEN -- asynchronous reset (active low)
204 IF rstn = '0' THEN -- asynchronous reset (active low)
183 sample_data_shaping_out_val <= '0';
205 sample_data_shaping_out_val <= '0';
184 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
206 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
185 sample_data_shaping_out_val <= sample_filter_v2_out_val;
207 sample_data_shaping_out_val <= sample_filter_v2_out_val;
186 END IF;
208 END IF;
187 END PROCESS;
209 END PROCESS;
188
210
189 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
211 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
190 PROCESS (clk, rstn)
212 PROCESS (clk, rstn)
191 BEGIN
213 BEGIN
192 IF rstn = '0' THEN
214 IF rstn = '0' THEN
193 sample_data_shaping_out(0, j) <= '0';
215 sample_data_shaping_out(0, j) <= '0';
194 sample_data_shaping_out(1, j) <= '0';
216 sample_data_shaping_out(1, j) <= '0';
195 sample_data_shaping_out(2, j) <= '0';
217 sample_data_shaping_out(2, j) <= '0';
196 sample_data_shaping_out(3, j) <= '0';
218 sample_data_shaping_out(3, j) <= '0';
197 sample_data_shaping_out(4, j) <= '0';
219 sample_data_shaping_out(4, j) <= '0';
198 sample_data_shaping_out(5, j) <= '0';
220 sample_data_shaping_out(5, j) <= '0';
199 sample_data_shaping_out(6, j) <= '0';
221 sample_data_shaping_out(6, j) <= '0';
200 sample_data_shaping_out(7, j) <= '0';
222 sample_data_shaping_out(7, j) <= '0';
201 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
223 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
202 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
224 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
203 IF data_shaping_SP0 = '1' THEN
225 IF data_shaping_SP0 = '1' THEN
204 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
226 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
205 ELSE
227 ELSE
206 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
228 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
207 END IF;
229 END IF;
208 IF data_shaping_SP1 = '1' THEN
230 IF data_shaping_SP1 = '1' THEN
209 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
231 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
210 ELSE
232 ELSE
211 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
233 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
212 END IF;
234 END IF;
213 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
235 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
214 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
236 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
215 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
237 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
216 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
238 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
217 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
239 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
218 END IF;
240 END IF;
219 END PROCESS;
241 END PROCESS;
220 END GENERATE;
242 END GENERATE;
221
243
222 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
244 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
223 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
245 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
224 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
246 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
225 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
247 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
226 END GENERATE;
248 END GENERATE;
227 END GENERATE;
249 END GENERATE;
228 -----------------------------------------------------------------------------
250 -----------------------------------------------------------------------------
229 -- F0 -- @24.576 kHz
251 -- F0 -- @24.576 kHz
230 -----------------------------------------------------------------------------
252 -----------------------------------------------------------------------------
231 Downsampling_f0 : Downsampling
253 Downsampling_f0 : Downsampling
232 GENERIC MAP (
254 GENERIC MAP (
233 ChanelCount => 8,
255 ChanelCount => 8,
234 SampleSize => 16,
256 SampleSize => 16,
235 DivideParam => 4)
257 DivideParam => 4)
236 PORT MAP (
258 PORT MAP (
237 clk => clk,
259 clk => clk,
238 rstn => rstn,
260 rstn => rstn,
239 sample_in_val => sample_filter_v2_out_val_s,
261 sample_in_val => sample_filter_v2_out_val_s,
240 sample_in => sample_filter_v2_out_s,
262 sample_in => sample_filter_v2_out_s,
241 sample_out_val => sample_f0_val_s,
263 sample_out_val => sample_f0_val_s,
242 sample_out => sample_f0);
264 sample_out => sample_f0);
243
265
244 sample_f0_val <= sample_f0_val_s;
266 sample_f0_val <= sample_f0_val_s;
245
267
246 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
268 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
247 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
269 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
248 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
270 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
249 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
271 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
250 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
272 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
251 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
273 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
252 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
274 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
253 END GENERATE all_bit_sample_f0;
275 END GENERATE all_bit_sample_f0;
254
276
255 --sample_f0_wen <= NOT(sample_f0_val) &
277 --sample_f0_wen <= NOT(sample_f0_val) &
256 -- NOT(sample_f0_val) &
278 -- NOT(sample_f0_val) &
257 -- NOT(sample_f0_val) &
279 -- NOT(sample_f0_val) &
258 -- NOT(sample_f0_val) &
280 -- NOT(sample_f0_val) &
259 -- NOT(sample_f0_val) &
281 -- NOT(sample_f0_val) &
260 -- NOT(sample_f0_val);
282 -- NOT(sample_f0_val);
261
283
262 -----------------------------------------------------------------------------
284 -----------------------------------------------------------------------------
263 -- F1 -- @4096 Hz
285 -- F1 -- @4096 Hz
264 -----------------------------------------------------------------------------
286 -----------------------------------------------------------------------------
265 Downsampling_f1 : Downsampling
287 Downsampling_f1 : Downsampling
266 GENERIC MAP (
288 GENERIC MAP (
267 ChanelCount => 8,
289 ChanelCount => 8,
268 SampleSize => 16,
290 SampleSize => 16,
269 DivideParam => 6)
291 DivideParam => 6)
270 PORT MAP (
292 PORT MAP (
271 clk => clk,
293 clk => clk,
272 rstn => rstn,
294 rstn => rstn,
273 sample_in_val => sample_f0_val_s ,
295 sample_in_val => sample_f0_val_s ,
274 sample_in => sample_f0,
296 sample_in => sample_f0,
275 sample_out_val => sample_f1_val_s,
297 sample_out_val => sample_f1_val_s,
276 sample_out => sample_f1);
298 sample_out => sample_f1);
277
299
278 sample_f1_val <= sample_f1_val_s;
300 sample_f1_val <= sample_f1_val_s;
279
301
280 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
302 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
281 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
303 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
282 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
304 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
283 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
305 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
284 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
306 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
285 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
307 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
286 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
308 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
287 END GENERATE all_bit_sample_f1;
309 END GENERATE all_bit_sample_f1;
288
310
289 --sample_f1_wen <= NOT(sample_f1_val) &
311 --sample_f1_wen <= NOT(sample_f1_val) &
290 -- NOT(sample_f1_val) &
312 -- NOT(sample_f1_val) &
291 -- NOT(sample_f1_val) &
313 -- NOT(sample_f1_val) &
292 -- NOT(sample_f1_val) &
314 -- NOT(sample_f1_val) &
293 -- NOT(sample_f1_val) &
315 -- NOT(sample_f1_val) &
294 -- NOT(sample_f1_val);
316 -- NOT(sample_f1_val);
295
317
296 -----------------------------------------------------------------------------
318 -----------------------------------------------------------------------------
297 -- F2 -- @256 Hz
319 -- F2 -- @256 Hz
320 -- F3 -- @16 Hz
298 -----------------------------------------------------------------------------
321 -----------------------------------------------------------------------------
299 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
322 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
300 sample_f0_s(0, I) <= sample_f0(0, I); -- V
323 sample_f0_s(0, I) <= sample_f0(0, I); -- V
301 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
324 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
302 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
325 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
303 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
326 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
304 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
327 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
305 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
328 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
306 END GENERATE all_bit_sample_f0_s;
329 END GENERATE all_bit_sample_f0_s;
307
330
308 Downsampling_f2 : Downsampling
331
332 cic_lfr_1: cic_lfr
309 GENERIC MAP (
333 GENERIC MAP (
310 ChanelCount => 6,
334 tech => 0,
311 SampleSize => 16,
335 use_RAM_nCEL => Mem_use)
312 DivideParam => 96)
313 PORT MAP (
336 PORT MAP (
314 clk => clk,
337 clk => clk,
315 rstn => rstn,
338 rstn => rstn,
316 sample_in_val => sample_f0_val_s ,
339 run => '1',
317 sample_in => sample_f0_s,
340
318 sample_out_val => sample_f2_val,
341 data_in => sample_f0_s,
319 sample_out => sample_f2);
342 data_in_valid => sample_f0_val_s,
320
343
321 --sample_f2_wen <= NOT(sample_f2_val) &
344 data_out_16 => sample_f2,
322 -- NOT(sample_f2_val) &
345 data_out_16_valid => sample_f2_val,
323 -- NOT(sample_f2_val) &
346
324 -- NOT(sample_f2_val) &
347 data_out_256 => sample_f3,
325 -- NOT(sample_f2_val) &
348 data_out_256_valid => sample_f3_val);
326 -- NOT(sample_f2_val);
327
349
328 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
350 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
329 sample_f2_wdata_s(I) <= sample_f2(0, I);
351 sample_f2_wdata_s(I) <= sample_f2(0, I);
330 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(3, I);
352 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
331 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(4, I);
353 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
332 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
354 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
333 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
355 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
334 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
356 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
335 END GENERATE all_bit_sample_f2;
357 END GENERATE all_bit_sample_f2;
336
358
337 -----------------------------------------------------------------------------
338 -- F3 -- @16 Hz
339 -----------------------------------------------------------------------------
340 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
341 sample_f1_s(0, I) <= sample_f1(0, I); -- V
342 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
343 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
344 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
345 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
346 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
347 END GENERATE all_bit_sample_f1_s;
348
349 Downsampling_f3 : Downsampling
350 GENERIC MAP (
351 ChanelCount => 6,
352 SampleSize => 16,
353 DivideParam => 256)
354 PORT MAP (
355 clk => clk,
356 rstn => rstn,
357 sample_in_val => sample_f1_val_s ,
358 sample_in => sample_f1_s,
359 sample_out_val => sample_f3_val,
360 sample_out => sample_f3);
361
362 --sample_f3_wen <= (NOT sample_f3_val) &
363 -- (NOT sample_f3_val) &
364 -- (NOT sample_f3_val) &
365 -- (NOT sample_f3_val) &
366 -- (NOT sample_f3_val) &
367 -- (NOT sample_f3_val);
368
369 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
359 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
370 sample_f3_wdata_s(I) <= sample_f3(0, I);
360 sample_f3_wdata_s(I) <= sample_f3(0, I);
371 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
361 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
372 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
362 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
373 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
363 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
374 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
364 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
375 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
365 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
376 END GENERATE all_bit_sample_f3;
366 END GENERATE all_bit_sample_f3;
377
367
378 -----------------------------------------------------------------------------
368 -----------------------------------------------------------------------------
379 --
369 --
380 -----------------------------------------------------------------------------
370 -----------------------------------------------------------------------------
381 sample_f0_wdata <= sample_f0_wdata_s;
371 sample_f0_wdata <= sample_f0_wdata_s;
382 sample_f1_wdata <= sample_f1_wdata_s;
372 sample_f1_wdata <= sample_f1_wdata_s;
383 sample_f2_wdata <= sample_f2_wdata_s;
373 sample_f2_wdata <= sample_f2_wdata_s;
384 sample_f3_wdata <= sample_f3_wdata_s;
374 sample_f3_wdata <= sample_f3_wdata_s;
385
375
386 END tb; No newline at end of file
376 END tb;
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