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LFR-em 1.1.83 version C ...
pellion -
r609:36cc9f0ea776 simu_with_Leon3
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 85 -- DAC --------------------------------------------------------------------
86 86 DAC_SDO : OUT STD_LOGIC;
87 87 DAC_SCK : OUT STD_LOGIC;
88 88 DAC_SYNC : OUT STD_LOGIC;
89 89 DAC_CAL_EN : OUT STD_LOGIC;
90 90 -- HK ---------------------------------------------------------------------
91 91 HK_smpclk : OUT STD_LOGIC;
92 92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 94 ---------------------------------------------------------------------------
95 95 TAG8 : OUT STD_LOGIC;
96 96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 97 );
98 98
99 99 END LFR_em;
100 100
101 101
102 102 ARCHITECTURE beh OF LFR_em IS
103 103
104 104 --==========================================================================
105 105 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
106 106 -- when enabled, chip enable polarity should be reversed and bank size also
107 107 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
108 108 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
109 109 --==========================================================================
110 110 CONSTANT USE_IAP_MEMCTRL : integer := 1;
111 111 --==========================================================================
112 112
113 113 SIGNAL clk_50_s : STD_LOGIC := '0';
114 114 SIGNAL clk_25 : STD_LOGIC := '0';
115 115 SIGNAL clk_24 : STD_LOGIC := '0';
116 116 -----------------------------------------------------------------------------
117 117 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 118 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 119
120 120 -- CONSTANTS
121 121 CONSTANT CFG_PADTECH : INTEGER := inferred;
122 122 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
123 123 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
124 124 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
125 125
126 126 SIGNAL apbi_ext : apb_slv_in_type;
127 127 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
128 128 SIGNAL ahbi_s_ext : ahb_slv_in_type;
129 129 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
130 130 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
131 131 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
132 132
133 133 -- Spacewire signals
134 134 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 135 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 136 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 137 SIGNAL spw_rxtxclk : STD_ULOGIC;
138 138 SIGNAL spw_rxclkn : STD_ULOGIC;
139 139 SIGNAL spw_clk : STD_LOGIC;
140 140 SIGNAL swni : grspw_in_type;
141 141 SIGNAL swno : grspw_out_type;
142 142
143 143 --GPIO
144 144 SIGNAL gpioi : gpio_in_type;
145 145 SIGNAL gpioo : gpio_out_type;
146 146
147 147 -- AD Converter ADS7886
148 148 SIGNAL sample : Samples14v(8 DOWNTO 0);
149 149 SIGNAL sample_s : Samples(8 DOWNTO 0);
150 150 SIGNAL sample_val : STD_LOGIC;
151 151 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
152 152
153 153 -----------------------------------------------------------------------------
154 154 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 155
156 156 -----------------------------------------------------------------------------
157 157 SIGNAL rstn_25 : STD_LOGIC;
158 158 SIGNAL rstn_24 : STD_LOGIC;
159 159
160 160 SIGNAL LFR_soft_rstn : STD_LOGIC;
161 161 SIGNAL LFR_rstn : STD_LOGIC;
162 162
163 163 SIGNAL ADC_smpclk_s : STD_LOGIC;
164 164 ----------------------------------------------------------------------------
165 165 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 166 SIGNAL nSRAM_READY : STD_LOGIC;
167 167
168 168 BEGIN -- beh
169 169
170 170 -----------------------------------------------------------------------------
171 171 -- CLK
172 172 -----------------------------------------------------------------------------
173 173 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
174 174 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
175 175
176 176 PROCESS(clk100MHz)
177 177 BEGIN
178 178 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
179 179 clk_50_s <= NOT clk_50_s;
180 180 END IF;
181 181 END PROCESS;
182 182
183 183 PROCESS(clk_50_s)
184 184 BEGIN
185 185 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
186 186 clk_25 <= NOT clk_25;
187 187 END IF;
188 188 END PROCESS;
189 189
190 190 PROCESS(clk49_152MHz)
191 191 BEGIN
192 192 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
193 193 clk_24 <= NOT clk_24;
194 194 END IF;
195 195 END PROCESS;
196 196
197 197 -----------------------------------------------------------------------------
198 198
199 199 PROCESS (clk_25, rstn_25)
200 200 BEGIN -- PROCESS
201 201 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
202 202 led(0) <= '0';
203 203 led(1) <= '0';
204 204 led(2) <= '0';
205 205 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
206 206 led(0) <= '0';
207 207 led(1) <= '1';
208 208 led(2) <= '1';
209 209 END IF;
210 210 END PROCESS;
211 211
212 212 --
213 213 leon3_soc_1 : leon3_soc
214 214 GENERIC MAP (
215 215 fabtech => apa3e,
216 216 memtech => apa3e,
217 217 padtech => inferred,
218 218 clktech => inferred,
219 219 disas => 0,
220 220 dbguart => 0,
221 221 pclow => 2,
222 222 clk_freq => 25000,
223 223 IS_RADHARD => 0,
224 224 NB_CPU => 1,
225 225 ENABLE_FPU => 1,
226 226 FPU_NETLIST => 0,
227 227 ENABLE_DSU => 1,
228 228 ENABLE_AHB_UART => 1,
229 229 ENABLE_APB_UART => 1,
230 230 ENABLE_IRQMP => 1,
231 231 ENABLE_GPT => 1,
232 232 NB_AHB_MASTER => NB_AHB_MASTER,
233 233 NB_AHB_SLAVE => NB_AHB_SLAVE,
234 234 NB_APB_SLAVE => NB_APB_SLAVE,
235 235 ADDRESS_SIZE => 20,
236 236 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
237 237 BYPASS_EDAC_MEMCTRLR => '0',
238 238 SRBANKSZ => 9)
239 239 PORT MAP (
240 240 clk => clk_25,
241 241 reset => rstn_25,
242 242 errorn => OPEN,
243 243
244 244 ahbrxd => TAG1,
245 245 ahbtxd => TAG3,
246 246 urxd1 => TAG2,
247 247 utxd1 => TAG4,
248 248
249 249 address => address,
250 250 data => data,
251 251 nSRAM_BE0 => nSRAM_BE0,
252 252 nSRAM_BE1 => nSRAM_BE1,
253 253 nSRAM_BE2 => nSRAM_BE2,
254 254 nSRAM_BE3 => nSRAM_BE3,
255 255 nSRAM_WE => nSRAM_WE,
256 256 nSRAM_CE => nSRAM_CE_s,
257 257 nSRAM_OE => nSRAM_OE,
258 258 nSRAM_READY => nSRAM_READY,
259 SRAM_MBE => '0',
259 SRAM_MBE => OPEN,
260 260
261 261 apbi_ext => apbi_ext,
262 262 apbo_ext => apbo_ext,
263 263 ahbi_s_ext => ahbi_s_ext,
264 264 ahbo_s_ext => ahbo_s_ext,
265 265 ahbi_m_ext => ahbi_m_ext,
266 266 ahbo_m_ext => ahbo_m_ext);
267 267
268 268 PROCESS (clk_25, rstn_25)
269 269 BEGIN -- PROCESS
270 270 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
271 271 nSRAM_READY <= '1';
272 272 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
273 273 nSRAM_READY <= '1';
274 274 END IF;
275 275 END PROCESS;
276 276
277 277 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
278 278 nSRAM_CE <= not nSRAM_CE_s(0);
279 279 END GENERATE;
280 280
281 281 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
282 282 nSRAM_CE <= nSRAM_CE_s(0);
283 283 END GENERATE;
284 284
285 285 -------------------------------------------------------------------------------
286 286 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
287 287 -------------------------------------------------------------------------------
288 288 apb_lfr_management_1 : apb_lfr_management
289 289 GENERIC MAP (
290 290 tech => apa3e,
291 291 pindex => 6,
292 292 paddr => 6,
293 293 pmask => 16#fff#,
294 294 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
295 295 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
296 296 PORT MAP (
297 297 clk25MHz => clk_25,
298 298 resetn_25MHz => rstn_25, -- TODO
299 299 -- clk24_576MHz => clk_24, -- 49.152MHz/2
300 300 -- resetn_24_576MHz => rstn_24, -- TODO
301 301
302 302 grspw_tick => swno.tickout,
303 303 apbi => apbi_ext,
304 304 apbo => apbo_ext(6),
305 305
306 306 HK_sample => sample_s(8),
307 307 HK_val => sample_val,
308 308 HK_sel => HK_SEL,
309 309
310 310 DAC_SDO => DAC_SDO,
311 311 DAC_SCK => DAC_SCK,
312 312 DAC_SYNC => DAC_SYNC,
313 313 DAC_CAL_EN => DAC_CAL_EN,
314 314
315 315 coarse_time => coarse_time,
316 316 fine_time => fine_time,
317 317 LFR_soft_rstn => LFR_soft_rstn
318 318 );
319 319
320 320 -----------------------------------------------------------------------
321 321 --- SpaceWire --------------------------------------------------------
322 322 -----------------------------------------------------------------------
323 323
324 324 -- SPW_EN <= '1';
325 325
326 326 spw_clk <= clk_50_s;
327 327 spw_rxtxclk <= spw_clk;
328 328 spw_rxclkn <= NOT spw_rxtxclk;
329 329
330 330 -- PADS for SPW1
331 331 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
332 332 PORT MAP (spw1_din, dtmp(0));
333 333 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
334 334 PORT MAP (spw1_sin, stmp(0));
335 335 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
336 336 PORT MAP (spw1_dout, swno.d(0));
337 337 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
338 338 PORT MAP (spw1_sout, swno.s(0));
339 339 -- PADS FOR SPW2
340 340 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
341 341 PORT MAP (spw2_din, dtmp(1));
342 342 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
343 343 PORT MAP (spw2_sin, stmp(1));
344 344 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
345 345 PORT MAP (spw2_dout, swno.d(1));
346 346 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
347 347 PORT MAP (spw2_sout, swno.s(1));
348 348
349 349 -- GRSPW PHY
350 350 --spw1_input: if CFG_SPW_GRSPW = 1 generate
351 351 spw_inputloop : FOR j IN 0 TO 1 GENERATE
352 352 spw_phy0 : grspw_phy
353 353 GENERIC MAP(
354 354 tech => apa3e,
355 355 rxclkbuftype => 1,
356 356 scantest => 0)
357 357 PORT MAP(
358 358 rxrst => swno.rxrst,
359 359 di => dtmp(j),
360 360 si => stmp(j),
361 361 rxclko => spw_rxclk(j),
362 362 do => swni.d(j),
363 363 ndo => swni.nd(j*5+4 DOWNTO j*5),
364 364 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
365 365 END GENERATE spw_inputloop;
366 366
367 367 -- SPW core
368 368 sw0 : grspwm GENERIC MAP(
369 369 tech => apa3e,
370 370 hindex => 1,
371 371 pindex => 5,
372 372 paddr => 5,
373 373 pirq => 11,
374 374 sysfreq => 25000, -- CPU_FREQ
375 375 rmap => 1,
376 376 rmapcrc => 1,
377 377 fifosize1 => 16,
378 378 fifosize2 => 16,
379 379 rxclkbuftype => 1,
380 380 rxunaligned => 0,
381 381 rmapbufs => 4,
382 382 ft => 0,
383 383 netlist => 0,
384 384 ports => 2,
385 385 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
386 386 memtech => apa3e,
387 387 destkey => 2,
388 388 spwcore => 1
389 389 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
390 390 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
391 391 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
392 392 )
393 393 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
394 394 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
395 395 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
396 396 swni, swno);
397 397
398 398 swni.tickin <= '0';
399 399 swni.rmapen <= '1';
400 400 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
401 401 swni.tickinraw <= '0';
402 402 swni.timein <= (OTHERS => '0');
403 403 swni.dcrstval <= (OTHERS => '0');
404 404 swni.timerrstval <= (OTHERS => '0');
405 405
406 406 -------------------------------------------------------------------------------
407 407 -- LFR ------------------------------------------------------------------------
408 408 -------------------------------------------------------------------------------
409 409 LFR_rstn <= LFR_soft_rstn AND rstn_25;
410 410
411 411 lpp_lfr_1 : lpp_lfr
412 412 GENERIC MAP (
413 413 Mem_use => use_RAM,
414 414 tech => inferred,
415 415 nb_data_by_buffer_size => 32,
416 416 --nb_word_by_buffer_size => 30,
417 417 nb_snapshot_param_size => 32,
418 418 delta_vector_size => 32,
419 419 delta_vector_size_f0_2 => 7, -- log2(96)
420 420 pindex => 15,
421 421 paddr => 15,
422 422 pmask => 16#fff#,
423 423 pirq_ms => 6,
424 424 pirq_wfp => 14,
425 425 hindex => 2,
426 426 top_lfr_version => X"010153", -- aa.bb.cc version
427 427 -- AA : BOARD NUMBER
428 428 -- 0 => MINI_LFR
429 429 -- 1 => EM
430 430 DEBUG_FORCE_DATA_DMA => 0)
431 431 PORT MAP (
432 432 clk => clk_25,
433 433 rstn => LFR_rstn,
434 434 sample_B => sample_s(2 DOWNTO 0),
435 435 sample_E => sample_s(7 DOWNTO 3),
436 436 sample_val => sample_val,
437 437 apbi => apbi_ext,
438 438 apbo => apbo_ext(15),
439 439 ahbi => ahbi_m_ext,
440 440 ahbo => ahbo_m_ext(2),
441 441 coarse_time => coarse_time,
442 442 fine_time => fine_time,
443 443 data_shaping_BW => bias_fail_sw,
444 444 debug_vector => OPEN,
445 445 debug_vector_ms => OPEN); --,
446 446 --observation_vector_0 => OPEN,
447 447 --observation_vector_1 => OPEN,
448 448 --observation_reg => observation_reg);
449 449
450 450
451 451 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
452 452 sample_s(I) <= sample(I) & '0' & '0';
453 453 END GENERATE all_sample;
454 454 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
455 455
456 456 -----------------------------------------------------------------------------
457 457 --
458 458 -----------------------------------------------------------------------------
459 459 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
460 460 GENERIC MAP (
461 461 ChanelCount => 9,
462 462 ncycle_cnv_high => 12,
463 463 ncycle_cnv => 25,
464 464 FILTER_ENABLED => 16#FF#)
465 465 PORT MAP (
466 466 cnv_clk => clk_24,
467 467 cnv_rstn => rstn_24,
468 468 cnv => ADC_smpclk_s,
469 469 clk => clk_25,
470 470 rstn => rstn_25,
471 471 ADC_data => ADC_data,
472 472 ADC_nOE => ADC_OEB_bar_CH_s,
473 473 sample => sample,
474 474 sample_val => sample_val);
475 475
476 476 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
477 477
478 478 ADC_smpclk <= ADC_smpclk_s;
479 479 HK_smpclk <= ADC_smpclk_s;
480 480
481 481 TAG8 <= ADC_smpclk_s;
482 482
483 483 -----------------------------------------------------------------------------
484 484 -- HK
485 485 -----------------------------------------------------------------------------
486 486 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
487 487
488 488 END beh;
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