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Remove arbitration in front of FFT based on Pong Status...
pellion -
r384:328a814d7018 (MINI-LFR) WFP_MS-0-1-20 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 BEGIN -- beh
180 180
181 181 -----------------------------------------------------------------------------
182 182 -- CLK
183 183 -----------------------------------------------------------------------------
184 184
185 185 PROCESS(clk_50)
186 186 BEGIN
187 187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 188 clk_50_s <= NOT clk_50_s;
189 189 END IF;
190 190 END PROCESS;
191 191
192 192 PROCESS(clk_50_s)
193 193 BEGIN
194 194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 195 clk_25 <= NOT clk_25;
196 196 END IF;
197 197 END PROCESS;
198 198
199 199 PROCESS(clk_49)
200 200 BEGIN
201 201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 202 clk_24 <= NOT clk_24;
203 203 END IF;
204 204 END PROCESS;
205 205
206 206 -----------------------------------------------------------------------------
207 207
208 208 PROCESS (clk_25, reset)
209 209 BEGIN -- PROCESS
210 210 IF reset = '0' THEN -- asynchronous reset (active low)
211 211 LED0 <= '0';
212 212 LED1 <= '0';
213 213 LED2 <= '0';
214 214 --IO1 <= '0';
215 215 --IO2 <= '1';
216 216 --IO3 <= '0';
217 217 --IO4 <= '0';
218 218 --IO5 <= '0';
219 219 --IO6 <= '0';
220 220 --IO7 <= '0';
221 221 --IO8 <= '0';
222 222 --IO9 <= '0';
223 223 --IO10 <= '0';
224 224 --IO11 <= '0';
225 225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 226 LED0 <= '0';
227 227 LED1 <= '1';
228 228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 229 --IO1 <= '1';
230 230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 231 --IO3 <= ADC_SDO(0);
232 232 --IO4 <= ADC_SDO(1);
233 233 --IO5 <= ADC_SDO(2);
234 234 --IO6 <= ADC_SDO(3);
235 235 --IO7 <= ADC_SDO(4);
236 236 --IO8 <= ADC_SDO(5);
237 237 --IO9 <= ADC_SDO(6);
238 238 --IO10 <= ADC_SDO(7);
239 239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 240 END IF;
241 241 END PROCESS;
242 242
243 243 PROCESS (clk_24, reset)
244 244 BEGIN -- PROCESS
245 245 IF reset = '0' THEN -- asynchronous reset (active low)
246 246 I00_s <= '0';
247 247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 248 I00_s <= NOT I00_s ;
249 249 END IF;
250 250 END PROCESS;
251 251 -- IO0 <= I00_s;
252 252
253 253 --UARTs
254 254 nCTS1 <= '1';
255 255 nCTS2 <= '1';
256 256 nDCD2 <= '1';
257 257
258 258 --EXT CONNECTOR
259 259
260 260 --SPACE WIRE
261 261
262 262 leon3_soc_1 : leon3_soc
263 263 GENERIC MAP (
264 264 fabtech => apa3e,
265 265 memtech => apa3e,
266 266 padtech => inferred,
267 267 clktech => inferred,
268 268 disas => 0,
269 269 dbguart => 0,
270 270 pclow => 2,
271 271 clk_freq => 25000,
272 272 NB_CPU => 1,
273 273 ENABLE_FPU => 1,
274 274 FPU_NETLIST => 0,
275 275 ENABLE_DSU => 1,
276 276 ENABLE_AHB_UART => 1,
277 277 ENABLE_APB_UART => 1,
278 278 ENABLE_IRQMP => 1,
279 279 ENABLE_GPT => 1,
280 280 NB_AHB_MASTER => NB_AHB_MASTER,
281 281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 282 NB_APB_SLAVE => NB_APB_SLAVE)
283 283 PORT MAP (
284 284 clk => clk_25,
285 285 reset => reset,
286 286 errorn => errorn,
287 287 ahbrxd => TXD1,
288 288 ahbtxd => RXD1,
289 289 urxd1 => TXD2,
290 290 utxd1 => RXD2,
291 291 address => SRAM_A,
292 292 data => SRAM_DQ,
293 293 nSRAM_BE0 => SRAM_nBE(0),
294 294 nSRAM_BE1 => SRAM_nBE(1),
295 295 nSRAM_BE2 => SRAM_nBE(2),
296 296 nSRAM_BE3 => SRAM_nBE(3),
297 297 nSRAM_WE => SRAM_nWE,
298 298 nSRAM_CE => SRAM_CE,
299 299 nSRAM_OE => SRAM_nOE,
300 300
301 301 apbi_ext => apbi_ext,
302 302 apbo_ext => apbo_ext,
303 303 ahbi_s_ext => ahbi_s_ext,
304 304 ahbo_s_ext => ahbo_s_ext,
305 305 ahbi_m_ext => ahbi_m_ext,
306 306 ahbo_m_ext => ahbo_m_ext);
307 307
308 308 -------------------------------------------------------------------------------
309 309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 310 -------------------------------------------------------------------------------
311 311 apb_lfr_time_management_1 : apb_lfr_time_management
312 312 GENERIC MAP (
313 313 pindex => 6,
314 314 paddr => 6,
315 315 pmask => 16#fff#,
316 316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 318 PORT MAP (
319 319 clk25MHz => clk_25,
320 320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 321 resetn => reset,
322 322 grspw_tick => swno.tickout,
323 323 apbi => apbi_ext,
324 324 apbo => apbo_ext(6),
325 325 coarse_time => coarse_time,
326 326 fine_time => fine_time);
327 327
328 328 -----------------------------------------------------------------------
329 329 --- SpaceWire --------------------------------------------------------
330 330 -----------------------------------------------------------------------
331 331
332 332 SPW_EN <= '1';
333 333
334 334 spw_clk <= clk_50_s;
335 335 spw_rxtxclk <= spw_clk;
336 336 spw_rxclkn <= NOT spw_rxtxclk;
337 337
338 338 -- PADS for SPW1
339 339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 347 -- PADS FOR SPW2
348 348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 351 PORT MAP (SPW_RED_DIN, stmp(1));
352 352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356 356
357 357 -- GRSPW PHY
358 358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 360 spw_phy0 : grspw_phy
361 361 GENERIC MAP(
362 362 tech => apa3e,
363 363 rxclkbuftype => 1,
364 364 scantest => 0)
365 365 PORT MAP(
366 366 rxrst => swno.rxrst,
367 367 di => dtmp(j),
368 368 si => stmp(j),
369 369 rxclko => spw_rxclk(j),
370 370 do => swni.d(j),
371 371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 373 END GENERATE spw_inputloop;
374 374
375 375 -- SPW core
376 376 sw0 : grspwm GENERIC MAP(
377 377 tech => apa3e,
378 378 hindex => 1,
379 379 pindex => 5,
380 380 paddr => 5,
381 381 pirq => 11,
382 382 sysfreq => 25000, -- CPU_FREQ
383 383 rmap => 1,
384 384 rmapcrc => 1,
385 385 fifosize1 => 16,
386 386 fifosize2 => 16,
387 387 rxclkbuftype => 1,
388 388 rxunaligned => 0,
389 389 rmapbufs => 4,
390 390 ft => 0,
391 391 netlist => 0,
392 392 ports => 2,
393 393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 394 memtech => apa3e,
395 395 destkey => 2,
396 396 spwcore => 1
397 397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 400 )
401 401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 404 swni, swno);
405 405
406 406 swni.tickin <= '0';
407 407 swni.rmapen <= '1';
408 408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 409 swni.tickinraw <= '0';
410 410 swni.timein <= (OTHERS => '0');
411 411 swni.dcrstval <= (OTHERS => '0');
412 412 swni.timerrstval <= (OTHERS => '0');
413 413
414 414 -------------------------------------------------------------------------------
415 415 -- LFR ------------------------------------------------------------------------
416 416 -------------------------------------------------------------------------------
417 417 lpp_lfr_1 : lpp_lfr
418 418 GENERIC MAP (
419 419 Mem_use => use_RAM,
420 420 nb_data_by_buffer_size => 32,
421 421 nb_word_by_buffer_size => 30,
422 422 nb_snapshot_param_size => 32,
423 423 delta_vector_size => 32,
424 424 delta_vector_size_f0_2 => 7, -- log2(96)
425 425 pindex => 15,
426 426 paddr => 15,
427 427 pmask => 16#fff#,
428 428 pirq_ms => 6,
429 429 pirq_wfp => 14,
430 430 hindex => 2,
431 top_lfr_version => X"000112") -- aa.bb.cc version
431 top_lfr_version => X"000114") -- aa.bb.cc version
432 432 PORT MAP (
433 433 clk => clk_25,
434 434 rstn => reset,
435 435 sample_B => sample_s(2 DOWNTO 0),
436 436 sample_E => sample_s(7 DOWNTO 3),
437 437 sample_val => sample_val,
438 438 apbi => apbi_ext,
439 439 apbo => apbo_ext(15),
440 440 ahbi => ahbi_m_ext,
441 441 ahbo => ahbo_m_ext(2),
442 442 coarse_time => coarse_time,
443 443 fine_time => fine_time,
444 444 data_shaping_BW => bias_fail_sw_sig,
445 445 observation_vector_0=> observation_vector_0,
446 446 observation_vector_1 => observation_vector_1,
447 447 observation_reg => observation_reg);
448 448
449 449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
450 450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
451 451 END GENERATE all_sample;
452 452
453 453
454 454
455 455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
456 456 GENERIC MAP(
457 457 ChannelCount => 8,
458 458 SampleNbBits => 14,
459 459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
460 460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
461 461 PORT MAP (
462 462 -- CONV
463 463 cnv_clk => clk_24,
464 464 cnv_rstn => reset,
465 465 cnv => ADC_nCS_sig,
466 466 -- DATA
467 467 clk => clk_25,
468 468 rstn => reset,
469 469 sck => ADC_CLK_sig,
470 470 sdo => ADC_SDO_sig,
471 471 -- SAMPLE
472 472 sample => sample,
473 473 sample_val => sample_val);
474 474
475 475 --IO10 <= ADC_SDO_sig(5);
476 476 --IO9 <= ADC_SDO_sig(4);
477 477 --IO8 <= ADC_SDO_sig(3);
478 478
479 479 ADC_nCS <= ADC_nCS_sig;
480 480 ADC_CLK <= ADC_CLK_sig;
481 481 ADC_SDO_sig <= ADC_SDO;
482 482
483 483 ----------------------------------------------------------------------
484 484 --- GPIO -----------------------------------------------------------
485 485 ----------------------------------------------------------------------
486 486
487 487 grgpio0 : grgpio
488 488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
489 489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
490 490
491 491 --pio_pad_0 : iopad
492 492 -- GENERIC MAP (tech => CFG_PADTECH)
493 493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
494 494 --pio_pad_1 : iopad
495 495 -- GENERIC MAP (tech => CFG_PADTECH)
496 496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
497 497 --pio_pad_2 : iopad
498 498 -- GENERIC MAP (tech => CFG_PADTECH)
499 499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
500 500 --pio_pad_3 : iopad
501 501 -- GENERIC MAP (tech => CFG_PADTECH)
502 502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
503 503 --pio_pad_4 : iopad
504 504 -- GENERIC MAP (tech => CFG_PADTECH)
505 505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
506 506 --pio_pad_5 : iopad
507 507 -- GENERIC MAP (tech => CFG_PADTECH)
508 508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
509 509 --pio_pad_6 : iopad
510 510 -- GENERIC MAP (tech => CFG_PADTECH)
511 511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
512 512 --pio_pad_7 : iopad
513 513 -- GENERIC MAP (tech => CFG_PADTECH)
514 514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
515 515
516 516 PROCESS (clk_25, reset)
517 517 BEGIN -- PROCESS
518 518 IF reset = '0' THEN -- asynchronous reset (active low)
519 519 IO0 <= '0';
520 520 IO1 <= '0';
521 521 IO2 <= '0';
522 522 IO3 <= '0';
523 523 IO4 <= '0';
524 524 IO5 <= '0';
525 525 IO6 <= '0';
526 526 IO7 <= '0';
527 527 IO8 <= '0';
528 528 IO9 <= '0';
529 529 IO10 <= '0';
530 530 IO11 <= '0';
531 531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
532 532 CASE gpioo.dout(2 DOWNTO 0) IS
533 533 WHEN "011" =>
534 534 IO0 <= observation_reg(0 );
535 535 IO1 <= observation_reg(1 );
536 536 IO2 <= observation_reg(2 );
537 537 IO3 <= observation_reg(3 );
538 538 IO4 <= observation_reg(4 );
539 539 IO5 <= observation_reg(5 );
540 540 IO6 <= observation_reg(6 );
541 541 IO7 <= observation_reg(7 );
542 542 IO8 <= observation_reg(8 );
543 543 IO9 <= observation_reg(9 );
544 544 IO10 <= observation_reg(10);
545 545 IO11 <= observation_reg(11);
546 546 WHEN "001" =>
547 547 IO0 <= observation_reg(0 + 12);
548 548 IO1 <= observation_reg(1 + 12);
549 549 IO2 <= observation_reg(2 + 12);
550 550 IO3 <= observation_reg(3 + 12);
551 551 IO4 <= observation_reg(4 + 12);
552 552 IO5 <= observation_reg(5 + 12);
553 553 IO6 <= observation_reg(6 + 12);
554 554 IO7 <= observation_reg(7 + 12);
555 555 IO8 <= observation_reg(8 + 12);
556 556 IO9 <= observation_reg(9 + 12);
557 557 IO10 <= observation_reg(10 + 12);
558 558 IO11 <= observation_reg(11 + 12);
559 559 WHEN "010" =>
560 560 IO0 <= observation_reg(0 + 12 + 12);
561 561 IO1 <= observation_reg(1 + 12 + 12);
562 562 IO2 <= observation_reg(2 + 12 + 12);
563 563 IO3 <= observation_reg(3 + 12 + 12);
564 564 IO4 <= observation_reg(4 + 12 + 12);
565 565 IO5 <= observation_reg(5 + 12 + 12);
566 566 IO6 <= observation_reg(6 + 12 + 12);
567 567 IO7 <= observation_reg(7 + 12 + 12);
568 568 IO8 <= '0';
569 569 IO9 <= '0';
570 570 IO10 <= '0';
571 571 IO11 <= '0';
572 572 WHEN "000" =>
573 573 IO0 <= observation_vector_0(0 );
574 574 IO1 <= observation_vector_0(1 );
575 575 IO2 <= observation_vector_0(2 );
576 576 IO3 <= observation_vector_0(3 );
577 577 IO4 <= observation_vector_0(4 );
578 578 IO5 <= observation_vector_0(5 );
579 579 IO6 <= observation_vector_0(6 );
580 580 IO7 <= observation_vector_0(7 );
581 581 IO8 <= observation_vector_0(8 );
582 582 IO9 <= observation_vector_0(9 );
583 583 IO10 <= observation_vector_0(10);
584 584 IO11 <= observation_vector_0(11);
585 585 WHEN "100" =>
586 586 IO0 <= observation_vector_1(0 );
587 587 IO1 <= observation_vector_1(1 );
588 588 IO2 <= observation_vector_1(2 );
589 589 IO3 <= observation_vector_1(3 );
590 590 IO4 <= observation_vector_1(4 );
591 591 IO5 <= observation_vector_1(5 );
592 592 IO6 <= observation_vector_1(6 );
593 593 IO7 <= observation_vector_1(7 );
594 594 IO8 <= observation_vector_1(8 );
595 595 IO9 <= observation_vector_1(9 );
596 596 IO10 <= observation_vector_1(10);
597 597 IO11 <= observation_vector_1(11);
598 598 WHEN OTHERS => NULL;
599 599 END CASE;
600 600
601 601 END IF;
602 602 END PROCESS;
603 603
604 604 END beh;
Show file before | Show file after | Hide comments
@@ -1,972 +1,996
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_memory.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.spectral_matrix_package.ALL;
9 9 USE lpp.lpp_dma_pkg.ALL;
10 10 USE lpp.lpp_Header.ALL;
11 11 USE lpp.lpp_matrix.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.lpp_fft.ALL;
15 15 USE lpp.fft_components.ALL;
16 16
17 17 ENTITY lpp_lfr_ms IS
18 18 GENERIC (
19 19 Mem_use : INTEGER := use_RAM
20 20 );
21 21 PORT (
22 22 clk : IN STD_LOGIC;
23 23 rstn : IN STD_LOGIC;
24 24
25 25 ---------------------------------------------------------------------------
26 26 -- DATA INPUT
27 27 ---------------------------------------------------------------------------
28 28 -- TIME
29 29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 31 --
32 32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 34 --
35 35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 37 --
38 38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40
41 41 ---------------------------------------------------------------------------
42 42 -- DMA
43 43 ---------------------------------------------------------------------------
44 44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 46 dma_valid : OUT STD_LOGIC;
47 47 dma_valid_burst : OUT STD_LOGIC;
48 48 dma_ren : IN STD_LOGIC;
49 49 dma_done : IN STD_LOGIC;
50 50
51 51 -- Reg out
52 52 ready_matrix_f0 : OUT STD_LOGIC;
53 53 ready_matrix_f1 : OUT STD_LOGIC;
54 54 ready_matrix_f2 : OUT STD_LOGIC;
55 55 error_bad_component_error : OUT STD_LOGIC;
56 56 error_buffer_full : OUT STD_LOGIC;
57 57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58 58
59 59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60 --
61 61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63 63
64 64 -- Reg In
65 65 status_ready_matrix_f0 : IN STD_LOGIC;
66 66 status_ready_matrix_f1 : IN STD_LOGIC;
67 67 status_ready_matrix_f2 : IN STD_LOGIC;
68 68
69 69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
70 70 config_active_interruption_onError : IN STD_LOGIC;
71 71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
78 78
79 79 );
80 80 END;
81 81
82 82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83 83
84 84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 89
90 90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 95
96 96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 100
101 101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 102
103 103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 107
108 108 SIGNAL error_wen_f0 : STD_LOGIC;
109 109 SIGNAL error_wen_f1 : STD_LOGIC;
110 110 SIGNAL error_wen_f2 : STD_LOGIC;
111 111
112 112 SIGNAL one_sample_f1_full : STD_LOGIC;
113 113 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 114 SIGNAL one_sample_f2_full : STD_LOGIC;
115 115 SIGNAL one_sample_f2_wen : STD_LOGIC;
116 116
117 117 -----------------------------------------------------------------------------
118 118 -- FSM / SWITCH SELECT CHANNEL
119 119 -----------------------------------------------------------------------------
120 120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 121 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123 123
124 124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 128
129 129 -----------------------------------------------------------------------------
130 130 -- FSM LOAD FFT
131 131 -----------------------------------------------------------------------------
132 132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135 135
136 136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 137 SIGNAL sample_load : STD_LOGIC;
138 138 SIGNAL sample_valid : STD_LOGIC;
139 139 SIGNAL sample_valid_r : STD_LOGIC;
140 140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141 141
142 142
143 143 -----------------------------------------------------------------------------
144 144 -- FFT
145 145 -----------------------------------------------------------------------------
146 146 SIGNAL fft_read : STD_LOGIC;
147 147 SIGNAL fft_pong : STD_LOGIC;
148 148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 150 SIGNAL fft_data_valid : STD_LOGIC;
151 151 SIGNAL fft_ready : STD_LOGIC;
152 152 -----------------------------------------------------------------------------
153 153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 154 -----------------------------------------------------------------------------
155 155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 158 SIGNAL current_fifo_empty : STD_LOGIC;
159 159 SIGNAL current_fifo_locked : STD_LOGIC;
160 160 SIGNAL current_fifo_full : STD_LOGIC;
161 161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 162
163 163 -----------------------------------------------------------------------------
164 164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 172 -----------------------------------------------------------------------------
173 173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 176
177 177 SIGNAL SM_correlation_start : STD_LOGIC;
178 178 SIGNAL SM_correlation_auto : STD_LOGIC;
179 179 SIGNAL SM_correlation_done : STD_LOGIC;
180 180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 183 SIGNAL SM_correlation_begin : STD_LOGIC;
184 184
185 185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188 188
189 189 SIGNAL current_matrix_write : STD_LOGIC;
190 190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 191 -----------------------------------------------------------------------------
192 192 SIGNAL fifo_0_ready : STD_LOGIC;
193 193 SIGNAL fifo_1_ready : STD_LOGIC;
194 194 SIGNAL fifo_ongoing : STD_LOGIC;
195 195
196 196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 200 -----------------------------------------------------------------------------
201 201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
207 207
208 208 -----------------------------------------------------------------------------
209 209 -- TIME REG & INFOs
210 210 -----------------------------------------------------------------------------
211 211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 212
213 213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
217 217
218 218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222 222
223 223 --SIGNAL time_update_f0_A : STD_LOGIC;
224 224 --SIGNAL time_update_f0_B : STD_LOGIC;
225 225 --SIGNAL time_update_f1 : STD_LOGIC;
226 226 --SIGNAL time_update_f2 : STD_LOGIC;
227 227 --
228 228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
231 231
232 232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
235 235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
236 236 -----------------------------------------------------------------------------
237 SIGNAL ping_npong : STD_LOGIC;
238 SIGNAL sample_load_reg : STD_LOGIC;
237 SIGNAL fft_ongoing_counter : STD_LOGIC_VECTOR(1 DOWNTO 0);
238
239 SIGNAL fft_ready_reg : STD_LOGIC;
240 SIGNAL fft_ready_rising_down : STD_LOGIC;
241
242 SIGNAL sample_load_reg : STD_LOGIC;
243 SIGNAL sample_load_rising_down : STD_LOGIC;
239 244
240 245 BEGIN
241 246
242 247
243 248 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
244 249
245 250
246 251 switch_f0_inst : spectral_matrix_switch_f0
247 252 PORT MAP (
248 253 clk => clk,
249 254 rstn => rstn,
250 255
251 256 sample_wen => sample_f0_wen,
252 257
253 258 fifo_A_empty => sample_f0_A_empty,
254 259 fifo_A_full => sample_f0_A_full,
255 260 fifo_A_wen => sample_f0_A_wen,
256 261
257 262 fifo_B_empty => sample_f0_B_empty,
258 263 fifo_B_full => sample_f0_B_full,
259 264 fifo_B_wen => sample_f0_B_wen,
260 265
261 266 error_wen => error_wen_f0); -- TODO
262 267
263 268 -----------------------------------------------------------------------------
264 269 -- FIFO IN
265 270 -----------------------------------------------------------------------------
266 271 lppFIFOxN_f0_a : lppFIFOxN
267 272 GENERIC MAP (
268 273 tech => 0,
269 274 Mem_use => Mem_use,
270 275 Data_sz => 16,
271 276 Addr_sz => 8,
272 277 FifoCnt => 5)
273 278 PORT MAP (
274 279 clk => clk,
275 280 rstn => rstn,
276 281
277 282 ReUse => (OTHERS => '0'),
278 283
279 284 wen => sample_f0_A_wen,
280 285 wdata => sample_f0_wdata,
281 286
282 287 ren => sample_f0_A_ren,
283 288 rdata => sample_f0_A_rdata,
284 289
285 290 empty => sample_f0_A_empty,
286 291 full => sample_f0_A_full,
287 292 almost_full => OPEN);
288 293
289 294 lppFIFOxN_f0_b : lppFIFOxN
290 295 GENERIC MAP (
291 296 tech => 0,
292 297 Mem_use => Mem_use,
293 298 Data_sz => 16,
294 299 Addr_sz => 8,
295 300 FifoCnt => 5)
296 301 PORT MAP (
297 302 clk => clk,
298 303 rstn => rstn,
299 304
300 305 ReUse => (OTHERS => '0'),
301 306
302 307 wen => sample_f0_B_wen,
303 308 wdata => sample_f0_wdata,
304 309 ren => sample_f0_B_ren,
305 310 rdata => sample_f0_B_rdata,
306 311 empty => sample_f0_B_empty,
307 312 full => sample_f0_B_full,
308 313 almost_full => OPEN);
309 314
310 315 lppFIFOxN_f1 : lppFIFOxN
311 316 GENERIC MAP (
312 317 tech => 0,
313 318 Mem_use => Mem_use,
314 319 Data_sz => 16,
315 320 Addr_sz => 8,
316 321 FifoCnt => 5)
317 322 PORT MAP (
318 323 clk => clk,
319 324 rstn => rstn,
320 325
321 326 ReUse => (OTHERS => '0'),
322 327
323 328 wen => sample_f1_wen,
324 329 wdata => sample_f1_wdata,
325 330 ren => sample_f1_ren,
326 331 rdata => sample_f1_rdata,
327 332 empty => sample_f1_empty,
328 333 full => sample_f1_full,
329 334 almost_full => sample_f1_almost_full);
330 335
331 336
332 337 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
333 338
334 339 PROCESS (clk, rstn)
335 340 BEGIN -- PROCESS
336 341 IF rstn = '0' THEN -- asynchronous reset (active low)
337 342 one_sample_f1_full <= '0';
338 343 error_wen_f1 <= '0';
339 344 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
340 345 IF sample_f1_full = "00000" THEN
341 346 one_sample_f1_full <= '0';
342 347 ELSE
343 348 one_sample_f1_full <= '1';
344 349 END IF;
345 350 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
346 351 END IF;
347 352 END PROCESS;
348 353
349 354
350 355 lppFIFOxN_f2 : lppFIFOxN
351 356 GENERIC MAP (
352 357 tech => 0,
353 358 Mem_use => Mem_use,
354 359 Data_sz => 16,
355 360 Addr_sz => 8,
356 361 FifoCnt => 5)
357 362 PORT MAP (
358 363 clk => clk,
359 364 rstn => rstn,
360 365
361 366 ReUse => (OTHERS => '0'),
362 367
363 368 wen => sample_f2_wen,
364 369 wdata => sample_f2_wdata,
365 370 ren => sample_f2_ren,
366 371 rdata => sample_f2_rdata,
367 372 empty => sample_f2_empty,
368 373 full => sample_f2_full,
369 374 almost_full => OPEN);
370 375
371 376
372 377 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
373 378
374 379 PROCESS (clk, rstn)
375 380 BEGIN -- PROCESS
376 381 IF rstn = '0' THEN -- asynchronous reset (active low)
377 382 one_sample_f2_full <= '0';
378 383 error_wen_f2 <= '0';
379 384 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
380 385 IF sample_f2_full = "00000" THEN
381 386 one_sample_f2_full <= '0';
382 387 ELSE
383 388 one_sample_f2_full <= '1';
384 389 END IF;
385 390 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
386 391 END IF;
387 392 END PROCESS;
388 393
389 394 -----------------------------------------------------------------------------
390 395 -- FSM SELECT CHANNEL
391 396 -----------------------------------------------------------------------------
392 397 PROCESS (clk, rstn)
393 398 BEGIN
394 399 IF rstn = '0' THEN
395 400 state_fsm_select_channel <= IDLE;
396 401 ELSIF clk'EVENT AND clk = '1' THEN
397 402 CASE state_fsm_select_channel IS
398 403 WHEN IDLE =>
399 404 IF sample_f1_full = "11111" THEN
400 405 state_fsm_select_channel <= SWITCH_F1;
401 406 ELSIF sample_f1_almost_full = "00000" THEN
402 407 IF sample_f0_A_full = "11111" THEN
403 408 state_fsm_select_channel <= SWITCH_F0_A;
404 409 ELSIF sample_f0_B_full = "11111" THEN
405 410 state_fsm_select_channel <= SWITCH_F0_B;
406 411 ELSIF sample_f2_full = "11111" THEN
407 412 state_fsm_select_channel <= SWITCH_F2;
408 413 END IF;
409 414 END IF;
410 415
411 416 WHEN SWITCH_F0_A =>
412 417 IF sample_f0_A_empty = "11111" THEN
413 418 state_fsm_select_channel <= IDLE;
414 419 END IF;
415 420 WHEN SWITCH_F0_B =>
416 421 IF sample_f0_B_empty = "11111" THEN
417 422 state_fsm_select_channel <= IDLE;
418 423 END IF;
419 424 WHEN SWITCH_F1 =>
420 425 IF sample_f1_empty = "11111" THEN
421 426 state_fsm_select_channel <= IDLE;
422 427 END IF;
423 428 WHEN SWITCH_F2 =>
424 429 IF sample_f2_empty = "11111" THEN
425 430 state_fsm_select_channel <= IDLE;
426 431 END IF;
427 432 WHEN OTHERS => NULL;
428 433 END CASE;
429 434
430 435 END IF;
431 436 END PROCESS;
432 437
433 438 PROCESS (clk, rstn)
434 439 BEGIN
435 440 IF rstn = '0' THEN
436 441 pre_state_fsm_select_channel <= IDLE;
437 442 ELSIF clk'EVENT AND clk = '1' THEN
438 443 pre_state_fsm_select_channel <= state_fsm_select_channel;
439 444 END IF;
440 445 END PROCESS;
441 446
442 447
443 448 -----------------------------------------------------------------------------
444 449 -- SWITCH SELECT CHANNEL
445 450 -----------------------------------------------------------------------------
446 451 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
447 452 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
448 453 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
449 454 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
450 455 (OTHERS => '1');
451 456
452 457 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
453 458 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
454 459 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
455 460 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
456 461 (OTHERS => '0');
457 462
458 463 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
459 464 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
460 465 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
461 466 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
462 467
463 468
464 469 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
465 470 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
466 471 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
467 472 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
468 473
469 474
470 475 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
471 476 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
472 477 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
473 478 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
474 479
475 480 -----------------------------------------------------------------------------
476 481 -- FSM LOAD FFT
477 482 -----------------------------------------------------------------------------
478 483
479 sample_ren <= sample_ren_s WHEN ping_npong = fft_pong AND sample_load = '1' ELSE
484 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = "10" ELSE
485 sample_ren_s WHEN sample_load = '1' ELSE
480 486 (OTHERS => '1');
481 487
482 488 PROCESS (clk, rstn)
483 489 BEGIN
484 490 IF rstn = '0' THEN
485 491 sample_ren_s <= (OTHERS => '1');
486 492 state_fsm_load_FFT <= IDLE;
487 493 status_MS_input <= (OTHERS => '0');
488 494 --next_state_fsm_load_FFT <= IDLE;
489 495 --sample_valid <= '0';
490 496 ELSIF clk'EVENT AND clk = '1' THEN
491 497 CASE state_fsm_load_FFT IS
492 498 WHEN IDLE =>
493 499 --sample_valid <= '0';
494 500 sample_ren_s <= (OTHERS => '1');
495 501 IF sample_full = "11111" AND sample_load = '1' THEN
496 502 state_fsm_load_FFT <= FIFO_1;
497 503 status_MS_input <= status_channel;
498 504 END IF;
499 505
500 506 WHEN FIFO_1 =>
501 507 sample_ren_s <= "1111" & NOT(sample_load);
502 508 IF sample_empty(0) = '1' THEN
503 509 sample_ren_s <= (OTHERS => '1');
504 510 state_fsm_load_FFT <= FIFO_2;
505 511 END IF;
506 512
507 513 WHEN FIFO_2 =>
508 514 sample_ren_s <= "111" & NOT(sample_load) & '1';
509 515 IF sample_empty(1) = '1' THEN
510 516 sample_ren_s <= (OTHERS => '1');
511 517 state_fsm_load_FFT <= FIFO_3;
512 518 END IF;
513 519
514 520 WHEN FIFO_3 =>
515 521 sample_ren_s <= "11" & NOT(sample_load) & "11";
516 522 IF sample_empty(2) = '1' THEN
517 523 sample_ren_s <= (OTHERS => '1');
518 524 state_fsm_load_FFT <= FIFO_4;
519 525 END IF;
520 526
521 527 WHEN FIFO_4 =>
522 528 sample_ren_s <= '1' & NOT(sample_load) & "111";
523 529 IF sample_empty(3) = '1' THEN
524 530 sample_ren_s <= (OTHERS => '1');
525 531 state_fsm_load_FFT <= FIFO_5;
526 532 END IF;
527 533
528 534 WHEN FIFO_5 =>
529 535 sample_ren_s <= NOT(sample_load) & "1111";
530 536 IF sample_empty(4) = '1' THEN
531 537 sample_ren_s <= (OTHERS => '1');
532 538 state_fsm_load_FFT <= IDLE;
533 539 END IF;
534 540 WHEN OTHERS => NULL;
535 541 END CASE;
536 542 END IF;
537 543 END PROCESS;
538 544
539 545 PROCESS (clk, rstn)
540 546 BEGIN
541 547 IF rstn = '0' THEN
542 548 sample_valid_r <= '0';
543 549 next_state_fsm_load_FFT <= IDLE;
544 550 ELSIF clk'EVENT AND clk = '1' THEN
545 551 next_state_fsm_load_FFT <= state_fsm_load_FFT;
546 552 IF sample_ren_s = "11111" THEN
547 553 sample_valid_r <= '0';
548 554 ELSE
549 555 sample_valid_r <= '1';
550 556 END IF;
551 557 END IF;
552 558 END PROCESS;
553 559
554 -- sample_valid <= sample_valid_r AND sample_load;
555 sample_valid <= sample_valid_r AND sample_load WHEN ping_npong = fft_pong ELSE '0';
560 sample_valid <= '0' WHEN fft_ongoing_counter = "10" ELSE sample_valid_r AND sample_load;
556 561
557 562 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
558 563 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
559 564 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
560 565 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
561 566 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
562 567
563 568 -----------------------------------------------------------------------------
564 569 -- FFT
565 570 -----------------------------------------------------------------------------
566 571 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
567 572 PORT MAP (
568 573 clk => clk,
569 574 rstn => rstn,
570 575 sample_valid => sample_valid,
571 576 fft_read => fft_read,
572 577 sample_data => sample_data,
573 578 sample_load => sample_load,
574 579 fft_pong => fft_pong,
575 580 fft_data_im => fft_data_im,
576 581 fft_data_re => fft_data_re,
577 582 fft_data_valid => fft_data_valid,
578 583 fft_ready => fft_ready);
579 584
580 observation_vector_0(11 DOWNTO 0) <= "0000" & --11 10 9 8
581 sample_load_reg & --7
582 ping_npong & --6
583 fft_ready & --5
584 fft_data_valid & --4
585 fft_pong & --3
586 sample_load & --2
587 fft_read & --1
588 sample_valid; --0
585 observation_vector_0(11 DOWNTO 0) <= "00" & --11 10
586 fft_ongoing_counter & --9 8
587 sample_load_rising_down & --7
588 fft_ready_rising_down & --6
589 fft_ready & --5
590 fft_data_valid & --4
591 fft_pong & --3
592 sample_load & --2
593 fft_read & --1
594 sample_valid; --0
589 595
590 596 -----------------------------------------------------------------------------
597 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
598 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
599
591 600 PROCESS (clk, rstn)
592 601 BEGIN
593 602 IF rstn = '0' THEN
594 ping_npong <= '0';
603 fft_ready_reg <= '0';
595 604 sample_load_reg <= '0';
605
606 fft_ongoing_counter <= "00";
596 607 ELSIF clk'event AND clk = '1' THEN
597 sample_load_reg <= sample_load;
598 IF sample_load_reg = '1' AND sample_load = '0' THEN
599 ping_npong <= NOT ping_npong;
608 fft_ready_reg <= fft_ready;
609 sample_load_reg <= sample_load;
610
611 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
612 CASE fft_ongoing_counter IS
613 WHEN "01" => fft_ongoing_counter <= "00";
614 WHEN "10" => fft_ongoing_counter <= "01";
615 WHEN OTHERS => NULL;
616 END CASE;
617 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
618 CASE fft_ongoing_counter IS
619 WHEN "00" => fft_ongoing_counter <= "01";
620 WHEN "01" => fft_ongoing_counter <= "10";
621 WHEN OTHERS => NULL;
622 END CASE;
600 623 END IF;
624
601 625 END IF;
602 626 END PROCESS;
603 627
604 628 -----------------------------------------------------------------------------
605 629 PROCESS (clk, rstn)
606 630 BEGIN
607 631 IF rstn = '0' THEN
608 632 state_fsm_load_MS_memory <= IDLE;
609 633 current_fifo_load <= "00001";
610 634 ELSIF clk'EVENT AND clk = '1' THEN
611 635 CASE state_fsm_load_MS_memory IS
612 636 WHEN IDLE =>
613 637 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
614 638 state_fsm_load_MS_memory <= LOAD_FIFO;
615 639 END IF;
616 640 WHEN LOAD_FIFO =>
617 641 IF current_fifo_full = '1' THEN
618 642 state_fsm_load_MS_memory <= TRASH_FFT;
619 643 END IF;
620 644 WHEN TRASH_FFT =>
621 645 IF fft_ready = '0' THEN
622 646 state_fsm_load_MS_memory <= IDLE;
623 647 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
624 648 END IF;
625 649 WHEN OTHERS => NULL;
626 650 END CASE;
627 651
628 652 END IF;
629 653 END PROCESS;
630 654
631 655 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
632 656 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
633 657 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
634 658 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
635 659 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
636 660
637 661 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
638 662 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
639 663 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
640 664 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
641 665 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
642 666
643 667 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
644 668 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
645 669 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
646 670 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
647 671 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
648 672
649 673 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
650 674
651 675 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
652 676 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
653 677 AND state_fsm_load_MS_memory = LOAD_FIFO
654 678 AND current_fifo_load(I) = '1'
655 679 ELSE '1';
656 680 END GENERATE all_fifo;
657 681
658 682 PROCESS (clk, rstn)
659 683 BEGIN
660 684 IF rstn = '0' THEN
661 685 MEM_IN_SM_wen <= (OTHERS => '1');
662 686 ELSIF clk'EVENT AND clk = '1' THEN
663 687 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
664 688 END IF;
665 689 END PROCESS;
666 690
667 691 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
668 692 (fft_data_im & fft_data_re) &
669 693 (fft_data_im & fft_data_re) &
670 694 (fft_data_im & fft_data_re) &
671 695 (fft_data_im & fft_data_re);
672 696 -----------------------------------------------------------------------------
673 697
674 698
675 699 -----------------------------------------------------------------------------
676 700 Mem_In_SpectralMatrix : lppFIFOxN
677 701 GENERIC MAP (
678 702 tech => 0,
679 703 Mem_use => Mem_use,
680 704 Data_sz => 32, --16,
681 705 Addr_sz => 7, --8
682 706 FifoCnt => 5)
683 707 PORT MAP (
684 708 clk => clk,
685 709 rstn => rstn,
686 710
687 711 ReUse => MEM_IN_SM_ReUse,
688 712
689 713 wen => MEM_IN_SM_wen,
690 714 wdata => MEM_IN_SM_wData,
691 715
692 716 ren => MEM_IN_SM_ren,
693 717 rdata => MEM_IN_SM_rData,
694 718 full => MEM_IN_SM_Full,
695 719 empty => MEM_IN_SM_Empty,
696 720 almost_full => OPEN);
697 721
698 722 -----------------------------------------------------------------------------
699 723
700 724 observation_vector_1(11 DOWNTO 0) <= '0' &
701 725 SM_correlation_done & --4
702 726 SM_correlation_auto & --3
703 727 SM_correlation_start &
704 728 SM_correlation_start & --7
705 729 status_MS_input(1 DOWNTO 0)& --6..5
706 730 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
707 731
708 732 -----------------------------------------------------------------------------
709 733 MS_control_1 : MS_control
710 734 PORT MAP (
711 735 clk => clk,
712 736 rstn => rstn,
713 737
714 738 current_status_ms => status_MS_input,
715 739
716 740 fifo_in_lock => MEM_IN_SM_locked,
717 741 fifo_in_data => MEM_IN_SM_rdata,
718 742 fifo_in_full => MEM_IN_SM_Full,
719 743 fifo_in_empty => MEM_IN_SM_Empty,
720 744 fifo_in_ren => MEM_IN_SM_ren,
721 745 fifo_in_reuse => MEM_IN_SM_ReUse,
722 746
723 747 fifo_out_data => SM_in_data,
724 748 fifo_out_ren => SM_in_ren,
725 749 fifo_out_empty => SM_in_empty,
726 750
727 751 current_status_component => status_component,
728 752
729 753 correlation_start => SM_correlation_start,
730 754 correlation_auto => SM_correlation_auto,
731 755 correlation_done => SM_correlation_done);
732 756
733 757
734 758 MS_calculation_1 : MS_calculation
735 759 PORT MAP (
736 760 clk => clk,
737 761 rstn => rstn,
738 762
739 763 fifo_in_data => SM_in_data,
740 764 fifo_in_ren => SM_in_ren,
741 765 fifo_in_empty => SM_in_empty,
742 766
743 767 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
744 768 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
745 769 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
746 770
747 771 correlation_start => SM_correlation_start,
748 772 correlation_auto => SM_correlation_auto,
749 773 correlation_begin => SM_correlation_begin,
750 774 correlation_done => SM_correlation_done);
751 775
752 776 -----------------------------------------------------------------------------
753 777 PROCESS (clk, rstn)
754 778 BEGIN -- PROCESS
755 779 IF rstn = '0' THEN -- asynchronous reset (active low)
756 780 current_matrix_write <= '0';
757 781 current_matrix_wait_empty <= '1';
758 782 status_component_fifo_0 <= (OTHERS => '0');
759 783 status_component_fifo_1 <= (OTHERS => '0');
760 784 status_component_fifo_0_end <= '0';
761 785 status_component_fifo_1_end <= '0';
762 786 SM_correlation_done_reg1 <= '0';
763 787 SM_correlation_done_reg2 <= '0';
764 788 SM_correlation_done_reg3 <= '0';
765 789
766 790 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
767 791 SM_correlation_done_reg1 <= SM_correlation_done;
768 792 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
769 793 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
770 794 status_component_fifo_0_end <= '0';
771 795 status_component_fifo_1_end <= '0';
772 796 IF SM_correlation_begin = '1' THEN
773 797 IF current_matrix_write = '0' THEN
774 798 status_component_fifo_0 <= status_component;
775 799 ELSE
776 800 status_component_fifo_1 <= status_component;
777 801 END IF;
778 802 END IF;
779 803
780 804 IF SM_correlation_done_reg3 = '1' THEN
781 805 IF current_matrix_write = '0' THEN
782 806 status_component_fifo_0_end <= '1';
783 807 ELSE
784 808 status_component_fifo_1_end <= '1';
785 809 END IF;
786 810 current_matrix_wait_empty <= '1';
787 811 current_matrix_write <= NOT current_matrix_write;
788 812 END IF;
789 813
790 814 IF current_matrix_wait_empty <= '1' THEN
791 815 IF current_matrix_write = '0' THEN
792 816 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
793 817 ELSE
794 818 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
795 819 END IF;
796 820 END IF;
797 821
798 822 END IF;
799 823 END PROCESS;
800 824
801 825 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
802 826 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
803 827 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
804 828 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
805 829 '1' WHEN current_matrix_wait_empty = '1' ELSE
806 830 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
807 831 MEM_OUT_SM_Full(1);
808 832
809 833 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
810 834 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
811 835
812 836 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
813 837 -----------------------------------------------------------------------------
814 838
815 839 Mem_Out_SpectralMatrix : lppFIFOxN
816 840 GENERIC MAP (
817 841 tech => 0,
818 842 Mem_use => Mem_use,
819 843 Data_sz => 32,
820 844 Addr_sz => 8,
821 845 FifoCnt => 2)
822 846 PORT MAP (
823 847 clk => clk,
824 848 rstn => rstn,
825 849
826 850 ReUse => (OTHERS => '0'),
827 851
828 852 wen => MEM_OUT_SM_Write,
829 853 wdata => MEM_OUT_SM_Data_in,
830 854
831 855 ren => MEM_OUT_SM_Read,
832 856 rdata => MEM_OUT_SM_Data_out,
833 857
834 858 full => MEM_OUT_SM_Full,
835 859 empty => MEM_OUT_SM_Empty,
836 860 almost_full => OPEN);
837 861
838 862 -----------------------------------------------------------------------------
839 863 -- MEM_OUT_SM_Read <= "00";
840 864 PROCESS (clk, rstn)
841 865 BEGIN
842 866 IF rstn = '0' THEN
843 867 fifo_0_ready <= '0';
844 868 fifo_1_ready <= '0';
845 869 fifo_ongoing <= '0';
846 870 ELSIF clk'EVENT AND clk = '1' THEN
847 871 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
848 872 fifo_ongoing <= '1';
849 873 fifo_0_ready <= '0';
850 874 ELSIF status_component_fifo_0_end = '1' THEN
851 875 fifo_0_ready <= '1';
852 876 END IF;
853 877
854 878 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
855 879 fifo_ongoing <= '0';
856 880 fifo_1_ready <= '0';
857 881 ELSIF status_component_fifo_1_end = '1' THEN
858 882 fifo_1_ready <= '1';
859 883 END IF;
860 884
861 885 END IF;
862 886 END PROCESS;
863 887
864 888 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
865 889 '1' WHEN fifo_0_ready = '0' ELSE
866 890 FSM_DMA_fifo_ren;
867 891
868 892 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
869 893 '1' WHEN fifo_1_ready = '0' ELSE
870 894 FSM_DMA_fifo_ren;
871 895
872 896 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
873 897 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
874 898 '1';
875 899
876 900 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
877 901 status_component_fifo_1;
878 902
879 903 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
880 904 MEM_OUT_SM_Data_out(63 DOWNTO 32);
881 905
882 906 -----------------------------------------------------------------------------
883 907 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
884 908 PORT MAP (
885 909 HCLK => clk,
886 910 HRESETn => rstn,
887 911
888 912 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
889 913 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
890 914 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
891 915 fifo_data => FSM_DMA_fifo_data,
892 916 fifo_empty => FSM_DMA_fifo_empty,
893 917 fifo_ren => FSM_DMA_fifo_ren,
894 918
895 919 dma_addr => dma_addr,
896 920 dma_data => dma_data,
897 921 dma_valid => dma_valid,
898 922 dma_valid_burst => dma_valid_burst,
899 923 dma_ren => dma_ren,
900 924 dma_done => dma_done,
901 925
902 926 ready_matrix_f0 => ready_matrix_f0,
903 927 ready_matrix_f1 => ready_matrix_f1,
904 928 ready_matrix_f2 => ready_matrix_f2,
905 929
906 930 error_bad_component_error => error_bad_component_error,
907 931 error_buffer_full => error_buffer_full,
908 932
909 933 debug_reg => debug_reg,
910 934 status_ready_matrix_f0 => status_ready_matrix_f0,
911 935 status_ready_matrix_f1 => status_ready_matrix_f1,
912 936 status_ready_matrix_f2 => status_ready_matrix_f2,
913 937
914 938 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
915 939 config_active_interruption_onError => config_active_interruption_onError,
916 940
917 941 addr_matrix_f0 => addr_matrix_f0,
918 942 addr_matrix_f1 => addr_matrix_f1,
919 943 addr_matrix_f2 => addr_matrix_f2,
920 944
921 945 matrix_time_f0 => matrix_time_f0,
922 946 matrix_time_f1 => matrix_time_f1,
923 947 matrix_time_f2 => matrix_time_f2
924 948 );
925 949 -----------------------------------------------------------------------------
926 950
927 951
928 952
929 953
930 954
931 955 -----------------------------------------------------------------------------
932 956 -- TIME MANAGMENT
933 957 -----------------------------------------------------------------------------
934 958 all_time <= coarse_time & fine_time;
935 959 --
936 960 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
937 961 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
938 962 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
939 963 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
940 964
941 965 all_time_reg: FOR I IN 0 TO 3 GENERATE
942 966
943 967 PROCESS (clk, rstn)
944 968 BEGIN
945 969 IF rstn = '0' THEN
946 970 f_empty_reg(I) <= '1';
947 971 ELSIF clk'event AND clk = '1' THEN
948 972 f_empty_reg(I) <= f_empty(I);
949 973 END IF;
950 974 END PROCESS;
951 975
952 976 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
953 977
954 978 s_m_t_m_f0_A : spectral_matrix_time_managment
955 979 PORT MAP (
956 980 clk => clk,
957 981 rstn => rstn,
958 982 time_in => all_time,
959 983 update_1 => time_update_f(I),
960 984 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
961 985 );
962 986
963 987 END GENERATE all_time_reg;
964 988
965 989 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
966 990 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
967 991 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
968 992 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
969 993
970 994 -----------------------------------------------------------------------------
971 995
972 END Behavioral; No newline at end of file
996 END Behavioral;
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