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Remove arbitration in front of FFT based on Pong Status...
pellion -
r384:328a814d7018 (MINI-LFR) WFP_MS-0-1-20 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 BEGIN -- beh
179 BEGIN -- beh
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK
182 -- CLK
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184
184
185 PROCESS(clk_50)
185 PROCESS(clk_50)
186 BEGIN
186 BEGIN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 clk_50_s <= NOT clk_50_s;
188 clk_50_s <= NOT clk_50_s;
189 END IF;
189 END IF;
190 END PROCESS;
190 END PROCESS;
191
191
192 PROCESS(clk_50_s)
192 PROCESS(clk_50_s)
193 BEGIN
193 BEGIN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 clk_25 <= NOT clk_25;
195 clk_25 <= NOT clk_25;
196 END IF;
196 END IF;
197 END PROCESS;
197 END PROCESS;
198
198
199 PROCESS(clk_49)
199 PROCESS(clk_49)
200 BEGIN
200 BEGIN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 clk_24 <= NOT clk_24;
202 clk_24 <= NOT clk_24;
203 END IF;
203 END IF;
204 END PROCESS;
204 END PROCESS;
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207
207
208 PROCESS (clk_25, reset)
208 PROCESS (clk_25, reset)
209 BEGIN -- PROCESS
209 BEGIN -- PROCESS
210 IF reset = '0' THEN -- asynchronous reset (active low)
210 IF reset = '0' THEN -- asynchronous reset (active low)
211 LED0 <= '0';
211 LED0 <= '0';
212 LED1 <= '0';
212 LED1 <= '0';
213 LED2 <= '0';
213 LED2 <= '0';
214 --IO1 <= '0';
214 --IO1 <= '0';
215 --IO2 <= '1';
215 --IO2 <= '1';
216 --IO3 <= '0';
216 --IO3 <= '0';
217 --IO4 <= '0';
217 --IO4 <= '0';
218 --IO5 <= '0';
218 --IO5 <= '0';
219 --IO6 <= '0';
219 --IO6 <= '0';
220 --IO7 <= '0';
220 --IO7 <= '0';
221 --IO8 <= '0';
221 --IO8 <= '0';
222 --IO9 <= '0';
222 --IO9 <= '0';
223 --IO10 <= '0';
223 --IO10 <= '0';
224 --IO11 <= '0';
224 --IO11 <= '0';
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 LED0 <= '0';
226 LED0 <= '0';
227 LED1 <= '1';
227 LED1 <= '1';
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 --IO1 <= '1';
229 --IO1 <= '1';
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 --IO3 <= ADC_SDO(0);
231 --IO3 <= ADC_SDO(0);
232 --IO4 <= ADC_SDO(1);
232 --IO4 <= ADC_SDO(1);
233 --IO5 <= ADC_SDO(2);
233 --IO5 <= ADC_SDO(2);
234 --IO6 <= ADC_SDO(3);
234 --IO6 <= ADC_SDO(3);
235 --IO7 <= ADC_SDO(4);
235 --IO7 <= ADC_SDO(4);
236 --IO8 <= ADC_SDO(5);
236 --IO8 <= ADC_SDO(5);
237 --IO9 <= ADC_SDO(6);
237 --IO9 <= ADC_SDO(6);
238 --IO10 <= ADC_SDO(7);
238 --IO10 <= ADC_SDO(7);
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 END IF;
240 END IF;
241 END PROCESS;
241 END PROCESS;
242
242
243 PROCESS (clk_24, reset)
243 PROCESS (clk_24, reset)
244 BEGIN -- PROCESS
244 BEGIN -- PROCESS
245 IF reset = '0' THEN -- asynchronous reset (active low)
245 IF reset = '0' THEN -- asynchronous reset (active low)
246 I00_s <= '0';
246 I00_s <= '0';
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 I00_s <= NOT I00_s ;
248 I00_s <= NOT I00_s ;
249 END IF;
249 END IF;
250 END PROCESS;
250 END PROCESS;
251 -- IO0 <= I00_s;
251 -- IO0 <= I00_s;
252
252
253 --UARTs
253 --UARTs
254 nCTS1 <= '1';
254 nCTS1 <= '1';
255 nCTS2 <= '1';
255 nCTS2 <= '1';
256 nDCD2 <= '1';
256 nDCD2 <= '1';
257
257
258 --EXT CONNECTOR
258 --EXT CONNECTOR
259
259
260 --SPACE WIRE
260 --SPACE WIRE
261
261
262 leon3_soc_1 : leon3_soc
262 leon3_soc_1 : leon3_soc
263 GENERIC MAP (
263 GENERIC MAP (
264 fabtech => apa3e,
264 fabtech => apa3e,
265 memtech => apa3e,
265 memtech => apa3e,
266 padtech => inferred,
266 padtech => inferred,
267 clktech => inferred,
267 clktech => inferred,
268 disas => 0,
268 disas => 0,
269 dbguart => 0,
269 dbguart => 0,
270 pclow => 2,
270 pclow => 2,
271 clk_freq => 25000,
271 clk_freq => 25000,
272 NB_CPU => 1,
272 NB_CPU => 1,
273 ENABLE_FPU => 1,
273 ENABLE_FPU => 1,
274 FPU_NETLIST => 0,
274 FPU_NETLIST => 0,
275 ENABLE_DSU => 1,
275 ENABLE_DSU => 1,
276 ENABLE_AHB_UART => 1,
276 ENABLE_AHB_UART => 1,
277 ENABLE_APB_UART => 1,
277 ENABLE_APB_UART => 1,
278 ENABLE_IRQMP => 1,
278 ENABLE_IRQMP => 1,
279 ENABLE_GPT => 1,
279 ENABLE_GPT => 1,
280 NB_AHB_MASTER => NB_AHB_MASTER,
280 NB_AHB_MASTER => NB_AHB_MASTER,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 NB_APB_SLAVE => NB_APB_SLAVE)
282 NB_APB_SLAVE => NB_APB_SLAVE)
283 PORT MAP (
283 PORT MAP (
284 clk => clk_25,
284 clk => clk_25,
285 reset => reset,
285 reset => reset,
286 errorn => errorn,
286 errorn => errorn,
287 ahbrxd => TXD1,
287 ahbrxd => TXD1,
288 ahbtxd => RXD1,
288 ahbtxd => RXD1,
289 urxd1 => TXD2,
289 urxd1 => TXD2,
290 utxd1 => RXD2,
290 utxd1 => RXD2,
291 address => SRAM_A,
291 address => SRAM_A,
292 data => SRAM_DQ,
292 data => SRAM_DQ,
293 nSRAM_BE0 => SRAM_nBE(0),
293 nSRAM_BE0 => SRAM_nBE(0),
294 nSRAM_BE1 => SRAM_nBE(1),
294 nSRAM_BE1 => SRAM_nBE(1),
295 nSRAM_BE2 => SRAM_nBE(2),
295 nSRAM_BE2 => SRAM_nBE(2),
296 nSRAM_BE3 => SRAM_nBE(3),
296 nSRAM_BE3 => SRAM_nBE(3),
297 nSRAM_WE => SRAM_nWE,
297 nSRAM_WE => SRAM_nWE,
298 nSRAM_CE => SRAM_CE,
298 nSRAM_CE => SRAM_CE,
299 nSRAM_OE => SRAM_nOE,
299 nSRAM_OE => SRAM_nOE,
300
300
301 apbi_ext => apbi_ext,
301 apbi_ext => apbi_ext,
302 apbo_ext => apbo_ext,
302 apbo_ext => apbo_ext,
303 ahbi_s_ext => ahbi_s_ext,
303 ahbi_s_ext => ahbi_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
305 ahbi_m_ext => ahbi_m_ext,
305 ahbi_m_ext => ahbi_m_ext,
306 ahbo_m_ext => ahbo_m_ext);
306 ahbo_m_ext => ahbo_m_ext);
307
307
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 -------------------------------------------------------------------------------
310 -------------------------------------------------------------------------------
311 apb_lfr_time_management_1 : apb_lfr_time_management
311 apb_lfr_time_management_1 : apb_lfr_time_management
312 GENERIC MAP (
312 GENERIC MAP (
313 pindex => 6,
313 pindex => 6,
314 paddr => 6,
314 paddr => 6,
315 pmask => 16#fff#,
315 pmask => 16#fff#,
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 PORT MAP (
318 PORT MAP (
319 clk25MHz => clk_25,
319 clk25MHz => clk_25,
320 clk24_576MHz => clk_24, -- 49.152MHz/2
320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 resetn => reset,
321 resetn => reset,
322 grspw_tick => swno.tickout,
322 grspw_tick => swno.tickout,
323 apbi => apbi_ext,
323 apbi => apbi_ext,
324 apbo => apbo_ext(6),
324 apbo => apbo_ext(6),
325 coarse_time => coarse_time,
325 coarse_time => coarse_time,
326 fine_time => fine_time);
326 fine_time => fine_time);
327
327
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
330 -----------------------------------------------------------------------
330 -----------------------------------------------------------------------
331
331
332 SPW_EN <= '1';
332 SPW_EN <= '1';
333
333
334 spw_clk <= clk_50_s;
334 spw_clk <= clk_50_s;
335 spw_rxtxclk <= spw_clk;
335 spw_rxtxclk <= spw_clk;
336 spw_rxclkn <= NOT spw_rxtxclk;
336 spw_rxclkn <= NOT spw_rxtxclk;
337
337
338 -- PADS for SPW1
338 -- PADS for SPW1
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SIN, stmp(0));
342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 -- PADS FOR SPW2
347 -- PADS FOR SPW2
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_SIN, dtmp(1));
349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 PORT MAP (SPW_RED_DIN, stmp(1));
351 PORT MAP (SPW_RED_DIN, stmp(1));
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356
356
357 -- GRSPW PHY
357 -- GRSPW PHY
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 spw_phy0 : grspw_phy
360 spw_phy0 : grspw_phy
361 GENERIC MAP(
361 GENERIC MAP(
362 tech => apa3e,
362 tech => apa3e,
363 rxclkbuftype => 1,
363 rxclkbuftype => 1,
364 scantest => 0)
364 scantest => 0)
365 PORT MAP(
365 PORT MAP(
366 rxrst => swno.rxrst,
366 rxrst => swno.rxrst,
367 di => dtmp(j),
367 di => dtmp(j),
368 si => stmp(j),
368 si => stmp(j),
369 rxclko => spw_rxclk(j),
369 rxclko => spw_rxclk(j),
370 do => swni.d(j),
370 do => swni.d(j),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 END GENERATE spw_inputloop;
373 END GENERATE spw_inputloop;
374
374
375 -- SPW core
375 -- SPW core
376 sw0 : grspwm GENERIC MAP(
376 sw0 : grspwm GENERIC MAP(
377 tech => apa3e,
377 tech => apa3e,
378 hindex => 1,
378 hindex => 1,
379 pindex => 5,
379 pindex => 5,
380 paddr => 5,
380 paddr => 5,
381 pirq => 11,
381 pirq => 11,
382 sysfreq => 25000, -- CPU_FREQ
382 sysfreq => 25000, -- CPU_FREQ
383 rmap => 1,
383 rmap => 1,
384 rmapcrc => 1,
384 rmapcrc => 1,
385 fifosize1 => 16,
385 fifosize1 => 16,
386 fifosize2 => 16,
386 fifosize2 => 16,
387 rxclkbuftype => 1,
387 rxclkbuftype => 1,
388 rxunaligned => 0,
388 rxunaligned => 0,
389 rmapbufs => 4,
389 rmapbufs => 4,
390 ft => 0,
390 ft => 0,
391 netlist => 0,
391 netlist => 0,
392 ports => 2,
392 ports => 2,
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 memtech => apa3e,
394 memtech => apa3e,
395 destkey => 2,
395 destkey => 2,
396 spwcore => 1
396 spwcore => 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 )
400 )
401 PORT MAP(reset, clk_25, spw_rxclk(0),
401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 swni, swno);
404 swni, swno);
405
405
406 swni.tickin <= '0';
406 swni.tickin <= '0';
407 swni.rmapen <= '1';
407 swni.rmapen <= '1';
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 swni.tickinraw <= '0';
409 swni.tickinraw <= '0';
410 swni.timein <= (OTHERS => '0');
410 swni.timein <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
413
413
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
417 lpp_lfr_1 : lpp_lfr
417 lpp_lfr_1 : lpp_lfr
418 GENERIC MAP (
418 GENERIC MAP (
419 Mem_use => use_RAM,
419 Mem_use => use_RAM,
420 nb_data_by_buffer_size => 32,
420 nb_data_by_buffer_size => 32,
421 nb_word_by_buffer_size => 30,
421 nb_word_by_buffer_size => 30,
422 nb_snapshot_param_size => 32,
422 nb_snapshot_param_size => 32,
423 delta_vector_size => 32,
423 delta_vector_size => 32,
424 delta_vector_size_f0_2 => 7, -- log2(96)
424 delta_vector_size_f0_2 => 7, -- log2(96)
425 pindex => 15,
425 pindex => 15,
426 paddr => 15,
426 paddr => 15,
427 pmask => 16#fff#,
427 pmask => 16#fff#,
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"000112") -- aa.bb.cc version
431 top_lfr_version => X"000114") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
435 sample_B => sample_s(2 DOWNTO 0),
435 sample_B => sample_s(2 DOWNTO 0),
436 sample_E => sample_s(7 DOWNTO 3),
436 sample_E => sample_s(7 DOWNTO 3),
437 sample_val => sample_val,
437 sample_val => sample_val,
438 apbi => apbi_ext,
438 apbi => apbi_ext,
439 apbo => apbo_ext(15),
439 apbo => apbo_ext(15),
440 ahbi => ahbi_m_ext,
440 ahbi => ahbi_m_ext,
441 ahbo => ahbo_m_ext(2),
441 ahbo => ahbo_m_ext(2),
442 coarse_time => coarse_time,
442 coarse_time => coarse_time,
443 fine_time => fine_time,
443 fine_time => fine_time,
444 data_shaping_BW => bias_fail_sw_sig,
444 data_shaping_BW => bias_fail_sw_sig,
445 observation_vector_0=> observation_vector_0,
445 observation_vector_0=> observation_vector_0,
446 observation_vector_1 => observation_vector_1,
446 observation_vector_1 => observation_vector_1,
447 observation_reg => observation_reg);
447 observation_reg => observation_reg);
448
448
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
451 END GENERATE all_sample;
451 END GENERATE all_sample;
452
452
453
453
454
454
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
456 GENERIC MAP(
456 GENERIC MAP(
457 ChannelCount => 8,
457 ChannelCount => 8,
458 SampleNbBits => 14,
458 SampleNbBits => 14,
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
461 PORT MAP (
461 PORT MAP (
462 -- CONV
462 -- CONV
463 cnv_clk => clk_24,
463 cnv_clk => clk_24,
464 cnv_rstn => reset,
464 cnv_rstn => reset,
465 cnv => ADC_nCS_sig,
465 cnv => ADC_nCS_sig,
466 -- DATA
466 -- DATA
467 clk => clk_25,
467 clk => clk_25,
468 rstn => reset,
468 rstn => reset,
469 sck => ADC_CLK_sig,
469 sck => ADC_CLK_sig,
470 sdo => ADC_SDO_sig,
470 sdo => ADC_SDO_sig,
471 -- SAMPLE
471 -- SAMPLE
472 sample => sample,
472 sample => sample,
473 sample_val => sample_val);
473 sample_val => sample_val);
474
474
475 --IO10 <= ADC_SDO_sig(5);
475 --IO10 <= ADC_SDO_sig(5);
476 --IO9 <= ADC_SDO_sig(4);
476 --IO9 <= ADC_SDO_sig(4);
477 --IO8 <= ADC_SDO_sig(3);
477 --IO8 <= ADC_SDO_sig(3);
478
478
479 ADC_nCS <= ADC_nCS_sig;
479 ADC_nCS <= ADC_nCS_sig;
480 ADC_CLK <= ADC_CLK_sig;
480 ADC_CLK <= ADC_CLK_sig;
481 ADC_SDO_sig <= ADC_SDO;
481 ADC_SDO_sig <= ADC_SDO;
482
482
483 ----------------------------------------------------------------------
483 ----------------------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
485 ----------------------------------------------------------------------
485 ----------------------------------------------------------------------
486
486
487 grgpio0 : grgpio
487 grgpio0 : grgpio
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
490
490
491 --pio_pad_0 : iopad
491 --pio_pad_0 : iopad
492 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
494 --pio_pad_1 : iopad
494 --pio_pad_1 : iopad
495 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
497 --pio_pad_2 : iopad
497 --pio_pad_2 : iopad
498 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
500 --pio_pad_3 : iopad
500 --pio_pad_3 : iopad
501 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
503 --pio_pad_4 : iopad
503 --pio_pad_4 : iopad
504 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- GENERIC MAP (tech => CFG_PADTECH)
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
506 --pio_pad_5 : iopad
506 --pio_pad_5 : iopad
507 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- GENERIC MAP (tech => CFG_PADTECH)
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
509 --pio_pad_6 : iopad
509 --pio_pad_6 : iopad
510 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- GENERIC MAP (tech => CFG_PADTECH)
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
512 --pio_pad_7 : iopad
512 --pio_pad_7 : iopad
513 -- GENERIC MAP (tech => CFG_PADTECH)
513 -- GENERIC MAP (tech => CFG_PADTECH)
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
515
515
516 PROCESS (clk_25, reset)
516 PROCESS (clk_25, reset)
517 BEGIN -- PROCESS
517 BEGIN -- PROCESS
518 IF reset = '0' THEN -- asynchronous reset (active low)
518 IF reset = '0' THEN -- asynchronous reset (active low)
519 IO0 <= '0';
519 IO0 <= '0';
520 IO1 <= '0';
520 IO1 <= '0';
521 IO2 <= '0';
521 IO2 <= '0';
522 IO3 <= '0';
522 IO3 <= '0';
523 IO4 <= '0';
523 IO4 <= '0';
524 IO5 <= '0';
524 IO5 <= '0';
525 IO6 <= '0';
525 IO6 <= '0';
526 IO7 <= '0';
526 IO7 <= '0';
527 IO8 <= '0';
527 IO8 <= '0';
528 IO9 <= '0';
528 IO9 <= '0';
529 IO10 <= '0';
529 IO10 <= '0';
530 IO11 <= '0';
530 IO11 <= '0';
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
532 CASE gpioo.dout(2 DOWNTO 0) IS
532 CASE gpioo.dout(2 DOWNTO 0) IS
533 WHEN "011" =>
533 WHEN "011" =>
534 IO0 <= observation_reg(0 );
534 IO0 <= observation_reg(0 );
535 IO1 <= observation_reg(1 );
535 IO1 <= observation_reg(1 );
536 IO2 <= observation_reg(2 );
536 IO2 <= observation_reg(2 );
537 IO3 <= observation_reg(3 );
537 IO3 <= observation_reg(3 );
538 IO4 <= observation_reg(4 );
538 IO4 <= observation_reg(4 );
539 IO5 <= observation_reg(5 );
539 IO5 <= observation_reg(5 );
540 IO6 <= observation_reg(6 );
540 IO6 <= observation_reg(6 );
541 IO7 <= observation_reg(7 );
541 IO7 <= observation_reg(7 );
542 IO8 <= observation_reg(8 );
542 IO8 <= observation_reg(8 );
543 IO9 <= observation_reg(9 );
543 IO9 <= observation_reg(9 );
544 IO10 <= observation_reg(10);
544 IO10 <= observation_reg(10);
545 IO11 <= observation_reg(11);
545 IO11 <= observation_reg(11);
546 WHEN "001" =>
546 WHEN "001" =>
547 IO0 <= observation_reg(0 + 12);
547 IO0 <= observation_reg(0 + 12);
548 IO1 <= observation_reg(1 + 12);
548 IO1 <= observation_reg(1 + 12);
549 IO2 <= observation_reg(2 + 12);
549 IO2 <= observation_reg(2 + 12);
550 IO3 <= observation_reg(3 + 12);
550 IO3 <= observation_reg(3 + 12);
551 IO4 <= observation_reg(4 + 12);
551 IO4 <= observation_reg(4 + 12);
552 IO5 <= observation_reg(5 + 12);
552 IO5 <= observation_reg(5 + 12);
553 IO6 <= observation_reg(6 + 12);
553 IO6 <= observation_reg(6 + 12);
554 IO7 <= observation_reg(7 + 12);
554 IO7 <= observation_reg(7 + 12);
555 IO8 <= observation_reg(8 + 12);
555 IO8 <= observation_reg(8 + 12);
556 IO9 <= observation_reg(9 + 12);
556 IO9 <= observation_reg(9 + 12);
557 IO10 <= observation_reg(10 + 12);
557 IO10 <= observation_reg(10 + 12);
558 IO11 <= observation_reg(11 + 12);
558 IO11 <= observation_reg(11 + 12);
559 WHEN "010" =>
559 WHEN "010" =>
560 IO0 <= observation_reg(0 + 12 + 12);
560 IO0 <= observation_reg(0 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
568 IO8 <= '0';
568 IO8 <= '0';
569 IO9 <= '0';
569 IO9 <= '0';
570 IO10 <= '0';
570 IO10 <= '0';
571 IO11 <= '0';
571 IO11 <= '0';
572 WHEN "000" =>
572 WHEN "000" =>
573 IO0 <= observation_vector_0(0 );
573 IO0 <= observation_vector_0(0 );
574 IO1 <= observation_vector_0(1 );
574 IO1 <= observation_vector_0(1 );
575 IO2 <= observation_vector_0(2 );
575 IO2 <= observation_vector_0(2 );
576 IO3 <= observation_vector_0(3 );
576 IO3 <= observation_vector_0(3 );
577 IO4 <= observation_vector_0(4 );
577 IO4 <= observation_vector_0(4 );
578 IO5 <= observation_vector_0(5 );
578 IO5 <= observation_vector_0(5 );
579 IO6 <= observation_vector_0(6 );
579 IO6 <= observation_vector_0(6 );
580 IO7 <= observation_vector_0(7 );
580 IO7 <= observation_vector_0(7 );
581 IO8 <= observation_vector_0(8 );
581 IO8 <= observation_vector_0(8 );
582 IO9 <= observation_vector_0(9 );
582 IO9 <= observation_vector_0(9 );
583 IO10 <= observation_vector_0(10);
583 IO10 <= observation_vector_0(10);
584 IO11 <= observation_vector_0(11);
584 IO11 <= observation_vector_0(11);
585 WHEN "100" =>
585 WHEN "100" =>
586 IO0 <= observation_vector_1(0 );
586 IO0 <= observation_vector_1(0 );
587 IO1 <= observation_vector_1(1 );
587 IO1 <= observation_vector_1(1 );
588 IO2 <= observation_vector_1(2 );
588 IO2 <= observation_vector_1(2 );
589 IO3 <= observation_vector_1(3 );
589 IO3 <= observation_vector_1(3 );
590 IO4 <= observation_vector_1(4 );
590 IO4 <= observation_vector_1(4 );
591 IO5 <= observation_vector_1(5 );
591 IO5 <= observation_vector_1(5 );
592 IO6 <= observation_vector_1(6 );
592 IO6 <= observation_vector_1(6 );
593 IO7 <= observation_vector_1(7 );
593 IO7 <= observation_vector_1(7 );
594 IO8 <= observation_vector_1(8 );
594 IO8 <= observation_vector_1(8 );
595 IO9 <= observation_vector_1(9 );
595 IO9 <= observation_vector_1(9 );
596 IO10 <= observation_vector_1(10);
596 IO10 <= observation_vector_1(10);
597 IO11 <= observation_vector_1(11);
597 IO11 <= observation_vector_1(11);
598 WHEN OTHERS => NULL;
598 WHEN OTHERS => NULL;
599 END CASE;
599 END CASE;
600
600
601 END IF;
601 END IF;
602 END PROCESS;
602 END PROCESS;
603
603
604 END beh;
604 END beh;
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@@ -1,972 +1,996
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
15 USE lpp.fft_components.ALL;
16
16
17 ENTITY lpp_lfr_ms IS
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
19 Mem_use : INTEGER := use_RAM
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
24
25 ---------------------------------------------------------------------------
25 ---------------------------------------------------------------------------
26 -- DATA INPUT
26 -- DATA INPUT
27 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
28 -- TIME
28 -- TIME
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 --
31 --
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
34 --
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- DMA
42 -- DMA
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 dma_valid : OUT STD_LOGIC;
46 dma_valid : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
50
50
51 -- Reg out
51 -- Reg out
52 ready_matrix_f0 : OUT STD_LOGIC;
52 ready_matrix_f0 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58
58
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 --
60 --
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63
63
64 -- Reg In
64 -- Reg In
65 status_ready_matrix_f0 : IN STD_LOGIC;
65 status_ready_matrix_f0 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
68
68
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
78
78
79 );
79 );
80 END;
80 END;
81
81
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83
83
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89
89
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95
95
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100
100
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102
102
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107
107
108 SIGNAL error_wen_f0 : STD_LOGIC;
108 SIGNAL error_wen_f0 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
111
111
112 SIGNAL one_sample_f1_full : STD_LOGIC;
112 SIGNAL one_sample_f1_full : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
116
116
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 -- FSM / SWITCH SELECT CHANNEL
118 -- FSM / SWITCH SELECT CHANNEL
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123
123
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128
128
129 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 -- FSM LOAD FFT
130 -- FSM LOAD FFT
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135
135
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 SIGNAL sample_load : STD_LOGIC;
137 SIGNAL sample_load : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141
141
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- FFT
144 -- FFT
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 SIGNAL fft_read : STD_LOGIC;
146 SIGNAL fft_read : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_valid : STD_LOGIC;
150 SIGNAL fft_data_valid : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 SIGNAL current_fifo_empty : STD_LOGIC;
158 SIGNAL current_fifo_empty : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162
162
163 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176
176
177 SIGNAL SM_correlation_start : STD_LOGIC;
177 SIGNAL SM_correlation_start : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
184
184
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188
188
189 SIGNAL current_matrix_write : STD_LOGIC;
189 SIGNAL current_matrix_write : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 SIGNAL fifo_0_ready : STD_LOGIC;
192 SIGNAL fifo_0_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
195
195
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
207
207
208 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
209 -- TIME REG & INFOs
209 -- TIME REG & INFOs
210 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212
212
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
217
217
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222
222
223 --SIGNAL time_update_f0_A : STD_LOGIC;
223 --SIGNAL time_update_f0_A : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
227 --
227 --
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
231
231
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237 SIGNAL ping_npong : STD_LOGIC;
237 SIGNAL fft_ongoing_counter : STD_LOGIC_VECTOR(1 DOWNTO 0);
238 SIGNAL sample_load_reg : STD_LOGIC;
238
239 SIGNAL fft_ready_reg : STD_LOGIC;
240 SIGNAL fft_ready_rising_down : STD_LOGIC;
241
242 SIGNAL sample_load_reg : STD_LOGIC;
243 SIGNAL sample_load_rising_down : STD_LOGIC;
239
244
240 BEGIN
245 BEGIN
241
246
242
247
243 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
248 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
244
249
245
250
246 switch_f0_inst : spectral_matrix_switch_f0
251 switch_f0_inst : spectral_matrix_switch_f0
247 PORT MAP (
252 PORT MAP (
248 clk => clk,
253 clk => clk,
249 rstn => rstn,
254 rstn => rstn,
250
255
251 sample_wen => sample_f0_wen,
256 sample_wen => sample_f0_wen,
252
257
253 fifo_A_empty => sample_f0_A_empty,
258 fifo_A_empty => sample_f0_A_empty,
254 fifo_A_full => sample_f0_A_full,
259 fifo_A_full => sample_f0_A_full,
255 fifo_A_wen => sample_f0_A_wen,
260 fifo_A_wen => sample_f0_A_wen,
256
261
257 fifo_B_empty => sample_f0_B_empty,
262 fifo_B_empty => sample_f0_B_empty,
258 fifo_B_full => sample_f0_B_full,
263 fifo_B_full => sample_f0_B_full,
259 fifo_B_wen => sample_f0_B_wen,
264 fifo_B_wen => sample_f0_B_wen,
260
265
261 error_wen => error_wen_f0); -- TODO
266 error_wen => error_wen_f0); -- TODO
262
267
263 -----------------------------------------------------------------------------
268 -----------------------------------------------------------------------------
264 -- FIFO IN
269 -- FIFO IN
265 -----------------------------------------------------------------------------
270 -----------------------------------------------------------------------------
266 lppFIFOxN_f0_a : lppFIFOxN
271 lppFIFOxN_f0_a : lppFIFOxN
267 GENERIC MAP (
272 GENERIC MAP (
268 tech => 0,
273 tech => 0,
269 Mem_use => Mem_use,
274 Mem_use => Mem_use,
270 Data_sz => 16,
275 Data_sz => 16,
271 Addr_sz => 8,
276 Addr_sz => 8,
272 FifoCnt => 5)
277 FifoCnt => 5)
273 PORT MAP (
278 PORT MAP (
274 clk => clk,
279 clk => clk,
275 rstn => rstn,
280 rstn => rstn,
276
281
277 ReUse => (OTHERS => '0'),
282 ReUse => (OTHERS => '0'),
278
283
279 wen => sample_f0_A_wen,
284 wen => sample_f0_A_wen,
280 wdata => sample_f0_wdata,
285 wdata => sample_f0_wdata,
281
286
282 ren => sample_f0_A_ren,
287 ren => sample_f0_A_ren,
283 rdata => sample_f0_A_rdata,
288 rdata => sample_f0_A_rdata,
284
289
285 empty => sample_f0_A_empty,
290 empty => sample_f0_A_empty,
286 full => sample_f0_A_full,
291 full => sample_f0_A_full,
287 almost_full => OPEN);
292 almost_full => OPEN);
288
293
289 lppFIFOxN_f0_b : lppFIFOxN
294 lppFIFOxN_f0_b : lppFIFOxN
290 GENERIC MAP (
295 GENERIC MAP (
291 tech => 0,
296 tech => 0,
292 Mem_use => Mem_use,
297 Mem_use => Mem_use,
293 Data_sz => 16,
298 Data_sz => 16,
294 Addr_sz => 8,
299 Addr_sz => 8,
295 FifoCnt => 5)
300 FifoCnt => 5)
296 PORT MAP (
301 PORT MAP (
297 clk => clk,
302 clk => clk,
298 rstn => rstn,
303 rstn => rstn,
299
304
300 ReUse => (OTHERS => '0'),
305 ReUse => (OTHERS => '0'),
301
306
302 wen => sample_f0_B_wen,
307 wen => sample_f0_B_wen,
303 wdata => sample_f0_wdata,
308 wdata => sample_f0_wdata,
304 ren => sample_f0_B_ren,
309 ren => sample_f0_B_ren,
305 rdata => sample_f0_B_rdata,
310 rdata => sample_f0_B_rdata,
306 empty => sample_f0_B_empty,
311 empty => sample_f0_B_empty,
307 full => sample_f0_B_full,
312 full => sample_f0_B_full,
308 almost_full => OPEN);
313 almost_full => OPEN);
309
314
310 lppFIFOxN_f1 : lppFIFOxN
315 lppFIFOxN_f1 : lppFIFOxN
311 GENERIC MAP (
316 GENERIC MAP (
312 tech => 0,
317 tech => 0,
313 Mem_use => Mem_use,
318 Mem_use => Mem_use,
314 Data_sz => 16,
319 Data_sz => 16,
315 Addr_sz => 8,
320 Addr_sz => 8,
316 FifoCnt => 5)
321 FifoCnt => 5)
317 PORT MAP (
322 PORT MAP (
318 clk => clk,
323 clk => clk,
319 rstn => rstn,
324 rstn => rstn,
320
325
321 ReUse => (OTHERS => '0'),
326 ReUse => (OTHERS => '0'),
322
327
323 wen => sample_f1_wen,
328 wen => sample_f1_wen,
324 wdata => sample_f1_wdata,
329 wdata => sample_f1_wdata,
325 ren => sample_f1_ren,
330 ren => sample_f1_ren,
326 rdata => sample_f1_rdata,
331 rdata => sample_f1_rdata,
327 empty => sample_f1_empty,
332 empty => sample_f1_empty,
328 full => sample_f1_full,
333 full => sample_f1_full,
329 almost_full => sample_f1_almost_full);
334 almost_full => sample_f1_almost_full);
330
335
331
336
332 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
337 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
333
338
334 PROCESS (clk, rstn)
339 PROCESS (clk, rstn)
335 BEGIN -- PROCESS
340 BEGIN -- PROCESS
336 IF rstn = '0' THEN -- asynchronous reset (active low)
341 IF rstn = '0' THEN -- asynchronous reset (active low)
337 one_sample_f1_full <= '0';
342 one_sample_f1_full <= '0';
338 error_wen_f1 <= '0';
343 error_wen_f1 <= '0';
339 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
344 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
340 IF sample_f1_full = "00000" THEN
345 IF sample_f1_full = "00000" THEN
341 one_sample_f1_full <= '0';
346 one_sample_f1_full <= '0';
342 ELSE
347 ELSE
343 one_sample_f1_full <= '1';
348 one_sample_f1_full <= '1';
344 END IF;
349 END IF;
345 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
350 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
346 END IF;
351 END IF;
347 END PROCESS;
352 END PROCESS;
348
353
349
354
350 lppFIFOxN_f2 : lppFIFOxN
355 lppFIFOxN_f2 : lppFIFOxN
351 GENERIC MAP (
356 GENERIC MAP (
352 tech => 0,
357 tech => 0,
353 Mem_use => Mem_use,
358 Mem_use => Mem_use,
354 Data_sz => 16,
359 Data_sz => 16,
355 Addr_sz => 8,
360 Addr_sz => 8,
356 FifoCnt => 5)
361 FifoCnt => 5)
357 PORT MAP (
362 PORT MAP (
358 clk => clk,
363 clk => clk,
359 rstn => rstn,
364 rstn => rstn,
360
365
361 ReUse => (OTHERS => '0'),
366 ReUse => (OTHERS => '0'),
362
367
363 wen => sample_f2_wen,
368 wen => sample_f2_wen,
364 wdata => sample_f2_wdata,
369 wdata => sample_f2_wdata,
365 ren => sample_f2_ren,
370 ren => sample_f2_ren,
366 rdata => sample_f2_rdata,
371 rdata => sample_f2_rdata,
367 empty => sample_f2_empty,
372 empty => sample_f2_empty,
368 full => sample_f2_full,
373 full => sample_f2_full,
369 almost_full => OPEN);
374 almost_full => OPEN);
370
375
371
376
372 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
377 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
373
378
374 PROCESS (clk, rstn)
379 PROCESS (clk, rstn)
375 BEGIN -- PROCESS
380 BEGIN -- PROCESS
376 IF rstn = '0' THEN -- asynchronous reset (active low)
381 IF rstn = '0' THEN -- asynchronous reset (active low)
377 one_sample_f2_full <= '0';
382 one_sample_f2_full <= '0';
378 error_wen_f2 <= '0';
383 error_wen_f2 <= '0';
379 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
380 IF sample_f2_full = "00000" THEN
385 IF sample_f2_full = "00000" THEN
381 one_sample_f2_full <= '0';
386 one_sample_f2_full <= '0';
382 ELSE
387 ELSE
383 one_sample_f2_full <= '1';
388 one_sample_f2_full <= '1';
384 END IF;
389 END IF;
385 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
390 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
386 END IF;
391 END IF;
387 END PROCESS;
392 END PROCESS;
388
393
389 -----------------------------------------------------------------------------
394 -----------------------------------------------------------------------------
390 -- FSM SELECT CHANNEL
395 -- FSM SELECT CHANNEL
391 -----------------------------------------------------------------------------
396 -----------------------------------------------------------------------------
392 PROCESS (clk, rstn)
397 PROCESS (clk, rstn)
393 BEGIN
398 BEGIN
394 IF rstn = '0' THEN
399 IF rstn = '0' THEN
395 state_fsm_select_channel <= IDLE;
400 state_fsm_select_channel <= IDLE;
396 ELSIF clk'EVENT AND clk = '1' THEN
401 ELSIF clk'EVENT AND clk = '1' THEN
397 CASE state_fsm_select_channel IS
402 CASE state_fsm_select_channel IS
398 WHEN IDLE =>
403 WHEN IDLE =>
399 IF sample_f1_full = "11111" THEN
404 IF sample_f1_full = "11111" THEN
400 state_fsm_select_channel <= SWITCH_F1;
405 state_fsm_select_channel <= SWITCH_F1;
401 ELSIF sample_f1_almost_full = "00000" THEN
406 ELSIF sample_f1_almost_full = "00000" THEN
402 IF sample_f0_A_full = "11111" THEN
407 IF sample_f0_A_full = "11111" THEN
403 state_fsm_select_channel <= SWITCH_F0_A;
408 state_fsm_select_channel <= SWITCH_F0_A;
404 ELSIF sample_f0_B_full = "11111" THEN
409 ELSIF sample_f0_B_full = "11111" THEN
405 state_fsm_select_channel <= SWITCH_F0_B;
410 state_fsm_select_channel <= SWITCH_F0_B;
406 ELSIF sample_f2_full = "11111" THEN
411 ELSIF sample_f2_full = "11111" THEN
407 state_fsm_select_channel <= SWITCH_F2;
412 state_fsm_select_channel <= SWITCH_F2;
408 END IF;
413 END IF;
409 END IF;
414 END IF;
410
415
411 WHEN SWITCH_F0_A =>
416 WHEN SWITCH_F0_A =>
412 IF sample_f0_A_empty = "11111" THEN
417 IF sample_f0_A_empty = "11111" THEN
413 state_fsm_select_channel <= IDLE;
418 state_fsm_select_channel <= IDLE;
414 END IF;
419 END IF;
415 WHEN SWITCH_F0_B =>
420 WHEN SWITCH_F0_B =>
416 IF sample_f0_B_empty = "11111" THEN
421 IF sample_f0_B_empty = "11111" THEN
417 state_fsm_select_channel <= IDLE;
422 state_fsm_select_channel <= IDLE;
418 END IF;
423 END IF;
419 WHEN SWITCH_F1 =>
424 WHEN SWITCH_F1 =>
420 IF sample_f1_empty = "11111" THEN
425 IF sample_f1_empty = "11111" THEN
421 state_fsm_select_channel <= IDLE;
426 state_fsm_select_channel <= IDLE;
422 END IF;
427 END IF;
423 WHEN SWITCH_F2 =>
428 WHEN SWITCH_F2 =>
424 IF sample_f2_empty = "11111" THEN
429 IF sample_f2_empty = "11111" THEN
425 state_fsm_select_channel <= IDLE;
430 state_fsm_select_channel <= IDLE;
426 END IF;
431 END IF;
427 WHEN OTHERS => NULL;
432 WHEN OTHERS => NULL;
428 END CASE;
433 END CASE;
429
434
430 END IF;
435 END IF;
431 END PROCESS;
436 END PROCESS;
432
437
433 PROCESS (clk, rstn)
438 PROCESS (clk, rstn)
434 BEGIN
439 BEGIN
435 IF rstn = '0' THEN
440 IF rstn = '0' THEN
436 pre_state_fsm_select_channel <= IDLE;
441 pre_state_fsm_select_channel <= IDLE;
437 ELSIF clk'EVENT AND clk = '1' THEN
442 ELSIF clk'EVENT AND clk = '1' THEN
438 pre_state_fsm_select_channel <= state_fsm_select_channel;
443 pre_state_fsm_select_channel <= state_fsm_select_channel;
439 END IF;
444 END IF;
440 END PROCESS;
445 END PROCESS;
441
446
442
447
443 -----------------------------------------------------------------------------
448 -----------------------------------------------------------------------------
444 -- SWITCH SELECT CHANNEL
449 -- SWITCH SELECT CHANNEL
445 -----------------------------------------------------------------------------
450 -----------------------------------------------------------------------------
446 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
451 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
447 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
452 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
448 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
453 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
449 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
454 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
450 (OTHERS => '1');
455 (OTHERS => '1');
451
456
452 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
457 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
453 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
458 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
454 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
459 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
455 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
460 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
456 (OTHERS => '0');
461 (OTHERS => '0');
457
462
458 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
463 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
459 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
464 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
460 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
465 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
461 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
466 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
462
467
463
468
464 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
469 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
465 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
470 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
466 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
471 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
467 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
472 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
468
473
469
474
470 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
475 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
471 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
476 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
472 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
477 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
473 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
478 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
474
479
475 -----------------------------------------------------------------------------
480 -----------------------------------------------------------------------------
476 -- FSM LOAD FFT
481 -- FSM LOAD FFT
477 -----------------------------------------------------------------------------
482 -----------------------------------------------------------------------------
478
483
479 sample_ren <= sample_ren_s WHEN ping_npong = fft_pong AND sample_load = '1' ELSE
484 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = "10" ELSE
485 sample_ren_s WHEN sample_load = '1' ELSE
480 (OTHERS => '1');
486 (OTHERS => '1');
481
487
482 PROCESS (clk, rstn)
488 PROCESS (clk, rstn)
483 BEGIN
489 BEGIN
484 IF rstn = '0' THEN
490 IF rstn = '0' THEN
485 sample_ren_s <= (OTHERS => '1');
491 sample_ren_s <= (OTHERS => '1');
486 state_fsm_load_FFT <= IDLE;
492 state_fsm_load_FFT <= IDLE;
487 status_MS_input <= (OTHERS => '0');
493 status_MS_input <= (OTHERS => '0');
488 --next_state_fsm_load_FFT <= IDLE;
494 --next_state_fsm_load_FFT <= IDLE;
489 --sample_valid <= '0';
495 --sample_valid <= '0';
490 ELSIF clk'EVENT AND clk = '1' THEN
496 ELSIF clk'EVENT AND clk = '1' THEN
491 CASE state_fsm_load_FFT IS
497 CASE state_fsm_load_FFT IS
492 WHEN IDLE =>
498 WHEN IDLE =>
493 --sample_valid <= '0';
499 --sample_valid <= '0';
494 sample_ren_s <= (OTHERS => '1');
500 sample_ren_s <= (OTHERS => '1');
495 IF sample_full = "11111" AND sample_load = '1' THEN
501 IF sample_full = "11111" AND sample_load = '1' THEN
496 state_fsm_load_FFT <= FIFO_1;
502 state_fsm_load_FFT <= FIFO_1;
497 status_MS_input <= status_channel;
503 status_MS_input <= status_channel;
498 END IF;
504 END IF;
499
505
500 WHEN FIFO_1 =>
506 WHEN FIFO_1 =>
501 sample_ren_s <= "1111" & NOT(sample_load);
507 sample_ren_s <= "1111" & NOT(sample_load);
502 IF sample_empty(0) = '1' THEN
508 IF sample_empty(0) = '1' THEN
503 sample_ren_s <= (OTHERS => '1');
509 sample_ren_s <= (OTHERS => '1');
504 state_fsm_load_FFT <= FIFO_2;
510 state_fsm_load_FFT <= FIFO_2;
505 END IF;
511 END IF;
506
512
507 WHEN FIFO_2 =>
513 WHEN FIFO_2 =>
508 sample_ren_s <= "111" & NOT(sample_load) & '1';
514 sample_ren_s <= "111" & NOT(sample_load) & '1';
509 IF sample_empty(1) = '1' THEN
515 IF sample_empty(1) = '1' THEN
510 sample_ren_s <= (OTHERS => '1');
516 sample_ren_s <= (OTHERS => '1');
511 state_fsm_load_FFT <= FIFO_3;
517 state_fsm_load_FFT <= FIFO_3;
512 END IF;
518 END IF;
513
519
514 WHEN FIFO_3 =>
520 WHEN FIFO_3 =>
515 sample_ren_s <= "11" & NOT(sample_load) & "11";
521 sample_ren_s <= "11" & NOT(sample_load) & "11";
516 IF sample_empty(2) = '1' THEN
522 IF sample_empty(2) = '1' THEN
517 sample_ren_s <= (OTHERS => '1');
523 sample_ren_s <= (OTHERS => '1');
518 state_fsm_load_FFT <= FIFO_4;
524 state_fsm_load_FFT <= FIFO_4;
519 END IF;
525 END IF;
520
526
521 WHEN FIFO_4 =>
527 WHEN FIFO_4 =>
522 sample_ren_s <= '1' & NOT(sample_load) & "111";
528 sample_ren_s <= '1' & NOT(sample_load) & "111";
523 IF sample_empty(3) = '1' THEN
529 IF sample_empty(3) = '1' THEN
524 sample_ren_s <= (OTHERS => '1');
530 sample_ren_s <= (OTHERS => '1');
525 state_fsm_load_FFT <= FIFO_5;
531 state_fsm_load_FFT <= FIFO_5;
526 END IF;
532 END IF;
527
533
528 WHEN FIFO_5 =>
534 WHEN FIFO_5 =>
529 sample_ren_s <= NOT(sample_load) & "1111";
535 sample_ren_s <= NOT(sample_load) & "1111";
530 IF sample_empty(4) = '1' THEN
536 IF sample_empty(4) = '1' THEN
531 sample_ren_s <= (OTHERS => '1');
537 sample_ren_s <= (OTHERS => '1');
532 state_fsm_load_FFT <= IDLE;
538 state_fsm_load_FFT <= IDLE;
533 END IF;
539 END IF;
534 WHEN OTHERS => NULL;
540 WHEN OTHERS => NULL;
535 END CASE;
541 END CASE;
536 END IF;
542 END IF;
537 END PROCESS;
543 END PROCESS;
538
544
539 PROCESS (clk, rstn)
545 PROCESS (clk, rstn)
540 BEGIN
546 BEGIN
541 IF rstn = '0' THEN
547 IF rstn = '0' THEN
542 sample_valid_r <= '0';
548 sample_valid_r <= '0';
543 next_state_fsm_load_FFT <= IDLE;
549 next_state_fsm_load_FFT <= IDLE;
544 ELSIF clk'EVENT AND clk = '1' THEN
550 ELSIF clk'EVENT AND clk = '1' THEN
545 next_state_fsm_load_FFT <= state_fsm_load_FFT;
551 next_state_fsm_load_FFT <= state_fsm_load_FFT;
546 IF sample_ren_s = "11111" THEN
552 IF sample_ren_s = "11111" THEN
547 sample_valid_r <= '0';
553 sample_valid_r <= '0';
548 ELSE
554 ELSE
549 sample_valid_r <= '1';
555 sample_valid_r <= '1';
550 END IF;
556 END IF;
551 END IF;
557 END IF;
552 END PROCESS;
558 END PROCESS;
553
559
554 -- sample_valid <= sample_valid_r AND sample_load;
560 sample_valid <= '0' WHEN fft_ongoing_counter = "10" ELSE sample_valid_r AND sample_load;
555 sample_valid <= sample_valid_r AND sample_load WHEN ping_npong = fft_pong ELSE '0';
556
561
557 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
562 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
558 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
563 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
559 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
564 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
560 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
565 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
561 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
566 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
562
567
563 -----------------------------------------------------------------------------
568 -----------------------------------------------------------------------------
564 -- FFT
569 -- FFT
565 -----------------------------------------------------------------------------
570 -----------------------------------------------------------------------------
566 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
571 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
567 PORT MAP (
572 PORT MAP (
568 clk => clk,
573 clk => clk,
569 rstn => rstn,
574 rstn => rstn,
570 sample_valid => sample_valid,
575 sample_valid => sample_valid,
571 fft_read => fft_read,
576 fft_read => fft_read,
572 sample_data => sample_data,
577 sample_data => sample_data,
573 sample_load => sample_load,
578 sample_load => sample_load,
574 fft_pong => fft_pong,
579 fft_pong => fft_pong,
575 fft_data_im => fft_data_im,
580 fft_data_im => fft_data_im,
576 fft_data_re => fft_data_re,
581 fft_data_re => fft_data_re,
577 fft_data_valid => fft_data_valid,
582 fft_data_valid => fft_data_valid,
578 fft_ready => fft_ready);
583 fft_ready => fft_ready);
579
584
580 observation_vector_0(11 DOWNTO 0) <= "0000" & --11 10 9 8
585 observation_vector_0(11 DOWNTO 0) <= "00" & --11 10
581 sample_load_reg & --7
586 fft_ongoing_counter & --9 8
582 ping_npong & --6
587 sample_load_rising_down & --7
583 fft_ready & --5
588 fft_ready_rising_down & --6
584 fft_data_valid & --4
589 fft_ready & --5
585 fft_pong & --3
590 fft_data_valid & --4
586 sample_load & --2
591 fft_pong & --3
587 fft_read & --1
592 sample_load & --2
588 sample_valid; --0
593 fft_read & --1
594 sample_valid; --0
589
595
590 -----------------------------------------------------------------------------
596 -----------------------------------------------------------------------------
597 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
598 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
599
591 PROCESS (clk, rstn)
600 PROCESS (clk, rstn)
592 BEGIN
601 BEGIN
593 IF rstn = '0' THEN
602 IF rstn = '0' THEN
594 ping_npong <= '0';
603 fft_ready_reg <= '0';
595 sample_load_reg <= '0';
604 sample_load_reg <= '0';
605
606 fft_ongoing_counter <= "00";
596 ELSIF clk'event AND clk = '1' THEN
607 ELSIF clk'event AND clk = '1' THEN
597 sample_load_reg <= sample_load;
608 fft_ready_reg <= fft_ready;
598 IF sample_load_reg = '1' AND sample_load = '0' THEN
609 sample_load_reg <= sample_load;
599 ping_npong <= NOT ping_npong;
610
611 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
612 CASE fft_ongoing_counter IS
613 WHEN "01" => fft_ongoing_counter <= "00";
614 WHEN "10" => fft_ongoing_counter <= "01";
615 WHEN OTHERS => NULL;
616 END CASE;
617 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
618 CASE fft_ongoing_counter IS
619 WHEN "00" => fft_ongoing_counter <= "01";
620 WHEN "01" => fft_ongoing_counter <= "10";
621 WHEN OTHERS => NULL;
622 END CASE;
600 END IF;
623 END IF;
624
601 END IF;
625 END IF;
602 END PROCESS;
626 END PROCESS;
603
627
604 -----------------------------------------------------------------------------
628 -----------------------------------------------------------------------------
605 PROCESS (clk, rstn)
629 PROCESS (clk, rstn)
606 BEGIN
630 BEGIN
607 IF rstn = '0' THEN
631 IF rstn = '0' THEN
608 state_fsm_load_MS_memory <= IDLE;
632 state_fsm_load_MS_memory <= IDLE;
609 current_fifo_load <= "00001";
633 current_fifo_load <= "00001";
610 ELSIF clk'EVENT AND clk = '1' THEN
634 ELSIF clk'EVENT AND clk = '1' THEN
611 CASE state_fsm_load_MS_memory IS
635 CASE state_fsm_load_MS_memory IS
612 WHEN IDLE =>
636 WHEN IDLE =>
613 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
637 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
614 state_fsm_load_MS_memory <= LOAD_FIFO;
638 state_fsm_load_MS_memory <= LOAD_FIFO;
615 END IF;
639 END IF;
616 WHEN LOAD_FIFO =>
640 WHEN LOAD_FIFO =>
617 IF current_fifo_full = '1' THEN
641 IF current_fifo_full = '1' THEN
618 state_fsm_load_MS_memory <= TRASH_FFT;
642 state_fsm_load_MS_memory <= TRASH_FFT;
619 END IF;
643 END IF;
620 WHEN TRASH_FFT =>
644 WHEN TRASH_FFT =>
621 IF fft_ready = '0' THEN
645 IF fft_ready = '0' THEN
622 state_fsm_load_MS_memory <= IDLE;
646 state_fsm_load_MS_memory <= IDLE;
623 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
647 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
624 END IF;
648 END IF;
625 WHEN OTHERS => NULL;
649 WHEN OTHERS => NULL;
626 END CASE;
650 END CASE;
627
651
628 END IF;
652 END IF;
629 END PROCESS;
653 END PROCESS;
630
654
631 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
655 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
632 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
656 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
633 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
657 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
634 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
658 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
635 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
659 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
636
660
637 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
661 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
638 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
662 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
639 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
663 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
640 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
664 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
641 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
665 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
642
666
643 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
667 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
644 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
668 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
645 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
669 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
646 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
670 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
647 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
671 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
648
672
649 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
673 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
650
674
651 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
675 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
652 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
676 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
653 AND state_fsm_load_MS_memory = LOAD_FIFO
677 AND state_fsm_load_MS_memory = LOAD_FIFO
654 AND current_fifo_load(I) = '1'
678 AND current_fifo_load(I) = '1'
655 ELSE '1';
679 ELSE '1';
656 END GENERATE all_fifo;
680 END GENERATE all_fifo;
657
681
658 PROCESS (clk, rstn)
682 PROCESS (clk, rstn)
659 BEGIN
683 BEGIN
660 IF rstn = '0' THEN
684 IF rstn = '0' THEN
661 MEM_IN_SM_wen <= (OTHERS => '1');
685 MEM_IN_SM_wen <= (OTHERS => '1');
662 ELSIF clk'EVENT AND clk = '1' THEN
686 ELSIF clk'EVENT AND clk = '1' THEN
663 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
687 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
664 END IF;
688 END IF;
665 END PROCESS;
689 END PROCESS;
666
690
667 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
691 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
668 (fft_data_im & fft_data_re) &
692 (fft_data_im & fft_data_re) &
669 (fft_data_im & fft_data_re) &
693 (fft_data_im & fft_data_re) &
670 (fft_data_im & fft_data_re) &
694 (fft_data_im & fft_data_re) &
671 (fft_data_im & fft_data_re);
695 (fft_data_im & fft_data_re);
672 -----------------------------------------------------------------------------
696 -----------------------------------------------------------------------------
673
697
674
698
675 -----------------------------------------------------------------------------
699 -----------------------------------------------------------------------------
676 Mem_In_SpectralMatrix : lppFIFOxN
700 Mem_In_SpectralMatrix : lppFIFOxN
677 GENERIC MAP (
701 GENERIC MAP (
678 tech => 0,
702 tech => 0,
679 Mem_use => Mem_use,
703 Mem_use => Mem_use,
680 Data_sz => 32, --16,
704 Data_sz => 32, --16,
681 Addr_sz => 7, --8
705 Addr_sz => 7, --8
682 FifoCnt => 5)
706 FifoCnt => 5)
683 PORT MAP (
707 PORT MAP (
684 clk => clk,
708 clk => clk,
685 rstn => rstn,
709 rstn => rstn,
686
710
687 ReUse => MEM_IN_SM_ReUse,
711 ReUse => MEM_IN_SM_ReUse,
688
712
689 wen => MEM_IN_SM_wen,
713 wen => MEM_IN_SM_wen,
690 wdata => MEM_IN_SM_wData,
714 wdata => MEM_IN_SM_wData,
691
715
692 ren => MEM_IN_SM_ren,
716 ren => MEM_IN_SM_ren,
693 rdata => MEM_IN_SM_rData,
717 rdata => MEM_IN_SM_rData,
694 full => MEM_IN_SM_Full,
718 full => MEM_IN_SM_Full,
695 empty => MEM_IN_SM_Empty,
719 empty => MEM_IN_SM_Empty,
696 almost_full => OPEN);
720 almost_full => OPEN);
697
721
698 -----------------------------------------------------------------------------
722 -----------------------------------------------------------------------------
699
723
700 observation_vector_1(11 DOWNTO 0) <= '0' &
724 observation_vector_1(11 DOWNTO 0) <= '0' &
701 SM_correlation_done & --4
725 SM_correlation_done & --4
702 SM_correlation_auto & --3
726 SM_correlation_auto & --3
703 SM_correlation_start &
727 SM_correlation_start &
704 SM_correlation_start & --7
728 SM_correlation_start & --7
705 status_MS_input(1 DOWNTO 0)& --6..5
729 status_MS_input(1 DOWNTO 0)& --6..5
706 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
730 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
707
731
708 -----------------------------------------------------------------------------
732 -----------------------------------------------------------------------------
709 MS_control_1 : MS_control
733 MS_control_1 : MS_control
710 PORT MAP (
734 PORT MAP (
711 clk => clk,
735 clk => clk,
712 rstn => rstn,
736 rstn => rstn,
713
737
714 current_status_ms => status_MS_input,
738 current_status_ms => status_MS_input,
715
739
716 fifo_in_lock => MEM_IN_SM_locked,
740 fifo_in_lock => MEM_IN_SM_locked,
717 fifo_in_data => MEM_IN_SM_rdata,
741 fifo_in_data => MEM_IN_SM_rdata,
718 fifo_in_full => MEM_IN_SM_Full,
742 fifo_in_full => MEM_IN_SM_Full,
719 fifo_in_empty => MEM_IN_SM_Empty,
743 fifo_in_empty => MEM_IN_SM_Empty,
720 fifo_in_ren => MEM_IN_SM_ren,
744 fifo_in_ren => MEM_IN_SM_ren,
721 fifo_in_reuse => MEM_IN_SM_ReUse,
745 fifo_in_reuse => MEM_IN_SM_ReUse,
722
746
723 fifo_out_data => SM_in_data,
747 fifo_out_data => SM_in_data,
724 fifo_out_ren => SM_in_ren,
748 fifo_out_ren => SM_in_ren,
725 fifo_out_empty => SM_in_empty,
749 fifo_out_empty => SM_in_empty,
726
750
727 current_status_component => status_component,
751 current_status_component => status_component,
728
752
729 correlation_start => SM_correlation_start,
753 correlation_start => SM_correlation_start,
730 correlation_auto => SM_correlation_auto,
754 correlation_auto => SM_correlation_auto,
731 correlation_done => SM_correlation_done);
755 correlation_done => SM_correlation_done);
732
756
733
757
734 MS_calculation_1 : MS_calculation
758 MS_calculation_1 : MS_calculation
735 PORT MAP (
759 PORT MAP (
736 clk => clk,
760 clk => clk,
737 rstn => rstn,
761 rstn => rstn,
738
762
739 fifo_in_data => SM_in_data,
763 fifo_in_data => SM_in_data,
740 fifo_in_ren => SM_in_ren,
764 fifo_in_ren => SM_in_ren,
741 fifo_in_empty => SM_in_empty,
765 fifo_in_empty => SM_in_empty,
742
766
743 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
767 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
744 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
768 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
745 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
769 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
746
770
747 correlation_start => SM_correlation_start,
771 correlation_start => SM_correlation_start,
748 correlation_auto => SM_correlation_auto,
772 correlation_auto => SM_correlation_auto,
749 correlation_begin => SM_correlation_begin,
773 correlation_begin => SM_correlation_begin,
750 correlation_done => SM_correlation_done);
774 correlation_done => SM_correlation_done);
751
775
752 -----------------------------------------------------------------------------
776 -----------------------------------------------------------------------------
753 PROCESS (clk, rstn)
777 PROCESS (clk, rstn)
754 BEGIN -- PROCESS
778 BEGIN -- PROCESS
755 IF rstn = '0' THEN -- asynchronous reset (active low)
779 IF rstn = '0' THEN -- asynchronous reset (active low)
756 current_matrix_write <= '0';
780 current_matrix_write <= '0';
757 current_matrix_wait_empty <= '1';
781 current_matrix_wait_empty <= '1';
758 status_component_fifo_0 <= (OTHERS => '0');
782 status_component_fifo_0 <= (OTHERS => '0');
759 status_component_fifo_1 <= (OTHERS => '0');
783 status_component_fifo_1 <= (OTHERS => '0');
760 status_component_fifo_0_end <= '0';
784 status_component_fifo_0_end <= '0';
761 status_component_fifo_1_end <= '0';
785 status_component_fifo_1_end <= '0';
762 SM_correlation_done_reg1 <= '0';
786 SM_correlation_done_reg1 <= '0';
763 SM_correlation_done_reg2 <= '0';
787 SM_correlation_done_reg2 <= '0';
764 SM_correlation_done_reg3 <= '0';
788 SM_correlation_done_reg3 <= '0';
765
789
766 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
790 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
767 SM_correlation_done_reg1 <= SM_correlation_done;
791 SM_correlation_done_reg1 <= SM_correlation_done;
768 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
792 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
769 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
793 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
770 status_component_fifo_0_end <= '0';
794 status_component_fifo_0_end <= '0';
771 status_component_fifo_1_end <= '0';
795 status_component_fifo_1_end <= '0';
772 IF SM_correlation_begin = '1' THEN
796 IF SM_correlation_begin = '1' THEN
773 IF current_matrix_write = '0' THEN
797 IF current_matrix_write = '0' THEN
774 status_component_fifo_0 <= status_component;
798 status_component_fifo_0 <= status_component;
775 ELSE
799 ELSE
776 status_component_fifo_1 <= status_component;
800 status_component_fifo_1 <= status_component;
777 END IF;
801 END IF;
778 END IF;
802 END IF;
779
803
780 IF SM_correlation_done_reg3 = '1' THEN
804 IF SM_correlation_done_reg3 = '1' THEN
781 IF current_matrix_write = '0' THEN
805 IF current_matrix_write = '0' THEN
782 status_component_fifo_0_end <= '1';
806 status_component_fifo_0_end <= '1';
783 ELSE
807 ELSE
784 status_component_fifo_1_end <= '1';
808 status_component_fifo_1_end <= '1';
785 END IF;
809 END IF;
786 current_matrix_wait_empty <= '1';
810 current_matrix_wait_empty <= '1';
787 current_matrix_write <= NOT current_matrix_write;
811 current_matrix_write <= NOT current_matrix_write;
788 END IF;
812 END IF;
789
813
790 IF current_matrix_wait_empty <= '1' THEN
814 IF current_matrix_wait_empty <= '1' THEN
791 IF current_matrix_write = '0' THEN
815 IF current_matrix_write = '0' THEN
792 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
816 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
793 ELSE
817 ELSE
794 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
818 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
795 END IF;
819 END IF;
796 END IF;
820 END IF;
797
821
798 END IF;
822 END IF;
799 END PROCESS;
823 END PROCESS;
800
824
801 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
825 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
802 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
826 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
803 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
827 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
804 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
828 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
805 '1' WHEN current_matrix_wait_empty = '1' ELSE
829 '1' WHEN current_matrix_wait_empty = '1' ELSE
806 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
830 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
807 MEM_OUT_SM_Full(1);
831 MEM_OUT_SM_Full(1);
808
832
809 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
833 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
810 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
834 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
811
835
812 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
836 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
813 -----------------------------------------------------------------------------
837 -----------------------------------------------------------------------------
814
838
815 Mem_Out_SpectralMatrix : lppFIFOxN
839 Mem_Out_SpectralMatrix : lppFIFOxN
816 GENERIC MAP (
840 GENERIC MAP (
817 tech => 0,
841 tech => 0,
818 Mem_use => Mem_use,
842 Mem_use => Mem_use,
819 Data_sz => 32,
843 Data_sz => 32,
820 Addr_sz => 8,
844 Addr_sz => 8,
821 FifoCnt => 2)
845 FifoCnt => 2)
822 PORT MAP (
846 PORT MAP (
823 clk => clk,
847 clk => clk,
824 rstn => rstn,
848 rstn => rstn,
825
849
826 ReUse => (OTHERS => '0'),
850 ReUse => (OTHERS => '0'),
827
851
828 wen => MEM_OUT_SM_Write,
852 wen => MEM_OUT_SM_Write,
829 wdata => MEM_OUT_SM_Data_in,
853 wdata => MEM_OUT_SM_Data_in,
830
854
831 ren => MEM_OUT_SM_Read,
855 ren => MEM_OUT_SM_Read,
832 rdata => MEM_OUT_SM_Data_out,
856 rdata => MEM_OUT_SM_Data_out,
833
857
834 full => MEM_OUT_SM_Full,
858 full => MEM_OUT_SM_Full,
835 empty => MEM_OUT_SM_Empty,
859 empty => MEM_OUT_SM_Empty,
836 almost_full => OPEN);
860 almost_full => OPEN);
837
861
838 -----------------------------------------------------------------------------
862 -----------------------------------------------------------------------------
839 -- MEM_OUT_SM_Read <= "00";
863 -- MEM_OUT_SM_Read <= "00";
840 PROCESS (clk, rstn)
864 PROCESS (clk, rstn)
841 BEGIN
865 BEGIN
842 IF rstn = '0' THEN
866 IF rstn = '0' THEN
843 fifo_0_ready <= '0';
867 fifo_0_ready <= '0';
844 fifo_1_ready <= '0';
868 fifo_1_ready <= '0';
845 fifo_ongoing <= '0';
869 fifo_ongoing <= '0';
846 ELSIF clk'EVENT AND clk = '1' THEN
870 ELSIF clk'EVENT AND clk = '1' THEN
847 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
871 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
848 fifo_ongoing <= '1';
872 fifo_ongoing <= '1';
849 fifo_0_ready <= '0';
873 fifo_0_ready <= '0';
850 ELSIF status_component_fifo_0_end = '1' THEN
874 ELSIF status_component_fifo_0_end = '1' THEN
851 fifo_0_ready <= '1';
875 fifo_0_ready <= '1';
852 END IF;
876 END IF;
853
877
854 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
878 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
855 fifo_ongoing <= '0';
879 fifo_ongoing <= '0';
856 fifo_1_ready <= '0';
880 fifo_1_ready <= '0';
857 ELSIF status_component_fifo_1_end = '1' THEN
881 ELSIF status_component_fifo_1_end = '1' THEN
858 fifo_1_ready <= '1';
882 fifo_1_ready <= '1';
859 END IF;
883 END IF;
860
884
861 END IF;
885 END IF;
862 END PROCESS;
886 END PROCESS;
863
887
864 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
888 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
865 '1' WHEN fifo_0_ready = '0' ELSE
889 '1' WHEN fifo_0_ready = '0' ELSE
866 FSM_DMA_fifo_ren;
890 FSM_DMA_fifo_ren;
867
891
868 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
892 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
869 '1' WHEN fifo_1_ready = '0' ELSE
893 '1' WHEN fifo_1_ready = '0' ELSE
870 FSM_DMA_fifo_ren;
894 FSM_DMA_fifo_ren;
871
895
872 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
896 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
873 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
897 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
874 '1';
898 '1';
875
899
876 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
900 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
877 status_component_fifo_1;
901 status_component_fifo_1;
878
902
879 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
903 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
880 MEM_OUT_SM_Data_out(63 DOWNTO 32);
904 MEM_OUT_SM_Data_out(63 DOWNTO 32);
881
905
882 -----------------------------------------------------------------------------
906 -----------------------------------------------------------------------------
883 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
907 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
884 PORT MAP (
908 PORT MAP (
885 HCLK => clk,
909 HCLK => clk,
886 HRESETn => rstn,
910 HRESETn => rstn,
887
911
888 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
912 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
889 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
913 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
890 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
914 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
891 fifo_data => FSM_DMA_fifo_data,
915 fifo_data => FSM_DMA_fifo_data,
892 fifo_empty => FSM_DMA_fifo_empty,
916 fifo_empty => FSM_DMA_fifo_empty,
893 fifo_ren => FSM_DMA_fifo_ren,
917 fifo_ren => FSM_DMA_fifo_ren,
894
918
895 dma_addr => dma_addr,
919 dma_addr => dma_addr,
896 dma_data => dma_data,
920 dma_data => dma_data,
897 dma_valid => dma_valid,
921 dma_valid => dma_valid,
898 dma_valid_burst => dma_valid_burst,
922 dma_valid_burst => dma_valid_burst,
899 dma_ren => dma_ren,
923 dma_ren => dma_ren,
900 dma_done => dma_done,
924 dma_done => dma_done,
901
925
902 ready_matrix_f0 => ready_matrix_f0,
926 ready_matrix_f0 => ready_matrix_f0,
903 ready_matrix_f1 => ready_matrix_f1,
927 ready_matrix_f1 => ready_matrix_f1,
904 ready_matrix_f2 => ready_matrix_f2,
928 ready_matrix_f2 => ready_matrix_f2,
905
929
906 error_bad_component_error => error_bad_component_error,
930 error_bad_component_error => error_bad_component_error,
907 error_buffer_full => error_buffer_full,
931 error_buffer_full => error_buffer_full,
908
932
909 debug_reg => debug_reg,
933 debug_reg => debug_reg,
910 status_ready_matrix_f0 => status_ready_matrix_f0,
934 status_ready_matrix_f0 => status_ready_matrix_f0,
911 status_ready_matrix_f1 => status_ready_matrix_f1,
935 status_ready_matrix_f1 => status_ready_matrix_f1,
912 status_ready_matrix_f2 => status_ready_matrix_f2,
936 status_ready_matrix_f2 => status_ready_matrix_f2,
913
937
914 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
938 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
915 config_active_interruption_onError => config_active_interruption_onError,
939 config_active_interruption_onError => config_active_interruption_onError,
916
940
917 addr_matrix_f0 => addr_matrix_f0,
941 addr_matrix_f0 => addr_matrix_f0,
918 addr_matrix_f1 => addr_matrix_f1,
942 addr_matrix_f1 => addr_matrix_f1,
919 addr_matrix_f2 => addr_matrix_f2,
943 addr_matrix_f2 => addr_matrix_f2,
920
944
921 matrix_time_f0 => matrix_time_f0,
945 matrix_time_f0 => matrix_time_f0,
922 matrix_time_f1 => matrix_time_f1,
946 matrix_time_f1 => matrix_time_f1,
923 matrix_time_f2 => matrix_time_f2
947 matrix_time_f2 => matrix_time_f2
924 );
948 );
925 -----------------------------------------------------------------------------
949 -----------------------------------------------------------------------------
926
950
927
951
928
952
929
953
930
954
931 -----------------------------------------------------------------------------
955 -----------------------------------------------------------------------------
932 -- TIME MANAGMENT
956 -- TIME MANAGMENT
933 -----------------------------------------------------------------------------
957 -----------------------------------------------------------------------------
934 all_time <= coarse_time & fine_time;
958 all_time <= coarse_time & fine_time;
935 --
959 --
936 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
960 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
937 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
961 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
938 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
962 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
939 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
963 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
940
964
941 all_time_reg: FOR I IN 0 TO 3 GENERATE
965 all_time_reg: FOR I IN 0 TO 3 GENERATE
942
966
943 PROCESS (clk, rstn)
967 PROCESS (clk, rstn)
944 BEGIN
968 BEGIN
945 IF rstn = '0' THEN
969 IF rstn = '0' THEN
946 f_empty_reg(I) <= '1';
970 f_empty_reg(I) <= '1';
947 ELSIF clk'event AND clk = '1' THEN
971 ELSIF clk'event AND clk = '1' THEN
948 f_empty_reg(I) <= f_empty(I);
972 f_empty_reg(I) <= f_empty(I);
949 END IF;
973 END IF;
950 END PROCESS;
974 END PROCESS;
951
975
952 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
976 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
953
977
954 s_m_t_m_f0_A : spectral_matrix_time_managment
978 s_m_t_m_f0_A : spectral_matrix_time_managment
955 PORT MAP (
979 PORT MAP (
956 clk => clk,
980 clk => clk,
957 rstn => rstn,
981 rstn => rstn,
958 time_in => all_time,
982 time_in => all_time,
959 update_1 => time_update_f(I),
983 update_1 => time_update_f(I),
960 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
984 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
961 );
985 );
962
986
963 END GENERATE all_time_reg;
987 END GENERATE all_time_reg;
964
988
965 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
989 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
966 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
990 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
967 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
991 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
968 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
992 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
969
993
970 -----------------------------------------------------------------------------
994 -----------------------------------------------------------------------------
971
995
972 END Behavioral; No newline at end of file
996 END Behavioral;
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