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ajout de downsampler 6 apres le cic_lfr
pellion -
r497:2e89e897ccde (MINI-LFR) WFP_MS-0-1-42 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 196 --
197 197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 198
199 199 BEGIN -- beh
200 200
201 201 -----------------------------------------------------------------------------
202 202 -- CLK
203 203 -----------------------------------------------------------------------------
204 204
205 205 --PROCESS(clk_50)
206 206 --BEGIN
207 207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
208 208 -- clk_50_s <= NOT clk_50_s;
209 209 -- END IF;
210 210 --END PROCESS;
211 211
212 212 --PROCESS(clk_50_s)
213 213 --BEGIN
214 214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
215 215 -- clk_25 <= NOT clk_25;
216 216 -- END IF;
217 217 --END PROCESS;
218 218
219 219 --PROCESS(clk_49)
220 220 --BEGIN
221 221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
222 222 -- clk_24 <= NOT clk_24;
223 223 -- END IF;
224 224 --END PROCESS;
225 225
226 226 --PROCESS(clk_25)
227 227 --BEGIN
228 228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
229 229 -- rstn_25 <= reset;
230 230 -- END IF;
231 231 --END PROCESS;
232 232
233 233 PROCESS (clk_50, reset)
234 234 BEGIN -- PROCESS
235 235 IF reset = '0' THEN -- asynchronous reset (active low)
236 236 clk_50_s <= '0';
237 237 rstn_50 <= '0';
238 238 rstn_50_d1 <= '0';
239 239 rstn_50_d2 <= '0';
240 240 rstn_50_d3 <= '0';
241 241
242 242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
243 243 clk_50_s <= NOT clk_50_s;
244 244 rstn_50_d1 <= '1';
245 245 rstn_50_d2 <= rstn_50_d1;
246 246 rstn_50_d3 <= rstn_50_d2;
247 247 rstn_50 <= rstn_50_d3;
248 248 END IF;
249 249 END PROCESS;
250 250
251 251 PROCESS (clk_50_s, rstn_50)
252 252 BEGIN -- PROCESS
253 253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
254 254 clk_25 <= '0';
255 255 rstn_25 <= '0';
256 256 rstn_25_d1 <= '0';
257 257 rstn_25_d2 <= '0';
258 258 rstn_25_d3 <= '0';
259 259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
260 260 clk_25 <= NOT clk_25;
261 261 rstn_25_d1 <= '1';
262 262 rstn_25_d2 <= rstn_25_d1;
263 263 rstn_25_d3 <= rstn_25_d2;
264 264 rstn_25 <= rstn_25_d3;
265 265 END IF;
266 266 END PROCESS;
267 267
268 268 PROCESS (clk_49, reset)
269 269 BEGIN -- PROCESS
270 270 IF reset = '0' THEN -- asynchronous reset (active low)
271 271 clk_24 <= '0';
272 272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
273 273 clk_24 <= NOT clk_24;
274 274 END IF;
275 275 END PROCESS;
276 276
277 277 -----------------------------------------------------------------------------
278 278
279 279 PROCESS (clk_25, rstn_25)
280 280 BEGIN -- PROCESS
281 281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
282 282 LED0 <= '0';
283 283 LED1 <= '0';
284 284 LED2 <= '0';
285 285 --IO1 <= '0';
286 286 --IO2 <= '1';
287 287 --IO3 <= '0';
288 288 --IO4 <= '0';
289 289 --IO5 <= '0';
290 290 --IO6 <= '0';
291 291 --IO7 <= '0';
292 292 --IO8 <= '0';
293 293 --IO9 <= '0';
294 294 --IO10 <= '0';
295 295 --IO11 <= '0';
296 296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
297 297 LED0 <= '0';
298 298 LED1 <= '1';
299 299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
300 300 --IO1 <= '1';
301 301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
302 302 --IO3 <= ADC_SDO(0);
303 303 --IO4 <= ADC_SDO(1);
304 304 --IO5 <= ADC_SDO(2);
305 305 --IO6 <= ADC_SDO(3);
306 306 --IO7 <= ADC_SDO(4);
307 307 --IO8 <= ADC_SDO(5);
308 308 --IO9 <= ADC_SDO(6);
309 309 --IO10 <= ADC_SDO(7);
310 310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
311 311 END IF;
312 312 END PROCESS;
313 313
314 314 PROCESS (clk_24, rstn_25)
315 315 BEGIN -- PROCESS
316 316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
317 317 I00_s <= '0';
318 318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
319 319 I00_s <= NOT I00_s;
320 320 END IF;
321 321 END PROCESS;
322 322 -- IO0 <= I00_s;
323 323
324 324 --UARTs
325 325 nCTS1 <= '1';
326 326 nCTS2 <= '1';
327 327 nDCD2 <= '1';
328 328
329 329 --EXT CONNECTOR
330 330
331 331 --SPACE WIRE
332 332
333 333 leon3_soc_1 : leon3_soc
334 334 GENERIC MAP (
335 335 fabtech => apa3e,
336 336 memtech => apa3e,
337 337 padtech => inferred,
338 338 clktech => inferred,
339 339 disas => 0,
340 340 dbguart => 0,
341 341 pclow => 2,
342 342 clk_freq => 25000,
343 343 NB_CPU => 1,
344 344 ENABLE_FPU => 1,
345 345 FPU_NETLIST => 0,
346 346 ENABLE_DSU => 1,
347 347 ENABLE_AHB_UART => 1,
348 348 ENABLE_APB_UART => 1,
349 349 ENABLE_IRQMP => 1,
350 350 ENABLE_GPT => 1,
351 351 NB_AHB_MASTER => NB_AHB_MASTER,
352 352 NB_AHB_SLAVE => NB_AHB_SLAVE,
353 353 NB_APB_SLAVE => NB_APB_SLAVE,
354 354 ADDRESS_SIZE => 20,
355 355 USES_IAP_MEMCTRLR => 0)
356 356 PORT MAP (
357 357 clk => clk_25,
358 358 reset => rstn_25,
359 359 errorn => errorn,
360 360 ahbrxd => TXD1,
361 361 ahbtxd => RXD1,
362 362 urxd1 => TXD2,
363 363 utxd1 => RXD2,
364 364 address => SRAM_A,
365 365 data => SRAM_DQ,
366 366 nSRAM_BE0 => SRAM_nBE(0),
367 367 nSRAM_BE1 => SRAM_nBE(1),
368 368 nSRAM_BE2 => SRAM_nBE(2),
369 369 nSRAM_BE3 => SRAM_nBE(3),
370 370 nSRAM_WE => SRAM_nWE,
371 371 nSRAM_CE => SRAM_CE_s,
372 372 nSRAM_OE => SRAM_nOE,
373 373 nSRAM_READY => '0',
374 374 SRAM_MBE => OPEN,
375 375 apbi_ext => apbi_ext,
376 376 apbo_ext => apbo_ext,
377 377 ahbi_s_ext => ahbi_s_ext,
378 378 ahbo_s_ext => ahbo_s_ext,
379 379 ahbi_m_ext => ahbi_m_ext,
380 380 ahbo_m_ext => ahbo_m_ext);
381 381
382 382 SRAM_CE <= SRAM_CE_s(0);
383 383 -------------------------------------------------------------------------------
384 384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
385 385 -------------------------------------------------------------------------------
386 386 apb_lfr_time_management_1 : apb_lfr_time_management
387 387 GENERIC MAP (
388 388 pindex => 6,
389 389 paddr => 6,
390 390 pmask => 16#fff#,
391 391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
392 392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
393 393 PORT MAP (
394 394 clk25MHz => clk_25,
395 395 clk24_576MHz => clk_24, -- 49.152MHz/2
396 396 resetn => rstn_25,
397 397 grspw_tick => swno.tickout,
398 398 apbi => apbi_ext,
399 399 apbo => apbo_ext(6),
400 400 coarse_time => coarse_time,
401 401 fine_time => fine_time,
402 402 LFR_soft_rstn => LFR_soft_rstn
403 403 );
404 404
405 405 -----------------------------------------------------------------------
406 406 --- SpaceWire --------------------------------------------------------
407 407 -----------------------------------------------------------------------
408 408
409 409 SPW_EN <= '1';
410 410
411 411 spw_clk <= clk_50_s;
412 412 spw_rxtxclk <= spw_clk;
413 413 spw_rxclkn <= NOT spw_rxtxclk;
414 414
415 415 -- PADS for SPW1
416 416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
417 417 PORT MAP (SPW_NOM_DIN, dtmp(0));
418 418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
419 419 PORT MAP (SPW_NOM_SIN, stmp(0));
420 420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
421 421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
422 422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
423 423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
424 424 -- PADS FOR SPW2
425 425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
426 426 PORT MAP (SPW_RED_SIN, dtmp(1));
427 427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 428 PORT MAP (SPW_RED_DIN, stmp(1));
429 429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
430 430 PORT MAP (SPW_RED_DOUT, swno.d(1));
431 431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
432 432 PORT MAP (SPW_RED_SOUT, swno.s(1));
433 433
434 434 -- GRSPW PHY
435 435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
436 436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
437 437 spw_phy0 : grspw_phy
438 438 GENERIC MAP(
439 439 tech => apa3e,
440 440 rxclkbuftype => 1,
441 441 scantest => 0)
442 442 PORT MAP(
443 443 rxrst => swno.rxrst,
444 444 di => dtmp(j),
445 445 si => stmp(j),
446 446 rxclko => spw_rxclk(j),
447 447 do => swni.d(j),
448 448 ndo => swni.nd(j*5+4 DOWNTO j*5),
449 449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
450 450 END GENERATE spw_inputloop;
451 451
452 452 swni.rmapnodeaddr <= (OTHERS => '0');
453 453
454 454 -- SPW core
455 455 sw0 : grspwm GENERIC MAP(
456 456 tech => apa3e,
457 457 hindex => 1,
458 458 pindex => 5,
459 459 paddr => 5,
460 460 pirq => 11,
461 461 sysfreq => 25000, -- CPU_FREQ
462 462 rmap => 1,
463 463 rmapcrc => 1,
464 464 fifosize1 => 16,
465 465 fifosize2 => 16,
466 466 rxclkbuftype => 1,
467 467 rxunaligned => 0,
468 468 rmapbufs => 4,
469 469 ft => 0,
470 470 netlist => 0,
471 471 ports => 2,
472 472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
473 473 memtech => apa3e,
474 474 destkey => 2,
475 475 spwcore => 1
476 476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
477 477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
478 478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
479 479 )
480 480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
481 481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
482 482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
483 483 swni, swno);
484 484
485 485 swni.tickin <= '0';
486 486 swni.rmapen <= '1';
487 487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
488 488 swni.tickinraw <= '0';
489 489 swni.timein <= (OTHERS => '0');
490 490 swni.dcrstval <= (OTHERS => '0');
491 491 swni.timerrstval <= (OTHERS => '0');
492 492
493 493 -------------------------------------------------------------------------------
494 494 -- LFR ------------------------------------------------------------------------
495 495 -------------------------------------------------------------------------------
496 496
497 497
498 498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
499 499 --LFR_rstn <= rstn_25;
500 500
501 501 lpp_lfr_1 : lpp_lfr
502 502 GENERIC MAP (
503 503 Mem_use => use_RAM,
504 504 nb_data_by_buffer_size => 32,
505 505 nb_snapshot_param_size => 32,
506 506 delta_vector_size => 32,
507 507 delta_vector_size_f0_2 => 7, -- log2(96)
508 508 pindex => 15,
509 509 paddr => 15,
510 510 pmask => 16#fff#,
511 511 pirq_ms => 6,
512 512 pirq_wfp => 14,
513 513 hindex => 2,
514 top_lfr_version => X"000129") -- aa.bb.cc version
514 top_lfr_version => X"00012A") -- aa.bb.cc version
515 515 PORT MAP (
516 516 clk => clk_25,
517 517 rstn => LFR_rstn,
518 518 sample_B => sample_s(2 DOWNTO 0),
519 519 sample_E => sample_s(7 DOWNTO 3),
520 520 sample_val => sample_val,
521 521 apbi => apbi_ext,
522 522 apbo => apbo_ext(15),
523 523 ahbi => ahbi_m_ext,
524 524 ahbo => ahbo_m_ext(2),
525 525 coarse_time => coarse_time,
526 526 fine_time => fine_time,
527 527 data_shaping_BW => bias_fail_sw_sig,
528 528 debug_vector => lfr_debug_vector,
529 529 debug_vector_ms => lfr_debug_vector_ms
530 530 );
531 531
532 532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
533 533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
534 534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
535 535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
536 536 IO0 <= rstn_25;
537 537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
538 538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
539 539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
540 540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
541 541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
542 542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
543 543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
544 544
545 545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
546 546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
547 547 END GENERATE all_sample;
548 548
549 549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
550 550 GENERIC MAP(
551 551 ChannelCount => 8,
552 552 SampleNbBits => 14,
553 553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
554 554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
555 555 PORT MAP (
556 556 -- CONV
557 557 cnv_clk => clk_24,
558 558 cnv_rstn => rstn_25,
559 559 cnv => ADC_nCS_sig,
560 560 -- DATA
561 561 clk => clk_25,
562 562 rstn => rstn_25,
563 563 sck => ADC_CLK_sig,
564 564 sdo => ADC_SDO_sig,
565 565 -- SAMPLE
566 566 sample => sample,
567 567 sample_val => sample_val);
568 568
569 569 --IO10 <= ADC_SDO_sig(5);
570 570 --IO9 <= ADC_SDO_sig(4);
571 571 --IO8 <= ADC_SDO_sig(3);
572 572
573 573 ADC_nCS <= ADC_nCS_sig;
574 574 ADC_CLK <= ADC_CLK_sig;
575 575 ADC_SDO_sig <= ADC_SDO;
576 576
577 577 ----------------------------------------------------------------------
578 578 --- GPIO -----------------------------------------------------------
579 579 ----------------------------------------------------------------------
580 580
581 581 grgpio0 : grgpio
582 582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
583 583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
584 584
585 585 gpioi.sig_en <= (OTHERS => '0');
586 586 gpioi.sig_in <= (OTHERS => '0');
587 587 gpioi.din <= (OTHERS => '0');
588 588 --pio_pad_0 : iopad
589 589 -- GENERIC MAP (tech => CFG_PADTECH)
590 590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
591 591 --pio_pad_1 : iopad
592 592 -- GENERIC MAP (tech => CFG_PADTECH)
593 593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
594 594 --pio_pad_2 : iopad
595 595 -- GENERIC MAP (tech => CFG_PADTECH)
596 596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
597 597 --pio_pad_3 : iopad
598 598 -- GENERIC MAP (tech => CFG_PADTECH)
599 599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
600 600 --pio_pad_4 : iopad
601 601 -- GENERIC MAP (tech => CFG_PADTECH)
602 602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
603 603 --pio_pad_5 : iopad
604 604 -- GENERIC MAP (tech => CFG_PADTECH)
605 605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
606 606 --pio_pad_6 : iopad
607 607 -- GENERIC MAP (tech => CFG_PADTECH)
608 608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
609 609 --pio_pad_7 : iopad
610 610 -- GENERIC MAP (tech => CFG_PADTECH)
611 611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
612 612
613 613 PROCESS (clk_25, rstn_25)
614 614 BEGIN -- PROCESS
615 615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
616 616 -- --IO0 <= '0';
617 617 -- IO1 <= '0';
618 618 -- IO2 <= '0';
619 619 -- IO3 <= '0';
620 620 -- IO4 <= '0';
621 621 -- IO5 <= '0';
622 622 -- IO6 <= '0';
623 623 -- IO7 <= '0';
624 624 IO8 <= '0';
625 625 IO9 <= '0';
626 626 IO10 <= '0';
627 627 IO11 <= '0';
628 628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
629 629 CASE gpioo.dout(2 DOWNTO 0) IS
630 630 WHEN "011" =>
631 631 -- --IO0 <= observation_reg(0 );
632 632 -- IO1 <= observation_reg(1 );
633 633 -- IO2 <= observation_reg(2 );
634 634 -- IO3 <= observation_reg(3 );
635 635 -- IO4 <= observation_reg(4 );
636 636 -- IO5 <= observation_reg(5 );
637 637 -- IO6 <= observation_reg(6 );
638 638 -- IO7 <= observation_reg(7 );
639 639 IO8 <= observation_reg(8);
640 640 IO9 <= observation_reg(9);
641 641 IO10 <= observation_reg(10);
642 642 IO11 <= observation_reg(11);
643 643 WHEN "001" =>
644 644 -- --IO0 <= observation_reg(0 + 12);
645 645 -- IO1 <= observation_reg(1 + 12);
646 646 -- IO2 <= observation_reg(2 + 12);
647 647 -- IO3 <= observation_reg(3 + 12);
648 648 -- IO4 <= observation_reg(4 + 12);
649 649 -- IO5 <= observation_reg(5 + 12);
650 650 -- IO6 <= observation_reg(6 + 12);
651 651 -- IO7 <= observation_reg(7 + 12);
652 652 IO8 <= observation_reg(8 + 12);
653 653 IO9 <= observation_reg(9 + 12);
654 654 IO10 <= observation_reg(10 + 12);
655 655 IO11 <= observation_reg(11 + 12);
656 656 WHEN "010" =>
657 657 -- --IO0 <= observation_reg(0 + 12 + 12);
658 658 -- IO1 <= observation_reg(1 + 12 + 12);
659 659 -- IO2 <= observation_reg(2 + 12 + 12);
660 660 -- IO3 <= observation_reg(3 + 12 + 12);
661 661 -- IO4 <= observation_reg(4 + 12 + 12);
662 662 -- IO5 <= observation_reg(5 + 12 + 12);
663 663 -- IO6 <= observation_reg(6 + 12 + 12);
664 664 -- IO7 <= observation_reg(7 + 12 + 12);
665 665 IO8 <= '0';
666 666 IO9 <= '0';
667 667 IO10 <= '0';
668 668 IO11 <= '0';
669 669 WHEN "000" =>
670 670 -- --IO0 <= observation_vector_0(0 );
671 671 -- IO1 <= observation_vector_0(1 );
672 672 -- IO2 <= observation_vector_0(2 );
673 673 -- IO3 <= observation_vector_0(3 );
674 674 -- IO4 <= observation_vector_0(4 );
675 675 -- IO5 <= observation_vector_0(5 );
676 676 -- IO6 <= observation_vector_0(6 );
677 677 -- IO7 <= observation_vector_0(7 );
678 678 IO8 <= observation_vector_0(8);
679 679 IO9 <= observation_vector_0(9);
680 680 IO10 <= observation_vector_0(10);
681 681 IO11 <= observation_vector_0(11);
682 682 WHEN "100" =>
683 683 -- --IO0 <= observation_vector_1(0 );
684 684 -- IO1 <= observation_vector_1(1 );
685 685 -- IO2 <= observation_vector_1(2 );
686 686 -- IO3 <= observation_vector_1(3 );
687 687 -- IO4 <= observation_vector_1(4 );
688 688 -- IO5 <= observation_vector_1(5 );
689 689 -- IO6 <= observation_vector_1(6 );
690 690 -- IO7 <= observation_vector_1(7 );
691 691 IO8 <= observation_vector_1(8);
692 692 IO9 <= observation_vector_1(9);
693 693 IO10 <= observation_vector_1(10);
694 694 IO11 <= observation_vector_1(11);
695 695 WHEN OTHERS => NULL;
696 696 END CASE;
697 697
698 698 END IF;
699 699 END PROCESS;
700 700 -----------------------------------------------------------------------------
701 701 --
702 702 -----------------------------------------------------------------------------
703 703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
704 704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
705 705 apbo_ext(I) <= apb_none;
706 706 END GENERATE apbo_ext_not_used;
707 707 END GENERATE all_apbo_ext;
708 708
709 709
710 710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
711 711 ahbo_s_ext(I) <= ahbs_none;
712 712 END GENERATE all_ahbo_ext;
713 713
714 714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
715 715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
716 716 ahbo_m_ext(I) <= ahbm_none;
717 717 END GENERATE ahbo_m_ext_not_used;
718 718 END GENERATE all_ahbo_m_ext;
719 719
720 720 END beh;
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@@ -1,376 +1,419
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY lpp;
28 28 USE lpp.lpp_ad_conv.ALL;
29 29 USE lpp.iir_filter.ALL;
30 30 USE lpp.FILTERcfg.ALL;
31 31 USE lpp.lpp_memory.ALL;
32 32 USE lpp.lpp_waveform_pkg.ALL;
33 33 USE lpp.cic_pkg.ALL;
34 34 USE data_type_pkg.ALL;
35 35
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 39 LIBRARY grlib;
40 40 USE grlib.amba.ALL;
41 41 USE grlib.stdlib.ALL;
42 42 USE grlib.devices.ALL;
43 43 USE GRLIB.DMA2AHB_Package.ALL;
44 44
45 45 ENTITY lpp_lfr_filter IS
46 46 GENERIC(
47 47 Mem_use : INTEGER := use_RAM
48 48 );
49 49 PORT (
50 50 sample : IN Samples(7 DOWNTO 0);
51 51 sample_val : IN STD_LOGIC;
52 52 --
53 53 clk : IN STD_LOGIC;
54 54 rstn : IN STD_LOGIC;
55 55 --
56 56 data_shaping_SP0 : IN STD_LOGIC;
57 57 data_shaping_SP1 : IN STD_LOGIC;
58 58 data_shaping_R0 : IN STD_LOGIC;
59 59 data_shaping_R1 : IN STD_LOGIC;
60 60 data_shaping_R2 : IN STD_LOGIC;
61 61 --
62 62 sample_f0_val : OUT STD_LOGIC;
63 63 sample_f1_val : OUT STD_LOGIC;
64 64 sample_f2_val : OUT STD_LOGIC;
65 65 sample_f3_val : OUT STD_LOGIC;
66 66 --
67 67 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 68 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 69 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 70 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
71 71 );
72 72 END lpp_lfr_filter;
73 73
74 74 ARCHITECTURE tb OF lpp_lfr_filter IS
75 75
76 76 COMPONENT Downsampling
77 77 GENERIC (
78 78 ChanelCount : INTEGER;
79 79 SampleSize : INTEGER;
80 80 DivideParam : INTEGER);
81 81 PORT (
82 82 clk : IN STD_LOGIC;
83 83 rstn : IN STD_LOGIC;
84 84 sample_in_val : IN STD_LOGIC;
85 85 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
86 86 sample_out_val : OUT STD_LOGIC;
87 87 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
88 88 END COMPONENT;
89 89
90 90 -----------------------------------------------------------------------------
91 91 CONSTANT ChanelCount : INTEGER := 8;
92 92
93 93 -----------------------------------------------------------------------------
94 94 SIGNAL sample_val_delay : STD_LOGIC;
95 95 -----------------------------------------------------------------------------
96 96 CONSTANT Coef_SZ : INTEGER := 9;
97 97 CONSTANT CoefCntPerCel : INTEGER := 6;
98 98 CONSTANT CoefPerCel : INTEGER := 5;
99 99 CONSTANT Cels_count : INTEGER := 5;
100 100
101 101 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
102 102 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
103 103 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
104 104 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
105 105 --
106 106 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
107 107 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
108 108 -----------------------------------------------------------------------------
109 109 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
110 110 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
111 111 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
112 112 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
113 113 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
114 114 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
115 115 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
116 116 -----------------------------------------------------------------------------
117 117 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
118 118 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
119 119 -----------------------------------------------------------------------------
120 120 -- SIGNAL sample_f0_val : STD_LOGIC;
121 121 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
122 122 SIGNAL sample_f0_s : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
123 123 --
124 124 -- SIGNAL sample_f1_val : STD_LOGIC;
125 125 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
126 126 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
127 127 --
128 128 -- SIGNAL sample_f2_val : STD_LOGIC;
129 SIGNAL sample_f2 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
130 SIGNAL sample_f3 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
129 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
130 SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
131 SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
132 SIGNAL sample_f2_cic_val : STD_LOGIC;
133
134 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
135 SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
136 SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
137 SIGNAL sample_f3_cic_val : STD_LOGIC;
131 138
132 139 -----------------------------------------------------------------------------
133 140 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
134 141 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
135 142 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
136 143 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
137 144 -----------------------------------------------------------------------------
138 145
139 146 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
140 147 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
141 148 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
142 149 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
143 150
144 151 SIGNAL sample_f0_val_s : STD_LOGIC;
145 152 SIGNAL sample_f1_val_s : STD_LOGIC;
146 153 BEGIN
147 154
148 155 -----------------------------------------------------------------------------
149 156 PROCESS (clk, rstn)
150 157 BEGIN -- PROCESS
151 158 IF rstn = '0' THEN -- asynchronous reset (active low)
152 159 sample_val_delay <= '0';
153 160 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
154 161 sample_val_delay <= sample_val;
155 162 END IF;
156 163 END PROCESS;
157 164
158 165 -----------------------------------------------------------------------------
159 166 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
160 167 SampleLoop : FOR j IN 0 TO 15 GENERATE
161 168 sample_filter_in(i, j) <= sample(i)(j);
162 169 END GENERATE;
163 170
164 171 sample_filter_in(i, 16) <= sample(i)(15);
165 172 sample_filter_in(i, 17) <= sample(i)(15);
166 173 END GENERATE;
167 174
168 175 coefs_v2 <= CoefsInitValCst_v2;
169 176
170 177 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
171 178 GENERIC MAP (
172 179 tech => 0,
173 180 Mem_use => Mem_use, -- use_RAM
174 181 Sample_SZ => 18,
175 182 Coef_SZ => Coef_SZ,
176 183 Coef_Nb => 25,
177 184 Coef_sel_SZ => 5,
178 185 Cels_count => Cels_count,
179 186 ChanelsCount => ChanelCount)
180 187 PORT MAP (
181 188 rstn => rstn,
182 189 clk => clk,
183 190 virg_pos => 7,
184 191 coefs => coefs_v2,
185 192 sample_in_val => sample_val_delay,
186 193 sample_in => sample_filter_in,
187 194 sample_out_val => sample_filter_v2_out_val,
188 195 sample_out => sample_filter_v2_out);
189 196
190 197 -----------------------------------------------------------------------------
191 198 -- DATA_SHAPING
192 199 -----------------------------------------------------------------------------
193 200 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
194 201 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
195 202 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
196 203 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
197 204 END GENERATE all_data_shaping_in_loop;
198 205
199 206 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
200 207 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
201 208
202 209 PROCESS (clk, rstn)
203 210 BEGIN -- PROCESS
204 211 IF rstn = '0' THEN -- asynchronous reset (active low)
205 212 sample_data_shaping_out_val <= '0';
206 213 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
207 214 sample_data_shaping_out_val <= sample_filter_v2_out_val;
208 215 END IF;
209 216 END PROCESS;
210 217
211 218 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
212 219 PROCESS (clk, rstn)
213 220 BEGIN
214 221 IF rstn = '0' THEN
215 222 sample_data_shaping_out(0, j) <= '0';
216 223 sample_data_shaping_out(1, j) <= '0';
217 224 sample_data_shaping_out(2, j) <= '0';
218 225 sample_data_shaping_out(3, j) <= '0';
219 226 sample_data_shaping_out(4, j) <= '0';
220 227 sample_data_shaping_out(5, j) <= '0';
221 228 sample_data_shaping_out(6, j) <= '0';
222 229 sample_data_shaping_out(7, j) <= '0';
223 230 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
224 231 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
225 232 IF data_shaping_SP0 = '1' THEN
226 233 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
227 234 ELSE
228 235 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
229 236 END IF;
230 237 IF data_shaping_SP1 = '1' THEN
231 238 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
232 239 ELSE
233 240 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
234 241 END IF;
235 242 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
236 243 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
237 244 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
238 245 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
239 246 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
240 247 END IF;
241 248 END PROCESS;
242 249 END GENERATE;
243 250
244 251 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
245 252 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
246 253 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
247 254 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
248 255 END GENERATE;
249 256 END GENERATE;
250 257 -----------------------------------------------------------------------------
251 258 -- F0 -- @24.576 kHz
252 259 -----------------------------------------------------------------------------
253 260 Downsampling_f0 : Downsampling
254 261 GENERIC MAP (
255 262 ChanelCount => 8,
256 263 SampleSize => 16,
257 264 DivideParam => 4)
258 265 PORT MAP (
259 266 clk => clk,
260 267 rstn => rstn,
261 268 sample_in_val => sample_filter_v2_out_val_s,
262 269 sample_in => sample_filter_v2_out_s,
263 270 sample_out_val => sample_f0_val_s,
264 271 sample_out => sample_f0);
265 272
266 273 sample_f0_val <= sample_f0_val_s;
267 274
268 275 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
269 276 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
270 277 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
271 278 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
272 279 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
273 280 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
274 281 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
275 282 END GENERATE all_bit_sample_f0;
276 283
277 284 --sample_f0_wen <= NOT(sample_f0_val) &
278 285 -- NOT(sample_f0_val) &
279 286 -- NOT(sample_f0_val) &
280 287 -- NOT(sample_f0_val) &
281 288 -- NOT(sample_f0_val) &
282 289 -- NOT(sample_f0_val);
283 290
284 291 -----------------------------------------------------------------------------
285 292 -- F1 -- @4096 Hz
286 293 -----------------------------------------------------------------------------
287 294 Downsampling_f1 : Downsampling
288 295 GENERIC MAP (
289 296 ChanelCount => 8,
290 297 SampleSize => 16,
291 298 DivideParam => 6)
292 299 PORT MAP (
293 300 clk => clk,
294 301 rstn => rstn,
295 302 sample_in_val => sample_f0_val_s ,
296 303 sample_in => sample_f0,
297 304 sample_out_val => sample_f1_val_s,
298 305 sample_out => sample_f1);
299 306
300 307 sample_f1_val <= sample_f1_val_s;
301 308
302 309 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
303 310 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
304 311 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
305 312 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
306 313 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
307 314 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
308 315 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
309 316 END GENERATE all_bit_sample_f1;
310 317
311 318 --sample_f1_wen <= NOT(sample_f1_val) &
312 319 -- NOT(sample_f1_val) &
313 320 -- NOT(sample_f1_val) &
314 321 -- NOT(sample_f1_val) &
315 322 -- NOT(sample_f1_val) &
316 323 -- NOT(sample_f1_val);
317 324
318 325 -----------------------------------------------------------------------------
319 326 -- F2 -- @256 Hz
320 327 -- F3 -- @16 Hz
321 328 -----------------------------------------------------------------------------
322 329 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
323 330 sample_f0_s(0, I) <= sample_f0(0, I); -- V
324 331 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
325 332 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
326 333 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
327 334 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
328 335 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
329 336 END GENERATE all_bit_sample_f0_s;
330 337
331 338
332 339 cic_lfr_1: cic_lfr
333 340 GENERIC MAP (
334 341 tech => 0,
335 342 use_RAM_nCEL => Mem_use)
336 343 PORT MAP (
337 344 clk => clk,
338 345 rstn => rstn,
339 346 run => '1',
340 347
341 348 data_in => sample_f0_s,
342 349 data_in_valid => sample_f0_val_s,
343 350
344 data_out_16 => sample_f2,
345 data_out_16_valid => sample_f2_val,
351 data_out_16 => sample_f2_cic,
352 data_out_16_valid => sample_f2_cic_val,
346 353
347 data_out_256 => sample_f3,
348 data_out_256_valid => sample_f3_val);
354 data_out_256 => sample_f3_cic,
355 data_out_256_valid => sample_f3_cic_val);
356
357 -----------------------------------------------------------------------------
358
359 all_bit_sample_f2_cic : FOR I IN 15 DOWNTO 0 GENERATE
360 all_channel_sample_f2_cic : FOR J IN 5 DOWNTO 0 GENERATE
361 sample_f2_cic_s(J,I) <= sample_f2_cic(J,I);
362 END GENERATE all_channel_sample_f2_cic;
363 END GENERATE all_bit_sample_f2_cic;
364
365 Downsampling_f2 : Downsampling
366 GENERIC MAP (
367 ChanelCount => 6,
368 SampleSize => 16,
369 DivideParam => 6)
370 PORT MAP (
371 clk => clk,
372 rstn => rstn,
373 sample_in_val => sample_f2_cic_val ,
374 sample_in => sample_f2_cic_s,
375 sample_out_val => sample_f2_val,
376 sample_out => sample_f2);
349 377
350 378 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
351 sample_f2_wdata_s(I) <= sample_f2(0, I);
352 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
353 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
354 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
355 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
356 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
379 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
380 sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
381 END GENERATE all_channel_sample_f2;
357 382 END GENERATE all_bit_sample_f2;
358
383
384 -----------------------------------------------------------------------------
385
359 386 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
360 sample_f3_wdata_s(I) <= sample_f3(0, I);
361 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
362 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
363 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
364 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
365 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
387 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
388 sample_f3_cic_s(J,I) <= sample_f3_cic(J,I);
389 END GENERATE all_channel_sample_f3;
366 390 END GENERATE all_bit_sample_f3;
391
392 Downsampling_f3 : Downsampling
393 GENERIC MAP (
394 ChanelCount => 6,
395 SampleSize => 16,
396 DivideParam => 6)
397 PORT MAP (
398 clk => clk,
399 rstn => rstn,
400 sample_in_val => sample_f3_cic_val ,
401 sample_in => sample_f3_cic_s,
402 sample_out_val => sample_f3_val,
403 sample_out => sample_f3);
404
405 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
406 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
407 sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
408 END GENERATE all_channel_sample_f3;
409 END GENERATE all_bit_sample_f3;
367 410
368 411 -----------------------------------------------------------------------------
369 412 --
370 413 -----------------------------------------------------------------------------
371 414 sample_f0_wdata <= sample_f0_wdata_s;
372 415 sample_f1_wdata <= sample_f1_wdata_s;
373 416 sample_f2_wdata <= sample_f2_wdata_s;
374 417 sample_f3_wdata <= sample_f3_wdata_s;
375 418
376 419 END tb;
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