HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r535:27c141696b35

(LFR-EM) WFP_MS_1.1.61...

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r535:27c141696b35 (LFR-EM) WFP_MS_1-1-61 JC

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designs/LFR-em-WFP_MS/LFR-em.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY LFR_em IS
               PORT (
                 clk100MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 -- TAG --------------------------------------------------------------------
                 TAG1           : IN    STD_ULOGIC;  -- DSU rx data
                 TAG3           : OUT   STD_ULOGIC;  -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 TAG2           : IN    STD_ULOGIC;  -- UART1 rx data
                 TAG4           : OUT   STD_ULOGIC;  -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address        : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data           : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0      : OUT   STD_LOGIC;
                 nSRAM_BE1      : OUT   STD_LOGIC;
                 nSRAM_BE2      : OUT   STD_LOGIC;
                 nSRAM_BE3      : OUT   STD_LOGIC;
                 nSRAM_WE       : OUT   STD_LOGIC;
                 nSRAM_CE       : OUT   STD_LOGIC;
                 nSRAM_OE       : OUT   STD_LOGIC;
                 -- SPW --------------------------------------------------------------------
                 spw1_din       : IN    STD_LOGIC;
                 spw1_sin       : IN    STD_LOGIC;
                 spw1_dout      : OUT   STD_LOGIC;
                 spw1_sout      : OUT   STD_LOGIC;
                 spw2_din       : IN    STD_LOGIC;
                 spw2_sin       : IN    STD_LOGIC;
                 spw2_dout      : OUT   STD_LOGIC;
                 spw2_sout      : OUT   STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT   STD_LOGIC;
                 ADC_OEB_bar_CH : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT   STD_LOGIC;
                 ADC_data       : IN    STD_LOGIC_VECTOR(13 DOWNTO 0);
                 -- DAC --------------------------------------------------------------------
                 DAC_SDO    : OUT STD_LOGIC;
                 DAC_SCK    : OUT STD_LOGIC;
                 DAC_SYNC   : OUT STD_LOGIC;
                 DAC_CAL_EN : OUT STD_LOGIC;
                 -- HK ---------------------------------------------------------------------
                 HK_smpclk      : OUT   STD_LOGIC;
                 ADC_OEB_bar_HK : OUT   STD_LOGIC;
                 HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 TAG8           : OUT   STD_LOGIC;
                 led            : OUT   STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
             END LFR_em;
             ARCHITECTURE beh OF LFR_em IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(8 DOWNTO 0);
               SIGNAL sample_s    : Samples(8 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL  ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn : STD_LOGIC;
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
               PROCESS(clk100MHz)
               BEGIN
                 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
                   clk_50_s <= NOT clk_50_s;
                 END IF;
               END PROCESS;
               PROCESS(clk_50_s)
               BEGIN
                 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   led(0) <= '0';
                   led(1) <= '0';
                   led(2) <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   led(0) <= '0';
                   led(1) <= '1';
                   led(2) <= '1';
                 END IF;
               END PROCESS;
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   IS_RADHARD      => 0,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => 0)
                 PORT MAP (
                   clk    => clk_25,
                   reset  => rstn,
                   errorn => OPEN,
                   ahbrxd => TAG1,
                   ahbtxd => TAG3,
                   urxd1  => TAG2,
                   utxd1  => TAG4,
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => nSRAM_BE0,
                   nSRAM_BE1 => nSRAM_BE1,
                   nSRAM_BE2 => nSRAM_BE2,
                   nSRAM_BE3 => nSRAM_BE3,
                   nSRAM_WE  => nSRAM_WE,
                   nSRAM_CE  => nSRAM_CE_s,
                   nSRAM_OE  => nSRAM_OE,
                   nSRAM_READY => '0',
                   SRAM_MBE    => OPEN,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               nSRAM_CE <= nSRAM_CE_s(0);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   tech             => apa3e,
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz      => clk_25,
                   clk24_576MHz  => clk_24,          -- 49.152MHz/2
                   resetn        => rstn,
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                   HK_sample     => sample_s(8),
                   HK_val        => sample_val,
                   HK_sel        => HK_SEL,
                   DAC_SDO           => DAC_SDO,
                   DAC_SCK            => DAC_SCK,
                   DAC_SYNC          => DAC_SYNC,
                   DAC_CAL_EN        => DAC_CAL_EN,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
             --  SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"01013C")  -- aa.bb.cc version
+                  top_lfr_version        => X"01013D")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw,
                   debug_vector    => OPEN,
                   debug_vector_ms => OPEN);     --,
               --observation_vector_0 => OPEN,
               --observation_vector_1 => OPEN,
               --observation_reg => observation_reg);
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I) & '0' & '0';
               END GENERATE all_sample;
               sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
                 GENERIC MAP (
                   ChanelCount     => 9,
                   ncycle_cnv_high => 13,
                   ncycle_cnv      => 25,
                   FILTER_ENABLED  => 16#FF#)
                 PORT MAP (
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
                   rstn       => rstn,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH_s,
                   sample     => sample,
                   sample_val => sample_val);
               ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
               ADC_smpclk <= ADC_smpclk_s;
               HK_smpclk  <= ADC_smpclk_s;
               TAG8 <= ADC_smpclk_s;
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
             END beh;

lib/lpp/lfr_management/apb_lfr_management.vhd +2 -2

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    11:17:05 07/02/2012
             -- Design Name:
             -- Module Name:    apb_lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY lpp;
             USE lpp.apb_devices_list.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
             USE lpp.lpp_cna.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY apb_lfr_management IS
               GENERIC(
                 tech             : INTEGER := 0;
                 pindex           : INTEGER := 0;        --! APB slave index
                 paddr            : INTEGER := 0;        --! ADDR field of the APB BAR
                 pmask            : INTEGER := 16#fff#;  --! MASK field of the APB BAR
                 FIRST_DIVISION   : INTEGER := 374;
                 NB_SECOND_DESYNC : INTEGER := 60
                 );
               PORT (
                 clk25MHz     : IN STD_LOGIC;        --! Clock
                 clk24_576MHz : IN STD_LOGIC;        --! secondary clock
                 resetn       : IN STD_LOGIC;        --! Reset
                 grspw_tick : IN STD_LOGIC;  --! grspw signal asserted when a valid time-code is received
                 apbi          : IN  apb_slv_in_type;   --! APB slave input signals
                 apbo          : OUT apb_slv_out_type;  --! APB slave output signals
                 ---------------------------------------------------------------------------
                 HK_sample     : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                 HK_val        : IN  STD_LOGIC;
                 HK_sel        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 DAC_SDO       : OUT STD_LOGIC;
                 DAC_SCK       : OUT STD_LOGIC;
                 DAC_SYNC      : OUT STD_LOGIC;
                 DAC_CAL_EN    : OUT STD_LOGIC;
                 ---------------------------------------------------------------------------
                 coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --! coarse time
                 fine_time     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);  --! fine TIME
                 ---------------------------------------------------------------------------
                 LFR_soft_rstn : OUT STD_LOGIC
                 );
             END apb_lfr_management;
             ARCHITECTURE Behavioral OF apb_lfr_management IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
 => apb_iobar(paddr, pmask)
                 );
               TYPE apb_lfr_time_management_Reg IS RECORD
                 ctrl             : STD_LOGIC;
                 soft_reset       : STD_LOGIC;
                 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
                 coarse_time      : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 fine_time        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 LFR_soft_reset   : STD_LOGIC;
                 HK_temp_0        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 HK_temp_1        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 HK_temp_2        : STD_LOGIC_VECTOR(15 DOWNTO 0);
               END RECORD;
               SIGNAL r : apb_lfr_time_management_Reg;
               SIGNAL Rdata               : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL force_tick          : STD_LOGIC;
               SIGNAL previous_force_tick : STD_LOGIC;
               SIGNAL soft_tick           : STD_LOGIC;
               SIGNAL coarsetime_reg_updated : STD_LOGIC;
               SIGNAL coarsetime_reg         : STD_LOGIC_VECTOR(30 DOWNTO 0);
               --SIGNAL coarse_time_new    : STD_LOGIC;
               SIGNAL coarse_time_new_49 : STD_LOGIC;
               SIGNAL coarse_time_49     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL coarse_time_s      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               --SIGNAL fine_time_new      : STD_LOGIC;
               --SIGNAL fine_time_new_temp : STD_LOGIC;
               SIGNAL fine_time_new_49 : STD_LOGIC;
               SIGNAL fine_time_49     : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fine_time_s      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL tick             : STD_LOGIC;
               SIGNAL new_timecode     : STD_LOGIC;
               SIGNAL new_coarsetime   : STD_LOGIC;
               SIGNAL time_new_49 : STD_LOGIC;
               SIGNAL time_new    : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL force_reset          : STD_LOGIC;
               SIGNAL previous_force_reset : STD_LOGIC;
               SIGNAL soft_reset           : STD_LOGIC;
               SIGNAL soft_reset_sync      : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL HK_sel_s             : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL previous_fine_time_bit : STD_LOGIC;
               SIGNAL rstn_LFR_TM : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- DAC
               -----------------------------------------------------------------------------
               CONSTANT PRESZ         : INTEGER := 8;
               CONSTANT CPTSZ         : INTEGER := 16;
               CONSTANT datawidth     : INTEGER := 18;
               CONSTANT dacresolution : INTEGER := 12;
               CONSTANT abits         : INTEGER := 8;
               SIGNAL pre           : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
               SIGNAL N             : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
               SIGNAL Reload        : STD_LOGIC;
               SIGNAL DATA_IN       : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
               SIGNAL WEN           : STD_LOGIC;
               SIGNAL LOAD_ADDRESSN : STD_LOGIC;
               SIGNAL ADDRESS_IN    : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
               SIGNAL ADDRESS_OUT   : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
               SIGNAL INTERLEAVED   : STD_LOGIC;
               SIGNAL DAC_CFG       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL DAC_CAL_EN_s  : STD_LOGIC;
               SIGNAL HK_debug_mode : STD_LOGIC;
               SIGNAL HK_sel_debug  : STD_LOGIC_VECTOR(1 DOWNTO 0);
             BEGIN
               LFR_soft_rstn <= NOT r.LFR_soft_reset;
               PROCESS(resetn, clk25MHz)
                 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
               BEGIN
                 IF resetn = '0' THEN
                   Rdata              <= (OTHERS => '0');
                   r.coarse_time_load <= (OTHERS => '0');
                   r.soft_reset       <= '0';
                   r.ctrl             <= '0';
                   r.LFR_soft_reset   <= '1';
                   force_tick          <= '0';
                   previous_force_tick <= '0';
                   soft_tick           <= '0';
                   coarsetime_reg_updated <= '0';
                   --DAC
                   pre                    <= (OTHERS => '1');
                   N                      <= (OTHERS => '1');
                   Reload                 <= '1';
                   DATA_IN                <= (OTHERS => '0');
                   WEN                    <= '1';
                   LOAD_ADDRESSN          <= '1';
                   ADDRESS_IN             <= (OTHERS => '1');
                   INTERLEAVED            <= '0';
                   DAC_CFG                <= (OTHERS => '0');
                   --
                   DAC_CAL_EN_s           <= '0';
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
                   coarsetime_reg_updated <= '0';
                   force_tick          <= r.ctrl;
                   previous_force_tick <= force_tick;
                   IF (previous_force_tick = '0') AND (force_tick = '1') THEN
                     soft_tick <= '1';
                   ELSE
                     soft_tick <= '0';
                   END IF;
                   force_reset          <= r.soft_reset;
                   previous_force_reset <= force_reset;
                   IF (previous_force_reset = '0') AND (force_reset = '1') THEN
                     soft_reset <= '1';
                   ELSE
                     soft_reset <= '0';
                   END IF;
                   paddr             := "000000";
                   paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
                   Rdata             <= (OTHERS => '0');
+                  LOAD_ADDRESSN <= '1';
+                  WEN           <= '1';
                   IF apbi.psel(pindex) = '1' THEN
                     --APB READ OP
                     CASE paddr(7 DOWNTO 2) IS
                       WHEN ADDR_LFR_MANAGMENT_CONTROL =>
                         Rdata(0)           <= r.ctrl;
                         Rdata(1)           <= r.soft_reset;
                         Rdata(2)           <= r.LFR_soft_reset;
                         Rdata(3)           <= HK_debug_mode;
                         Rdata(5 DOWNTO 4)  <= HK_sel_debug;
                         Rdata(31 DOWNTO 6) <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
                         Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
                       WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
                         Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
                       WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.fine_time(15 DOWNTO 0);
                       WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.HK_temp_0;
                       WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.HK_temp_1;
                       WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.HK_temp_2;
                       WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
                         Rdata(3 DOWNTO 0)  <= DAC_CFG;
                         Rdata(4)           <= Reload;
                         Rdata(5)           <= INTERLEAVED;
                         Rdata(6)           <= DAC_CAL_EN_s;
                         Rdata(31 DOWNTO 7) <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
                         Rdata(PRESZ-1 DOWNTO 0) <= pre;
                         Rdata(31 DOWNTO PRESZ)  <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_DAC_N =>
                         Rdata(CPTSZ-1 DOWNTO 0) <= N;
                         Rdata(31 DOWNTO CPTSZ)  <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
                         Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
                         Rdata(31 DOWNTO abits)  <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
                         Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
                         Rdata(31 DOWNTO datawidth)  <= (OTHERS => '0');
                       WHEN OTHERS =>
                         Rdata(31 DOWNTO 0) <= (OTHERS => '0');
                     END CASE;
                     --APB Write OP
                     IF (apbi.pwrite AND apbi.penable) = '1' THEN
                       CASE paddr(7 DOWNTO 2) IS
                         WHEN ADDR_LFR_MANAGMENT_CONTROL =>
                           r.ctrl           <= apbi.pwdata(0);
                           r.soft_reset     <= apbi.pwdata(1);
                           r.LFR_soft_reset <= apbi.pwdata(2);
                           HK_debug_mode    <= apbi.pwdata(3);
                           HK_sel_debug     <= apbi.pwdata(5 DOWNTO 4);
                         WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
                           r.coarse_time_load     <= apbi.pwdata(30 DOWNTO 0);
                           coarsetime_reg_updated <= '1';
                         WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
                           DAC_CFG      <= apbi.pwdata(3 DOWNTO 0);
                           Reload       <= apbi.pwdata(4);
                           INTERLEAVED  <= apbi.pwdata(5);
                           DAC_CAL_EN_s <= apbi.pwdata(6);
                         WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
                           pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
                         WHEN ADDR_LFR_MANAGMENT_DAC_N =>
                           N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
                         WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
                           ADDRESS_IN    <= apbi.pwdata(abits-1 DOWNTO 0);
                           LOAD_ADDRESSN <= '0';
                         WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
                           DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
                           WEN     <= '0';
                         WHEN OTHERS =>
                           NULL;
                       END CASE;
                     ELSE
-                      LOAD_ADDRESSN <= '1';
-                      WEN           <= '1';
                       IF r.ctrl = '1' THEN
                         r.ctrl <= '0';
                       END IF;
                       IF r.soft_reset = '1' THEN
                         r.soft_reset <= '0';
                       END IF;
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               apbo.pirq    <= (OTHERS => '0');
               apbo.prdata  <= Rdata;
               apbo.pconfig <= pconfig;
               apbo.pindex  <= pindex;
               -----------------------------------------------------------------------------
               -- IN
               coarse_time    <= r.coarse_time;
               fine_time      <= r.fine_time;
               coarsetime_reg <= r.coarse_time_load;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- OUT
               r.coarse_time <= coarse_time_s;
               r.fine_time   <= fine_time_s;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               tick <= grspw_tick OR soft_tick;
               SYNC_VALID_BIT_1 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => tick,
                   sout    => new_timecode);
               SYNC_VALID_BIT_2 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => coarsetime_reg_updated,
                   sout    => new_coarsetime);
               SYNC_VALID_BIT_3 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => soft_reset,
                   sout    => soft_reset_sync);
               -----------------------------------------------------------------------------
               --SYNC_FF_1 : SYNC_FF
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk    => clk25MHz,
               --    rstn   => resetn,
               --    A      => fine_time_new_49,
               --    A_sync => fine_time_new_temp);
               --lpp_front_detection_1 : lpp_front_detection
               --  PORT MAP (
               --    clk  => clk25MHz,
               --    rstn => resetn,
               --    sin  => fine_time_new_temp,
               --    sout => fine_time_new);
               --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk_in  => clk24_576MHz,
               --    clk_out => clk25MHz,
               --    rstn    => resetn,
               --    sin     => coarse_time_new_49,
               --    sout    => coarse_time_new);
               time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
               SYNC_VALID_BIT_4 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk24_576MHz,
                   clk_out => clk25MHz,
                   rstn    => resetn,
                   sin     => time_new_49,
                   sout    => time_new);
               PROCESS (clk25MHz, resetn)
               BEGIN  -- PROCESS
                 IF resetn = '0' THEN                -- asynchronous reset (active low)
                   fine_time_s   <= (OTHERS => '0');
                   coarse_time_s <= (OTHERS => '0');
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
                   IF time_new = '1' THEN
                     fine_time_s   <= fine_time_49;
                     coarse_time_s <= coarse_time_49;
                   END IF;
                 END IF;
               END PROCESS;
               rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
                              '0' WHEN soft_reset_sync = '1' ELSE
                              '1';
               -----------------------------------------------------------------------------
               -- LFR_TIME_MANAGMENT
               -----------------------------------------------------------------------------
               lfr_time_management_1 : lfr_time_management
                 GENERIC MAP (
                   FIRST_DIVISION   => FIRST_DIVISION,
                   NB_SECOND_DESYNC => NB_SECOND_DESYNC)
                 PORT MAP (
                   clk  => clk24_576MHz,
                   rstn => rstn_LFR_TM,
                   tick           => new_timecode,
                   new_coarsetime => new_coarsetime,
                   coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
                   fine_time       => fine_time_49,
                   fine_time_new   => fine_time_new_49,
                   coarse_time     => coarse_time_49,
                   coarse_time_new => coarse_time_new_49);
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               PROCESS (clk25MHz, resetn)
                 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14;  -- freq = 2^(16-BIT)
                                                                 -- for each HK, the update frequency is freq/3
                                                                 --
                                                                 -- for 14, the update frequency is
                                                                 -- 4Hz and update for each
                                                                 -- HK is 1.33Hz
               BEGIN  -- PROCESS
                 IF resetn = '0' THEN                -- asynchronous reset (active low)
                   r.HK_temp_0 <= (OTHERS => '0');
                   r.HK_temp_1 <= (OTHERS => '0');
                   r.HK_temp_2 <= (OTHERS => '0');
                   HK_sel_s <= "00";
                   previous_fine_time_bit <= '0';
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
                   IF HK_val = '1' THEN
                     IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
                       previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
                       CASE HK_sel_s IS
                         WHEN "00" =>
                           r.HK_temp_0 <= HK_sample;
                           IF HK_debug_mode = '1' THEN
                             HK_sel_s <= HK_sel_debug;
                           ELSE
                             HK_sel_s <= "01";
                           END IF;
                         WHEN "01" =>
                           r.HK_temp_1 <= HK_sample;
                           IF HK_debug_mode = '1' THEN
                             HK_sel_s <= HK_sel_debug;
                           ELSE
                             HK_sel_s <= "10";
                           END IF;
                         WHEN "10" =>
                           r.HK_temp_2 <= HK_sample;
                           IF HK_debug_mode = '1' THEN
                             HK_sel_s <= HK_sel_debug;
                           ELSE
                             HK_sel_s <= "00";
                           END IF;
                         WHEN OTHERS => NULL;
                       END CASE;
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               HK_sel <= HK_sel_s;
               -----------------------------------------------------------------------------
               -- DAC
               -----------------------------------------------------------------------------
               cal : lfr_cal_driver
                 GENERIC MAP(
                   tech      => tech,
                   PRESZ     => PRESZ,
                   CPTSZ     => CPTSZ,
                   datawidth => datawidth,
                   abits     => abits
                   )
                 PORT MAP(
                   clk  => clk25MHz,
                   rstn => resetn,
                   pre           => pre,
                   N             => N,
                   Reload        => Reload,
                   DATA_IN       => DATA_IN,
                   WEN           => WEN,
                   LOAD_ADDRESSN => LOAD_ADDRESSN,
                   ADDRESS_IN    => ADDRESS_IN,
                   ADDRESS_OUT   => ADDRESS_OUT,
                   INTERLEAVED   => INTERLEAVED,
                   DAC_CFG       => DAC_CFG,
                   SYNC   => DAC_SYNC,
                   DOUT   => DAC_SDO,
                   SCLK   => DAC_SCK,
                   SMPCLK => OPEN                    --DAC_SMPCLK
                   );
               DAC_CAL_EN <= DAC_CAL_EN_s;
             END Behavioral;

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