HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r289:22f31659a8c7

(MINI_LFR) WaveFormPicker.0.0.0A

pellion -

r289:22f31659a8c7 WaveFormPicker-0-0-0A (MINI-LFR) JC

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r289:22f31659a8c7

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designs/LFR_simu/tb_waveform.do +27 -21

             onerror {resume}
             quietly WaveActivateNextPane {} 0
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid
-            add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd
+            add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_1/mem_array_t
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_t
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run
+            add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send
+            add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin
-            add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst
+            add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout
-            add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin
+            add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain
-            add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout
-            add wave -noupdate -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain
             add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data
             add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant
-            add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout
+            add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout
+            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0
+            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_0
+            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1
+            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1
+            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2
+            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2
+            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3
+            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_3
             TreeUpdate [SetDefaultTree]
-            WaveRestoreCursors {{Cursor 1} {12032365000 ps} 0}
+            WaveRestoreCursors {{Cursor 1} {12913873180 ps} 0}
             configure wave -namecolwidth 540
             configure wave -valuecolwidth 316
             configure wave -justifyvalue left
             configure wave -signalnamewidth 0
             configure wave -snapdistance 10
             configure wave -datasetprefix 0
             configure wave -rowmargin 4
             configure wave -childrowmargin 2
             configure wave -gridoffset 0
             configure wave -gridperiod 1
             configure wave -griddelta 40
             configure wave -timeline 0
             configure wave -timelineunits ns
             update
-            WaveRestoreZoom {0 ps} {162198702750 ps}
+            WaveRestoreZoom {0 ps} {63240778126 ps}

designs/LFR_simu/tb_waveform.vhd +8 -8

             ------------------------------------------------------------------------------
             --  LEON3 Demonstration design test bench
             --  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
             ------------------------------------------------------------------------------
             --  This file is a part of the GRLIB VHDL IP LIBRARY
             --  Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
             --
             -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
             -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
             -- IN ADVANCE IN WRITING.
             ------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             --LIBRARY std;
             --USE std.textio.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.libdcom.ALL;
             USE gaisler.sim.ALL;
             USE gaisler.jtagtst.ALL;
             USE gaisler.misc.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             --LIBRARY micron;
             --USE micron.components.ALL;
             LIBRARY lpp;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.testbench_package.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.CY7C1061DV33_pkg.ALL;
             ENTITY testbench IS
             END;
             ARCHITECTURE behav OF testbench IS
               -- REG ADDRESS
               CONSTANT INDEX_WAVEFORM_PICKER                  : INTEGER                       := 15;
               CONSTANT ADDR_WAVEFORM_PICKER                   : INTEGER                       := 15;
               CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING       : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
               CONSTANT ADDR_WAVEFORM_PICKER_CONTROL           : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
               CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0        : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
               CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1        : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
               CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2        : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
               CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3        : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
               CONSTANT ADDR_WAVEFORM_PICKER_STATUS            : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
               CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT     : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
               CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0          : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
               CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2        : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
               CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1          : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
               CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2          : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
               CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
               CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT        : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
               CONSTANT ADDR_WAVEFORM_PICKER_START_DATE        : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
               CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
               -- RAM ADDRESS
               CONSTANT AHB_RAM_ADDR_0                         : INTEGER                       := 16#100#;
               CONSTANT AHB_RAM_ADDR_1                         : INTEGER                       := 16#200#;
               CONSTANT AHB_RAM_ADDR_2                         : INTEGER                       := 16#300#;
               CONSTANT AHB_RAM_ADDR_3                         : INTEGER                       := 16#400#;
               -- Common signal
               SIGNAL clk49_152MHz : STD_LOGIC := '0';
               SIGNAL clk25MHz     : STD_LOGIC := '0';
               SIGNAL rstn         : STD_LOGIC := '0';
               -- ADC interface
               SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);   -- OUT
               SIGNAL ADC_smpclk     : STD_LOGIC;                      -- OUT
               SIGNAL ADC_data       : STD_LOGIC_VECTOR(13 DOWNTO 0);  -- IN
               -- AD Converter RHF1401
               SIGNAL sample     : Samples14v(7 DOWNTO 0);
               SIGNAL sample_val : STD_LOGIC;
               -- AHB/APB SIGNAL
               SIGNAL apbi  : apb_slv_in_type;
               SIGNAL apbo  : apb_slv_out_vector := (OTHERS => apb_none);
               SIGNAL ahbsi : ahb_slv_in_type;
               SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
               SIGNAL ahbmi : ahb_mst_in_type;
               SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
               SIGNAL bias_fail_bw : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- LPP_WAVEFORM
               -----------------------------------------------------------------------------
               CONSTANT data_size               : INTEGER := 96;
               CONSTANT nb_burst_available_size : INTEGER := 50;
               CONSTANT nb_snapshot_param_size  : INTEGER := 2;
               CONSTANT delta_vector_size       : INTEGER := 2;
               CONSTANT delta_vector_size_f0_2  : INTEGER := 2;
               SIGNAL reg_run                      : STD_LOGIC;
               SIGNAL reg_start_date               : STD_LOGIC_VECTOR(30 DOWNTO 0);
               SIGNAL reg_delta_snapshot           : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL reg_delta_f0                 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL reg_delta_f0_2               : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
               SIGNAL reg_delta_f1                 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL reg_delta_f2                 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL enable_f0                    : STD_LOGIC;
               SIGNAL enable_f1                    : STD_LOGIC;
               SIGNAL enable_f2                    : STD_LOGIC;
               SIGNAL enable_f3                    : STD_LOGIC;
               SIGNAL burst_f0                     : STD_LOGIC;
               SIGNAL burst_f1                     : STD_LOGIC;
               SIGNAL burst_f2                     : STD_LOGIC;
               SIGNAL nb_data_by_buffer            : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param            : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL status_full                  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_ack              : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_err              : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_new_err               : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL coarse_time                  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time                    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL addr_data_f0                 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_in_valid             : STD_LOGIC;
               SIGNAL data_f0_in                   : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL addr_data_f1                 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_in_valid             : STD_LOGIC;
               SIGNAL data_f1_in                   : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL addr_data_f2                 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_in_valid             : STD_LOGIC;
               SIGNAL data_f2_in                   : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL addr_data_f3                 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_in_valid             : STD_LOGIC;
               SIGNAL data_f3_in                   : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f0_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out_valid       : STD_LOGIC;
               SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f0_data_out_ack         : STD_LOGIC;
               SIGNAL data_f1_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out_valid       : STD_LOGIC;
               SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f1_data_out_ack         : STD_LOGIC;
               SIGNAL data_f2_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out_valid       : STD_LOGIC;
               SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f2_data_out_ack         : STD_LOGIC;
               SIGNAL data_f3_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out_valid       : STD_LOGIC;
               SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f3_data_out_ack         : STD_LOGIC;
               --MEM CTRLR
               SIGNAL memi       : memory_in_type;
               SIGNAL memo       : memory_out_type;
               SIGNAL wpo        : wprot_out_type;
               SIGNAL sdo        : sdram_out_type;
               SIGNAL address   : STD_LOGIC_VECTOR(19 DOWNTO 0);
               SIGNAL data      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL nSRAM_BE0 : STD_LOGIC;
               SIGNAL nSRAM_BE1 : STD_LOGIC;
               SIGNAL nSRAM_BE2 : STD_LOGIC;
               SIGNAL nSRAM_BE3 : STD_LOGIC;
               SIGNAL nSRAM_WE  : STD_LOGIC;
               SIGNAL nSRAM_CE  : STD_LOGIC;
               SIGNAL nSRAM_OE  : STD_LOGIC;
               CONSTANT padtech : INTEGER := inferred;
               SIGNAL not_ramsn_0 : STD_LOGIC;
             BEGIN
               -----------------------------------------------------------------------------
               clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps;  -- 49.152/2 MHz
               clk25MHz     <= NOT clk25MHz     AFTER 5 ns;      -- 100 MHz
               -----------------------------------------------------------------------------
               MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
                 TestModule_RHF1401_1 : TestModule_RHF1401
                   GENERIC MAP (
                     freq      => 24*(I+1),
                     amplitude => 8000/(I+1),
                     impulsion => 0)
                   PORT MAP (
                     ADC_smpclk  => ADC_smpclk,
                     ADC_OEB_bar => ADC_OEB_bar_CH(I),
                     ADC_data    => ADC_data);
               END GENERATE MODULE_RHF1401;
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
                 GENERIC MAP (
                   ChanelCount     => 8,
                   ncycle_cnv_high => 79,
                   ncycle_cnv      => 500)
                 PORT MAP (
                   cnv_clk    => clk49_152MHz,
                   cnv_rstn   => rstn,
                   cnv        => ADC_smpclk,
                   clk        => clk25MHz,
                   rstn       => rstn,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH,
                   sample     => sample,
                   sample_val => sample_val);
               -----------------------------------------------------------------------------
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_CEL,  -- use_RAM
                   nb_data_by_buffer_size => 32,
                   nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 32,
                   pindex                 => INDEX_WAVEFORM_PICKER,
                   paddr                  => ADDR_WAVEFORM_PICKER,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 0,
                   top_lfr_version        => X"00000001")
                 PORT MAP (
                   clk             => clk25MHz,
                   rstn            => rstn,
                   sample_B        => sample(2 DOWNTO 0),
                   sample_E        => sample(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi,
                   apbo            => apbo(15),
                   ahbi            => ahbmi,
                   ahbo            => ahbmo(0),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_bw);
               -----------------------------------------------------------------------------
               ---  AHB CONTROLLER  -------------------------------------------------
               ahb0 : ahbctrl                        -- AHB arbiter/multiplexer
                 GENERIC MAP (defmast => 0, split => 0,
                              rrobin  => 1, ioaddr => 16#FFF#,
                              ioen    => 0, nahbm => 1, nahbs => 1)
                 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
               ---  AHB RAM ----------------------------------------------------------
               --ahbram0 : ahbram
               --  GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
               --  PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
               --ahbram1 : ahbram
               --  GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
               --  PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
               --ahbram2 : ahbram
               --  GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
               --  PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
               --ahbram3 : ahbram
               --  GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
               --  PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
               -----------------------------------------------------------------------------
             ----------------------------------------------------------------------
             ---  Memory controllers  ---------------------------------------------
             ----------------------------------------------------------------------
               memctrlr : mctrl GENERIC MAP (
                 hindex  => 0,
                 pindex  => 0,
                 paddr   => 0,
                 srbanks => 1
                 )
                 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
               memi.brdyn  <= '1';
               memi.bexcn  <= '1';
               memi.writen <= '1';
               memi.wrn    <= "1111";
               memi.bwidth <= "10";
               bdr : FOR i IN 0 TO 3 GENERATE
                 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
                   PORT MAP (
                     data(31-i*8 DOWNTO 24-i*8),
                     memo.data(31-i*8 DOWNTO 24-i*8),
                     memo.bdrive(i),
                     memi.data(31-i*8 DOWNTO 24-i*8));
               END GENERATE;
               addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
                 PORT MAP (address, memo.address(21 DOWNTO 2));
               not_ramsn_0 <= NOT(memo.ramsn(0));
               rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
               oen_pad  : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
               nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
               nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
               nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
               nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
               nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
               async_1Mx16_0: CY7C1061DV33
                 GENERIC MAP (
                   ADDR_BITS         => 20,
                   DATA_BITS         => 16,
                   depth 	        => 1048576,
                   TimingInfo        => TRUE,
                   TimingChecks	=> '1')
                 PORT MAP (
                   CE1_b => '0',
                   CE2   => nSRAM_CE,
                   WE_b  => nSRAM_WE,
                   OE_b  => nSRAM_OE,
                   BHE_b => nSRAM_BE1,
                   BLE_b => nSRAM_BE0,
                   A     => address,
                   DQ    => data(15 DOWNTO 0));
               async_1Mx16_1: CY7C1061DV33
                 GENERIC MAP (
                   ADDR_BITS         => 20,
                   DATA_BITS         => 16,
                   depth 	        => 1048576,
                   TimingInfo        => TRUE,
                   TimingChecks	=> '1')
                 PORT MAP (
                   CE1_b => '0',
                   CE2   => nSRAM_CE,
                   WE_b  => nSRAM_WE,
                   OE_b  => nSRAM_OE,
                   BHE_b => nSRAM_BE3,
                   BLE_b => nSRAM_BE2,
                   A     => address,
                   DQ    => data(31 DOWNTO 16));
               -----------------------------------------------------------------------------
               WaveGen_Proc : PROCESS
               BEGIN
                 -- insert signal assignments here
                 WAIT UNTIL clk25MHz = '1';
                 rstn          <= '0';
                 apbi.psel(15) <= '0';
                 apbi.pwrite   <= '0';
                 apbi.penable  <= '0';
                 apbi.paddr    <= (OTHERS => '0');
                 apbi.pwdata   <= (OTHERS => '0');
                 fine_time     <= (OTHERS => '0');
                 coarse_time   <= (OTHERS => '0');
                 WAIT UNTIL clk25MHz = '1';
             --    ahbmi.HGRANT(2) <= '1';
             --    ahbmi.HREADY    <= '1';
             --    ahbmi.HRESP     <= HRESP_OKAY;
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 rstn <= '1';
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 ---------------------------------------------------------------------------
                 -- CONFIGURATION STEP
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
-                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40200000");
+                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
-                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40400000");
+                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
-                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40800000");
+                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
-                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000002");--"00000020"
+                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020"
-                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0     , X"00000002");--"00000019"
+                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0     , X"00000019");--"00000019"
-                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2   , X"00000001");--"00000007"
+                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2   , X"00000007");--"00000007"
-                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1     , X"00000020");--"00000019"
+                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1     , X"00000019");--"00000019"
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2     , X"00000001");--"00000001"
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
                 --
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
-                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000081");
+                APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 WAIT FOR 1 us;
                 coarse_time <= X"00000001";
                 ---------------------------------------------------------------------------
                 -- RUN STEP
                 WAIT FOR 200 ms;
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
                 WAIT FOR 10 us;
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
                 WAIT UNTIL clk25MHz = '1';
                 coarse_time <= X"00000010";
                 WAIT FOR 100 ms;
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
                 WAIT FOR 10 us;
                 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
                 WAIT FOR 200 ms;
                 REPORT "*** END simulation ***" SEVERITY failure;
                 WAIT;
               END PROCESS WaveGen_Proc;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- IRQ
               -----------------------------------------------------------------------------
               PROCESS (clk25MHz, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
             END;

lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd +10 -6

             --************************************************************************
             --**    MODEL   :       async_1Mx16.vhd                                    **
             --**    COMPANY :       Cypress Semiconductor                           **
             --**    REVISION:       1.0 Created new base model                                  **
             --************************************************************************
             -------------------------------------------------------------------------------JC\/
             --Library ieee,work;
             LIBRARY ieee;
             -------------------------------------------------------------------------------JC/\
             USE IEEE.Std_Logic_1164.ALL;
             USE IEEE.Std_Logic_unsigned.ALL;
             -------------------------------------------------------------------------------JC\/
             --use work.package_timing.all;
             --use work.package_utility.all;
             LIBRARY lpp;
             USE lpp.package_timing.ALL;
             USE lpp.package_utility.ALL;
             -------------------------------------------------------------------------------JC/\
             ------------------------
             -- Entity Description
             ------------------------
             ENTITY CY7C1061DV33 IS
               GENERIC
                 (ADDR_BITS : INTEGER := 20;
                  DATA_BITS : INTEGER := 16;
                  depth     : INTEGER := 1048576;
                  TimingInfo   : BOOLEAN   := true;
                  TimingChecks : STD_LOGIC := '1'
                  );
               PORT (
                 CE1_b : IN    STD_LOGIC;            -- Chip Enable CE1#
                 CE2   : IN    STD_LOGIC;            -- Chip Enable CE2
                 WE_b  : IN    STD_LOGIC;            -- Write Enable WE#
                 OE_b  : IN    STD_LOGIC;            -- Output Enable OE#
                 BHE_b : IN    STD_LOGIC;            -- Byte Enable High BHE#
                 BLE_b : IN    STD_LOGIC;            -- Byte Enable Low BLE#
                 A     : IN    STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0);  -- Address Inputs A
                 DQ    : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO;
                 );
             END CY7C1061DV33;
             -----------------------------
             -- End Entity Description
             -----------------------------
             -----------------------------
             -- Architecture Description
             -----------------------------
             ARCHITECTURE behave_arch OF CY7C1061DV33 IS
               TYPE mem_array_type IS ARRAY (depth-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
               SIGNAL write_enable : STD_LOGIC;
               SIGNAL read_enable  : STD_LOGIC;
               SIGNAL byte_enable  : STD_LOGIC;
               SIGNAL CE_b         : STD_LOGIC;
               SIGNAL data_skew : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
               SIGNAL address_internal, address_skew : STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0);
               CONSTANT tSD_dataskew : TIME := tSD - 1 ns;
               CONSTANT tskew        : TIME := 1 ns;
               -------------------------------------------------------------------------------JC\/
-              TYPE mem_array_type_t IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
+              TYPE mem_array_type_t IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
-              SIGNAL mem_array_t : mem_array_type_t;
+              SIGNAL mem_array_0 : mem_array_type_t;
+              SIGNAL mem_array_1 : mem_array_type_t;
+              SIGNAL mem_array_2 : mem_array_type_t;
+              SIGNAL mem_array_3 : mem_array_type_t;
               -------------------------------------------------------------------------------JC/\
             BEGIN
               CE_b         <= CE1_b OR NOT(CE2);
               byte_enable  <= NOT(BHE_b AND BLE_b);
               write_enable <= NOT(CE1_b) AND CE2 AND NOT(WE_b) AND NOT(BHE_b AND BLE_b);
               read_enable  <= NOT(CE1_b) AND CE2 AND (WE_b) AND NOT(OE_b) AND NOT(BHE_b AND BLE_b);
               data_skew    <= DQ AFTER 1 ns;        -- changed on feb 15
               address_skew <= A  AFTER 1 ns;
               PROCESS (OE_b)
               BEGIN
                 IF (OE_b'EVENT AND OE_b = '1' AND write_enable /= '1') THEN
                   DQ <= (OTHERS => 'Z') after tHZOE;
                 END IF;
               END PROCESS;
               PROCESS (CE_b)
               BEGIN
                 IF (CE_b'EVENT AND CE_b = '1') THEN
                   DQ <= (OTHERS => 'Z') after tHZCE;
                 END IF;
               END PROCESS;
               PROCESS (write_enable'DELAYED(tHA))
               BEGIN
                 IF (write_enable'DELAYED(tHA) = '0' AND TimingInfo) THEN
                   ASSERT (A'LAST_EVENT = 0 ns) OR (A'LAST_EVENT > tHA)
                     REPORT "Address hold time tHA violated";
                 END IF;
               END PROCESS;
               PROCESS (write_enable'DELAYED(tHD))
               BEGIN
                 IF (write_enable'DELAYED(tHD) = '0' AND TimingInfo) THEN
                   ASSERT (DQ'LAST_EVENT > tHD) OR (DQ'LAST_EVENT = 0 ns)
                     REPORT "Data hold time tHD violated";
                 END IF;
               END PROCESS;
             -- main process
               PROCESS
                 VARIABLE mem_array : mem_array_type;
             --- Variables for timing checks
                 VARIABLE tPWE_chk  : TIME := -10 ns;
                 VARIABLE tAW_chk   : TIME := -10 ns;
                 VARIABLE tSD_chk   : TIME := -10 ns;
                 VARIABLE tRC_chk   : TIME := 0 ns;
                 VARIABLE tBAW_chk  : TIME := 0 ns;
                 VARIABLE tBBW_chk  : TIME := 0 ns;
                 VARIABLE tBCW_chk  : TIME := 0 ns;
                 VARIABLE tBDW_chk  : TIME := 0 ns;
                 VARIABLE tSA_chk   : TIME := 0 ns;
                 VARIABLE tSA_skew  : TIME := 0 ns;
                 VARIABLE tAint_chk : TIME := -10 ns;
                 VARIABLE write_flag : BOOLEAN := true;
                 VARIABLE accesstime : TIME := 0 ns;
               BEGIN
                 IF (address_skew'EVENT) THEN
                   tSA_skew := NOW;
                 END IF;
                 -- start of write
                 IF (write_enable = '1' AND write_enable'EVENT) THEN
                   DQ(DATA_BITS-1 DOWNTO 0) <= (OTHERS => 'Z') after tHZWE;
                   IF (A'LAST_EVENT >= tSA) THEN
                     address_internal <= A;
                     tPWE_chk         := NOW;
                     tAW_chk          := A'LAST_EVENT;
                     tAint_chk        := NOW;
                     write_flag       := true;
                   ELSE
                     IF (TimingInfo) THEN
                       ASSERT false
                         REPORT "Address setup violated";
                     END IF;
                     write_flag := false;
                   END IF;
                   -- end of write (with CE high or WE high)
                 ELSIF (write_enable = '0' AND write_enable'EVENT) THEN
                   --- check for pulse width
                   IF (NOW - tPWE_chk >= tPWE OR NOW - tPWE_chk <= 0.1 ns OR NOW = 0 ns) THEN
                     --- pulse width OK, do nothing
                   ELSE
                     IF (TimingInfo) THEN
                       ASSERT false
                         REPORT "Pulse Width violation";
                     END IF;
                     write_flag := false;
                   END IF;
                   IF (NOW > 0 ns) THEN
                     IF (tSA_skew - tAint_chk > tskew) THEN
                       ASSERT false
                         REPORT "Negative address setup";
                       write_flag := false;
                     END IF;
                   END IF;
                   --- check for address setup with write end, i.e., tAW
                   IF (NOW - tAW_chk >= tAW OR NOW = 0 ns) THEN
                     --- tAW OK, do nothing
                   ELSE
                     IF (TimingInfo) THEN
                       ASSERT false
                         REPORT "Address setup tAW violation";
                     END IF;
                     write_flag := false;
                   END IF;
                   --- check for data setup with write end, i.e., tSD
                   IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
                     --- tSD OK, do nothing
                   ELSE
                     IF (TimingInfo) THEN
                       ASSERT false
                         REPORT "Data setup tSD violation";
                     END IF;
                     write_flag := false;
                   END IF;
                   -- perform write operation if no violations
                   IF (write_flag = true) THEN
                     IF (BLE_b = '1' AND BLE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN
                       mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
                     END IF;
                     IF (BHE_b = '1' AND BHE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN
                       mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
                     END IF;
                     IF (BLE_b = '0' AND NOW - tBAW_chk >= tBW) THEN
                       mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
                     ELSIF (NOW - tBAW_chk < tBW AND NOW - tBAW_chk > 0.1 ns AND NOW > 0 ns) THEN
                       ASSERT false REPORT "Insufficient pulse width for lower byte to be written";
                     END IF;
                     IF (BHE_b = '0' AND NOW - tBBW_chk >= tBW) THEN
                       mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
                     ELSIF (NOW - tBBW_chk < tBW AND NOW - tBBW_chk > 0.1 ns AND NOW > 0 ns) THEN
                       ASSERT false REPORT "Insufficient pulse width for higher byte to be written";
                     END IF;
                     -------------------------------------------------------------------------------JC\/
-                    all_mem_array_obs: FOR I IN 0 TO 127 LOOP
+                    all_mem_array_obs: FOR I IN 0 TO 31 LOOP
-                      IF I < depth THEN
+                      IF I + ((2**15) *0) < depth THEN  mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF;
-                        mem_array_t(I) <= mem_array(I);
+                      IF I + ((2**15) *1) < depth THEN  mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF;
-                      END IF;
+                      IF I + ((2**15) *2) < depth THEN  mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF;
+                      IF I + ((2**15) *3) < depth THEN  mem_array_3(I) <= mem_array(I+((2**15) *3)); END IF;
                     END LOOP all_mem_array_obs;
                     -------------------------------------------------------------------------------JC/\
                   END IF;
                   -- end of write (with BLE high)
                 ELSIF (BLE_b'EVENT AND NOT(BHE_b'EVENT) AND write_enable = '1') THEN
                   IF (BLE_b = '0') THEN
                     --- Reset timing variables
                     tAW_chk    := A'LAST_EVENT;
                     tBAW_chk   := NOW;
                     write_flag := true;
                   ELSIF (BLE_b = '1') THEN
                     --- check for pulse width
                     IF (NOW - tPWE_chk >= tPWE) THEN
                       --- tPWE OK, do nothing
                     ELSE
                       IF (TimingInfo) THEN
                         ASSERT false
                           REPORT "Pulse Width violation";
                       END IF;
                       write_flag := false;
                     END IF;
                     --- check for address setup with write end, i.e., tAW
                     IF (NOW - tAW_chk >= tAW) THEN
                       --- tAW OK, do nothing
                     ELSE
                       IF (TimingInfo) THEN
                         ASSERT false
                           REPORT "Address setup tAW violation for Lower Byte Write";
                       END IF;
                       write_flag := false;
                     END IF;
                     --- check for byte write setup with write end, i.e., tBW
                     IF (NOW - tBAW_chk >= tBW) THEN
                       --- tBW OK, do nothing
                     ELSE
                       IF (TimingInfo) THEN
                         ASSERT false
                           REPORT "Lower Byte setup tBW violation";
                       END IF;
                       write_flag := false;
                     END IF;
                     --- check for data setup with write end, i.e., tSD
                     IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
                       --- tSD OK, do nothing
                     ELSE
                       IF (TimingInfo) THEN
                         ASSERT false
                           REPORT "Data setup tSD violation for Lower Byte Write";
                       END IF;
                       write_flag := false;
                     END IF;
                     --- perform WRITE operation if no violations
                     IF (write_flag = true) THEN
                       mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
                       IF (BHE_b = '0') THEN
                         mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
                       END IF;
                     END IF;
                     --- Reset timing variables
                     tAW_chk    := A'LAST_EVENT;
                     tBAW_chk   := NOW;
                     write_flag := true;
                   END IF;
                   -- end of write (with BHE high)
                 ELSIF (BHE_b'EVENT AND NOT(BLE_b'EVENT) AND write_enable = '1') THEN
                   IF (BHE_b = '0') THEN
                     --- Reset timing variables
                     tAW_chk    := A'LAST_EVENT;
                     tBBW_chk   := NOW;
                     write_flag := true;
                   ELSIF (BHE_b = '1') THEN
                     --- check for pulse width
                     IF (NOW - tPWE_chk >= tPWE) THEN
                       --- tPWE OK, do nothing
                     ELSE
                       IF (TimingInfo) THEN
                         ASSERT false
                           REPORT "Pulse Width violation";
                       END IF;
                       write_flag := false;
                     END IF;
                     --- check for address setup with write end, i.e., tAW
                     IF (NOW - tAW_chk >= tAW) THEN
                       --- tAW OK, do nothing
                     ELSE
                       IF (TimingInfo) THEN
                         ASSERT false
                           REPORT "Address setup tAW violation for Upper Byte Write";
                       END IF;
                       write_flag := false;
                     END IF;
                     --- check for byte setup with write end, i.e., tBW
                     IF (NOW - tBBW_chk >= tBW) THEN
                       --- tBW OK, do nothing
                     ELSE
                       IF (TimingInfo) THEN
                         ASSERT false
                           REPORT "Upper Byte setup tBW violation";
                       END IF;
                       write_flag := false;
                     END IF;
                     --- check for data setup with write end, i.e., tSD
                     IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
                       --- tSD OK, do nothing
                     ELSE
                       IF (TimingInfo) THEN
                         ASSERT false
                           REPORT "Data setup tSD violation for Upper Byte Write";
                       END IF;
                       write_flag := false;
                     END IF;
                     --- perform WRITE operation if no violations
                     IF (write_flag = true) THEN
                       mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
                       IF (BLE_b = '0') THEN
                         mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
                       END IF;
                     END IF;
                     --- Reset timing variables
                     tAW_chk    := A'LAST_EVENT;
                     tBBW_chk   := NOW;
                     write_flag := true;
                   END IF;
                 END IF;
                 --- END OF WRITE
                 IF (data_skew'EVENT AND read_enable /= '1') THEN
                   tSD_chk := NOW;
                 END IF;
                 --- START of READ
                 --- Tri-state the data bus if CE or OE disabled
                 IF (read_enable = '0' AND read_enable'EVENT) THEN
                   IF (OE_b'LAST_EVENT >= CE_b'LAST_EVENT) THEN
                     DQ <= (OTHERS => 'Z') after tHZCE;
                   ELSIF (CE_b'LAST_EVENT > OE_b'LAST_EVENT) THEN
                     DQ <= (OTHERS => 'Z') after tHZOE;
                   END IF;
                 END IF;
                 --- Address-controlled READ operation
                 IF (A'EVENT) THEN
                   IF (A'LAST_EVENT = CE_b'LAST_EVENT AND CE_b = '1') THEN
                     DQ <= (OTHERS => 'Z') after tHZCE;
                   END IF;
                   IF (NOW - tRC_chk >= tRC OR NOW - tRC_chk <= 0.1 ns OR tRC_chk = 0 ns) THEN
                     --- tRC OK, do nothing
                   ELSE
                     IF (TimingInfo) THEN
                       ASSERT false
                         REPORT "Read Cycle time tRC violation";
                     END IF;
                   END IF;
                   IF (read_enable = '1') THEN
                     IF (BLE_b = '0') THEN
                       DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A))(7 DOWNTO 0) AFTER tAA;
                     END IF;
                     IF (BHE_b = '0') THEN
                       DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A))(15 DOWNTO 8) AFTER tAA;
                     END IF;
                     tRC_chk := NOW;
                   END IF;
                   IF (write_enable = '1') THEN
                     --- do nothing
                   END IF;
                 END IF;
                 IF (read_enable = '0' AND read_enable'EVENT) THEN
                   DQ <= (OTHERS => 'Z') after tHZCE;
                   IF (NOW - tRC_chk >= tRC OR tRC_chk = 0 ns OR A'LAST_EVENT = read_enable'LAST_EVENT) THEN
                     --- tRC_chk needs to be reset when read ends
                     tRC_CHK := 0 ns;
                   ELSE
                     IF (TimingInfo) THEN
                       ASSERT false
                         REPORT "Read Cycle time tRC violation";
                     END IF;
                     tRC_CHK := 0 ns;
                   END IF;
                 END IF;
                 --- READ operation triggered by CE/OE/BHE/BLE
                 IF (read_enable = '1' AND read_enable'EVENT) THEN
                   tRC_chk := NOW;
                   --- CE triggered READ
                   IF (CE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN  --  changed rev2
                     IF (BLE_b = '0') THEN
                       DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE;
                     END IF;
                     IF (BHE_b = '0') THEN
                       DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE;
                     END IF;
                   END IF;
                   --- OE triggered READ
                   IF (OE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
                     -- if address or CE changes before OE such that tAA/tACE > tDOE
                     IF (CE_b'LAST_EVENT < tACE - tDOE AND A'LAST_EVENT < tAA - tDOE) THEN
                       IF (A'LAST_EVENT < CE_b'LAST_EVENT) THEN
                         accesstime := tAA-A'LAST_EVENT;
                         IF (BLE_b = '0') THEN
                           DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
                         END IF;
                         IF (BHE_b = '0') THEN
                           DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
                         END IF;
                       ELSE
                         accesstime := tACE-CE_b'LAST_EVENT;
                         IF (BLE_b = '0') THEN
                           DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
                         END IF;
                         IF (BHE_b = '0') THEN
                           DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
                         END IF;
                       END IF;
                       -- if address changes before OE such that tAA > tDOE
                     ELSIF (A'LAST_EVENT < tAA - tDOE) THEN
                       accesstime := tAA-A'LAST_EVENT;
                       IF (BLE_b = '0') THEN
                         DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
                       END IF;
                       IF (BHE_b = '0') THEN
                         DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
                       END IF;
                       -- if CE changes before OE such that tACE > tDOE
                     ELSIF (CE_b'LAST_EVENT < tACE - tDOE) THEN
                       accesstime := tACE-CE_b'LAST_EVENT;
                       IF (BLE_b = '0') THEN
                         DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
                       END IF;
                       IF (BHE_b = '0') THEN
                         DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
                       END IF;
                       -- if OE changes such that tDOE > tAA/tACE
                     ELSE
                       IF (BLE_b = '0') THEN
                         DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDOE;
                       END IF;
                       IF (BHE_b = '0') THEN
                         DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDOE;
                       END IF;
                     END IF;
                   END IF;
                   --- END of OE triggered READ
                   --- BLE/BHE triggered READ
                   IF (BLE_b'LAST_EVENT = read_enable'LAST_EVENT OR BHE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
                     -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE
                     IF (CE_b'LAST_EVENT < tACE - tDBE AND A'LAST_EVENT < tAA - tDBE) THEN
                       IF (A'LAST_EVENT < BLE_b'LAST_EVENT) THEN
                         accesstime := tAA-A'LAST_EVENT;
                         IF (BLE_b = '0') THEN
                           DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
                         END IF;
                         IF (BHE_b = '0') THEN
                           DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
                         END IF;
                       ELSE
                         accesstime := tACE-CE_b'LAST_EVENT;
                         IF (BLE_b = '0') THEN
                           DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
                         END IF;
                         IF (BHE_b = '0') THEN
                           DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
                         END IF;
                       END IF;
                       -- if address changes before BHE/BLE such that tAA > tDBE
                     ELSIF (A'LAST_EVENT < tAA - tDBE) THEN
                       accesstime := tAA-A'LAST_EVENT;
                       IF (BLE_b = '0') THEN
                         DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
                       END IF;
                       IF (BHE_b = '0') THEN
                         DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
                       END IF;
                       -- if CE changes before BHE/BLE such that tACE > tDBE
                     ELSIF (CE_b'LAST_EVENT < tACE - tDBE) THEN
                       accesstime := tACE-CE_b'LAST_EVENT;
                       IF (BLE_b = '0') THEN
                         DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
                       END IF;
                       IF (BHE_b = '0') THEN
                         DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
                       END IF;
                       -- if BHE/BLE changes such that tDBE > tAA/tACE
                     ELSE
                       IF (BLE_b = '0') THEN
                         DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE;
                       END IF;
                       IF (BHE_b = '0') THEN
                         DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE;
                       END IF;
                     END IF;
                   END IF;
                   -- END of BHE/BLE controlled READ
                   IF (WE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
                     IF (BLE_b = '0') THEN
                       DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE;
                     END IF;
                     IF (BHE_b = '0') THEN
                       DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE;
                     END IF;
                   END IF;
                 END IF;
                 --- END OF CE/OE/BHE/BLE controlled READ
                 --- If either BHE or BLE toggle during read mode
                 IF (BLE_b'EVENT AND BLE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN
                   DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE;
                 END IF;
                 IF (BHE_b'EVENT AND BHE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN
                   DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE;
                 END IF;
                 --- tri-state bus depending on BHE/BLE
                 IF (BLE_b'EVENT AND BLE_b = '1') THEN
                   DQ (7 DOWNTO 0) <= (OTHERS => 'Z') after tHZBE;
                 END IF;
                 IF (BHE_b'EVENT AND BHE_b = '1') THEN
                   DQ (15 DOWNTO 8) <= (OTHERS => 'Z') after tHZBE;
                 END IF;
                 WAIT ON write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew, address_skew;
               END PROCESS;
             END behave_arch;

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