@@ -1,48 +1,54 | |||||
1 | onerror {resume} |
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1 | onerror {resume} | |
2 | quietly WaveActivateNextPane {} 0 |
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2 | quietly WaveActivateNextPane {} 0 | |
3 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot |
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3 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot | |
4 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run |
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4 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run | |
5 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out |
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5 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out | |
6 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out |
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6 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out | |
7 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out |
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7 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out | |
8 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid |
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8 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid | |
9 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid |
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9 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid | |
10 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid |
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10 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid | |
11 | add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd |
|
11 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd | |
12 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_1/mem_array_t |
|
12 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address | |
13 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_t |
|
13 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in | |
14 |
add wave -noupdate |
|
14 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out | |
15 |
add wave -noupdate |
|
15 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data | |
16 |
add wave -noupdate |
|
16 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay | |
17 |
add wave -noupdate |
|
17 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done | |
18 |
add wave -noupdate |
|
18 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex | |
19 |
add wave -noupdate |
|
19 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn | |
20 |
add wave -noupdate |
|
20 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren | |
21 |
add wave -noupdate |
|
21 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run | |
22 |
add wave -noupdate |
|
22 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send | |
23 |
add wave -noupdate |
|
23 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst | |
24 |
add wave -noupdate |
|
24 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin | |
25 |
add wave -noupdate |
|
25 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout | |
26 | add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin |
|
26 | add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain | |
27 | add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout |
|
|||
28 | add wave -noupdate -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain |
|
|||
29 | add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data |
|
27 | add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data | |
30 | add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant |
|
28 | add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant | |
31 |
add wave -noupdate |
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29 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout | |
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30 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0 | |||
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31 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_0 | |||
|
32 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1 | |||
|
33 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1 | |||
|
34 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2 | |||
|
35 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 | |||
|
36 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3 | |||
|
37 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_3 | |||
32 | TreeUpdate [SetDefaultTree] |
|
38 | TreeUpdate [SetDefaultTree] | |
33 |
WaveRestoreCursors {{Cursor 1} {12 |
|
39 | WaveRestoreCursors {{Cursor 1} {12913873180 ps} 0} | |
34 | configure wave -namecolwidth 540 |
|
40 | configure wave -namecolwidth 540 | |
35 | configure wave -valuecolwidth 316 |
|
41 | configure wave -valuecolwidth 316 | |
36 | configure wave -justifyvalue left |
|
42 | configure wave -justifyvalue left | |
37 | configure wave -signalnamewidth 0 |
|
43 | configure wave -signalnamewidth 0 | |
38 | configure wave -snapdistance 10 |
|
44 | configure wave -snapdistance 10 | |
39 | configure wave -datasetprefix 0 |
|
45 | configure wave -datasetprefix 0 | |
40 | configure wave -rowmargin 4 |
|
46 | configure wave -rowmargin 4 | |
41 | configure wave -childrowmargin 2 |
|
47 | configure wave -childrowmargin 2 | |
42 | configure wave -gridoffset 0 |
|
48 | configure wave -gridoffset 0 | |
43 | configure wave -gridperiod 1 |
|
49 | configure wave -gridperiod 1 | |
44 | configure wave -griddelta 40 |
|
50 | configure wave -griddelta 40 | |
45 | configure wave -timeline 0 |
|
51 | configure wave -timeline 0 | |
46 | configure wave -timelineunits ns |
|
52 | configure wave -timelineunits ns | |
47 | update |
|
53 | update | |
48 |
WaveRestoreZoom {0 ps} { |
|
54 | WaveRestoreZoom {0 ps} {63240778126 ps} |
@@ -1,445 +1,445 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- LEON3 Demonstration design test bench |
|
2 | -- LEON3 Demonstration design test bench | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | ------------------------------------------------------------------------------ |
|
4 | ------------------------------------------------------------------------------ | |
5 | -- This file is a part of the GRLIB VHDL IP LIBRARY |
|
5 | -- This file is a part of the GRLIB VHDL IP LIBRARY | |
6 | -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. |
|
6 | -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. | |
7 | -- |
|
7 | -- | |
8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN |
|
8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN | |
9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED |
|
9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED | |
10 | -- IN ADVANCE IN WRITING. |
|
10 | -- IN ADVANCE IN WRITING. | |
11 | ------------------------------------------------------------------------------ |
|
11 | ------------------------------------------------------------------------------ | |
12 |
|
12 | |||
13 | LIBRARY ieee; |
|
13 | LIBRARY ieee; | |
14 | USE ieee.std_logic_1164.ALL; |
|
14 | USE ieee.std_logic_1164.ALL; | |
15 |
|
15 | |||
16 | --LIBRARY std; |
|
16 | --LIBRARY std; | |
17 | --USE std.textio.ALL; |
|
17 | --USE std.textio.ALL; | |
18 |
|
18 | |||
19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
22 | LIBRARY gaisler; |
|
22 | LIBRARY gaisler; | |
23 | USE gaisler.memctrl.ALL; |
|
23 | USE gaisler.memctrl.ALL; | |
24 | USE gaisler.leon3.ALL; |
|
24 | USE gaisler.leon3.ALL; | |
25 | USE gaisler.uart.ALL; |
|
25 | USE gaisler.uart.ALL; | |
26 | USE gaisler.misc.ALL; |
|
26 | USE gaisler.misc.ALL; | |
27 | USE gaisler.libdcom.ALL; |
|
27 | USE gaisler.libdcom.ALL; | |
28 | USE gaisler.sim.ALL; |
|
28 | USE gaisler.sim.ALL; | |
29 | USE gaisler.jtagtst.ALL; |
|
29 | USE gaisler.jtagtst.ALL; | |
30 | USE gaisler.misc.ALL; |
|
30 | USE gaisler.misc.ALL; | |
31 | LIBRARY techmap; |
|
31 | LIBRARY techmap; | |
32 | USE techmap.gencomp.ALL; |
|
32 | USE techmap.gencomp.ALL; | |
33 | LIBRARY esa; |
|
33 | LIBRARY esa; | |
34 | USE esa.memoryctrl.ALL; |
|
34 | USE esa.memoryctrl.ALL; | |
35 | --LIBRARY micron; |
|
35 | --LIBRARY micron; | |
36 | --USE micron.components.ALL; |
|
36 | --USE micron.components.ALL; | |
37 | LIBRARY lpp; |
|
37 | LIBRARY lpp; | |
38 | USE lpp.lpp_waveform_pkg.ALL; |
|
38 | USE lpp.lpp_waveform_pkg.ALL; | |
39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
|
40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.testbench_package.ALL; |
|
41 | USE lpp.testbench_package.ALL; | |
42 | USE lpp.lpp_lfr_pkg.ALL; |
|
42 | USE lpp.lpp_lfr_pkg.ALL; | |
43 | USE lpp.iir_filter.ALL; |
|
43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
|
44 | USE lpp.general_purpose.ALL; | |
45 | USE lpp.CY7C1061DV33_pkg.ALL; |
|
45 | USE lpp.CY7C1061DV33_pkg.ALL; | |
46 |
|
46 | |||
47 | ENTITY testbench IS |
|
47 | ENTITY testbench IS | |
48 | END; |
|
48 | END; | |
49 |
|
49 | |||
50 | ARCHITECTURE behav OF testbench IS |
|
50 | ARCHITECTURE behav OF testbench IS | |
51 | -- REG ADDRESS |
|
51 | -- REG ADDRESS | |
52 | CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15; |
|
52 | CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15; | |
53 | CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15; |
|
53 | CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15; | |
54 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; |
|
54 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; | |
55 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; |
|
55 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; | |
56 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; |
|
56 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; | |
57 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; |
|
57 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; | |
58 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; |
|
58 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; | |
59 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; |
|
59 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; | |
60 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; |
|
60 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; | |
61 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; |
|
61 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; | |
62 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; |
|
62 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; | |
63 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; |
|
63 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; | |
64 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; |
|
64 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; | |
65 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; |
|
65 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; | |
66 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; |
|
66 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; | |
67 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; |
|
67 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; | |
68 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; |
|
68 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; | |
69 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; |
|
69 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; | |
70 | -- RAM ADDRESS |
|
70 | -- RAM ADDRESS | |
71 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; |
|
71 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; | |
72 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
|
72 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; | |
73 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; |
|
73 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; | |
74 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; |
|
74 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; | |
75 |
|
75 | |||
76 |
|
76 | |||
77 | -- Common signal |
|
77 | -- Common signal | |
78 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; |
|
78 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; | |
79 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
|
79 | SIGNAL clk25MHz : STD_LOGIC := '0'; | |
80 | SIGNAL rstn : STD_LOGIC := '0'; |
|
80 | SIGNAL rstn : STD_LOGIC := '0'; | |
81 |
|
81 | |||
82 | -- ADC interface |
|
82 | -- ADC interface | |
83 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT |
|
83 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT | |
84 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT |
|
84 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT | |
85 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN |
|
85 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN | |
86 |
|
86 | |||
87 | -- AD Converter RHF1401 |
|
87 | -- AD Converter RHF1401 | |
88 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
88 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
89 | SIGNAL sample_val : STD_LOGIC; |
|
89 | SIGNAL sample_val : STD_LOGIC; | |
90 |
|
90 | |||
91 | -- AHB/APB SIGNAL |
|
91 | -- AHB/APB SIGNAL | |
92 | SIGNAL apbi : apb_slv_in_type; |
|
92 | SIGNAL apbi : apb_slv_in_type; | |
93 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
|
93 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
94 | SIGNAL ahbsi : ahb_slv_in_type; |
|
94 | SIGNAL ahbsi : ahb_slv_in_type; | |
95 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
|
95 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
96 | SIGNAL ahbmi : ahb_mst_in_type; |
|
96 | SIGNAL ahbmi : ahb_mst_in_type; | |
97 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
|
97 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
98 |
|
98 | |||
99 | SIGNAL bias_fail_bw : STD_LOGIC; |
|
99 | SIGNAL bias_fail_bw : STD_LOGIC; | |
100 |
|
100 | |||
101 | ----------------------------------------------------------------------------- |
|
101 | ----------------------------------------------------------------------------- | |
102 | -- LPP_WAVEFORM |
|
102 | -- LPP_WAVEFORM | |
103 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
104 | CONSTANT data_size : INTEGER := 96; |
|
104 | CONSTANT data_size : INTEGER := 96; | |
105 | CONSTANT nb_burst_available_size : INTEGER := 50; |
|
105 | CONSTANT nb_burst_available_size : INTEGER := 50; | |
106 | CONSTANT nb_snapshot_param_size : INTEGER := 2; |
|
106 | CONSTANT nb_snapshot_param_size : INTEGER := 2; | |
107 | CONSTANT delta_vector_size : INTEGER := 2; |
|
107 | CONSTANT delta_vector_size : INTEGER := 2; | |
108 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; |
|
108 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; | |
109 |
|
109 | |||
110 | SIGNAL reg_run : STD_LOGIC; |
|
110 | SIGNAL reg_run : STD_LOGIC; | |
111 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
111 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
112 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
112 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
113 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
113 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
114 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
114 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
115 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
115 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
116 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
116 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
117 | SIGNAL enable_f0 : STD_LOGIC; |
|
117 | SIGNAL enable_f0 : STD_LOGIC; | |
118 | SIGNAL enable_f1 : STD_LOGIC; |
|
118 | SIGNAL enable_f1 : STD_LOGIC; | |
119 | SIGNAL enable_f2 : STD_LOGIC; |
|
119 | SIGNAL enable_f2 : STD_LOGIC; | |
120 | SIGNAL enable_f3 : STD_LOGIC; |
|
120 | SIGNAL enable_f3 : STD_LOGIC; | |
121 | SIGNAL burst_f0 : STD_LOGIC; |
|
121 | SIGNAL burst_f0 : STD_LOGIC; | |
122 | SIGNAL burst_f1 : STD_LOGIC; |
|
122 | SIGNAL burst_f1 : STD_LOGIC; | |
123 | SIGNAL burst_f2 : STD_LOGIC; |
|
123 | SIGNAL burst_f2 : STD_LOGIC; | |
124 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
124 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
125 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
125 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
126 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
126 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
127 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
127 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
128 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
128 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
129 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
129 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
130 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
131 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
131 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
132 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
133 | SIGNAL data_f0_in_valid : STD_LOGIC; |
|
133 | SIGNAL data_f0_in_valid : STD_LOGIC; | |
134 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
134 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
135 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
135 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
136 | SIGNAL data_f1_in_valid : STD_LOGIC; |
|
136 | SIGNAL data_f1_in_valid : STD_LOGIC; | |
137 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
137 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
138 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
138 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
139 | SIGNAL data_f2_in_valid : STD_LOGIC; |
|
139 | SIGNAL data_f2_in_valid : STD_LOGIC; | |
140 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
140 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
141 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
141 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
142 | SIGNAL data_f3_in_valid : STD_LOGIC; |
|
142 | SIGNAL data_f3_in_valid : STD_LOGIC; | |
143 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
143 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
144 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
144 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
145 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
145 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
146 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
146 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
147 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
147 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
148 | SIGNAL data_f0_data_out_ack : STD_LOGIC; |
|
148 | SIGNAL data_f0_data_out_ack : STD_LOGIC; | |
149 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
149 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
150 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
150 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
151 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
151 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
152 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
152 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
153 | SIGNAL data_f1_data_out_ack : STD_LOGIC; |
|
153 | SIGNAL data_f1_data_out_ack : STD_LOGIC; | |
154 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
155 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
155 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
156 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
156 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
157 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
157 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
158 | SIGNAL data_f2_data_out_ack : STD_LOGIC; |
|
158 | SIGNAL data_f2_data_out_ack : STD_LOGIC; | |
159 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
159 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
160 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
160 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
161 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
161 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
162 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
162 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
163 | SIGNAL data_f3_data_out_ack : STD_LOGIC; |
|
163 | SIGNAL data_f3_data_out_ack : STD_LOGIC; | |
164 |
|
164 | |||
165 | --MEM CTRLR |
|
165 | --MEM CTRLR | |
166 | SIGNAL memi : memory_in_type; |
|
166 | SIGNAL memi : memory_in_type; | |
167 | SIGNAL memo : memory_out_type; |
|
167 | SIGNAL memo : memory_out_type; | |
168 | SIGNAL wpo : wprot_out_type; |
|
168 | SIGNAL wpo : wprot_out_type; | |
169 | SIGNAL sdo : sdram_out_type; |
|
169 | SIGNAL sdo : sdram_out_type; | |
170 |
|
170 | |||
171 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
171 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0); | |
172 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
172 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
173 | SIGNAL nSRAM_BE0 : STD_LOGIC; |
|
173 | SIGNAL nSRAM_BE0 : STD_LOGIC; | |
174 | SIGNAL nSRAM_BE1 : STD_LOGIC; |
|
174 | SIGNAL nSRAM_BE1 : STD_LOGIC; | |
175 | SIGNAL nSRAM_BE2 : STD_LOGIC; |
|
175 | SIGNAL nSRAM_BE2 : STD_LOGIC; | |
176 | SIGNAL nSRAM_BE3 : STD_LOGIC; |
|
176 | SIGNAL nSRAM_BE3 : STD_LOGIC; | |
177 | SIGNAL nSRAM_WE : STD_LOGIC; |
|
177 | SIGNAL nSRAM_WE : STD_LOGIC; | |
178 | SIGNAL nSRAM_CE : STD_LOGIC; |
|
178 | SIGNAL nSRAM_CE : STD_LOGIC; | |
179 | SIGNAL nSRAM_OE : STD_LOGIC; |
|
179 | SIGNAL nSRAM_OE : STD_LOGIC; | |
180 |
|
180 | |||
181 | CONSTANT padtech : INTEGER := inferred; |
|
181 | CONSTANT padtech : INTEGER := inferred; | |
182 | SIGNAL not_ramsn_0 : STD_LOGIC; |
|
182 | SIGNAL not_ramsn_0 : STD_LOGIC; | |
183 |
|
183 | |||
184 |
|
184 | |||
185 | BEGIN |
|
185 | BEGIN | |
186 |
|
186 | |||
187 | ----------------------------------------------------------------------------- |
|
187 | ----------------------------------------------------------------------------- | |
188 |
|
188 | |||
189 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
|
189 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz | |
190 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz |
|
190 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz | |
191 |
|
191 | |||
192 | ----------------------------------------------------------------------------- |
|
192 | ----------------------------------------------------------------------------- | |
193 |
|
193 | |||
194 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
|
194 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE | |
195 | TestModule_RHF1401_1 : TestModule_RHF1401 |
|
195 | TestModule_RHF1401_1 : TestModule_RHF1401 | |
196 | GENERIC MAP ( |
|
196 | GENERIC MAP ( | |
197 | freq => 24*(I+1), |
|
197 | freq => 24*(I+1), | |
198 | amplitude => 8000/(I+1), |
|
198 | amplitude => 8000/(I+1), | |
199 | impulsion => 0) |
|
199 | impulsion => 0) | |
200 | PORT MAP ( |
|
200 | PORT MAP ( | |
201 | ADC_smpclk => ADC_smpclk, |
|
201 | ADC_smpclk => ADC_smpclk, | |
202 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
|
202 | ADC_OEB_bar => ADC_OEB_bar_CH(I), | |
203 | ADC_data => ADC_data); |
|
203 | ADC_data => ADC_data); | |
204 | END GENERATE MODULE_RHF1401; |
|
204 | END GENERATE MODULE_RHF1401; | |
205 |
|
205 | |||
206 | ----------------------------------------------------------------------------- |
|
206 | ----------------------------------------------------------------------------- | |
207 |
|
207 | |||
208 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
|
208 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 | |
209 | GENERIC MAP ( |
|
209 | GENERIC MAP ( | |
210 | ChanelCount => 8, |
|
210 | ChanelCount => 8, | |
211 | ncycle_cnv_high => 79, |
|
211 | ncycle_cnv_high => 79, | |
212 | ncycle_cnv => 500) |
|
212 | ncycle_cnv => 500) | |
213 | PORT MAP ( |
|
213 | PORT MAP ( | |
214 | cnv_clk => clk49_152MHz, |
|
214 | cnv_clk => clk49_152MHz, | |
215 | cnv_rstn => rstn, |
|
215 | cnv_rstn => rstn, | |
216 | cnv => ADC_smpclk, |
|
216 | cnv => ADC_smpclk, | |
217 | clk => clk25MHz, |
|
217 | clk => clk25MHz, | |
218 | rstn => rstn, |
|
218 | rstn => rstn, | |
219 | ADC_data => ADC_data, |
|
219 | ADC_data => ADC_data, | |
220 | ADC_nOE => ADC_OEB_bar_CH, |
|
220 | ADC_nOE => ADC_OEB_bar_CH, | |
221 | sample => sample, |
|
221 | sample => sample, | |
222 | sample_val => sample_val); |
|
222 | sample_val => sample_val); | |
223 |
|
223 | |||
224 | ----------------------------------------------------------------------------- |
|
224 | ----------------------------------------------------------------------------- | |
225 |
|
225 | |||
226 | lpp_lfr_1 : lpp_lfr |
|
226 | lpp_lfr_1 : lpp_lfr | |
227 | GENERIC MAP ( |
|
227 | GENERIC MAP ( | |
228 | Mem_use => use_CEL, -- use_RAM |
|
228 | Mem_use => use_CEL, -- use_RAM | |
229 | nb_data_by_buffer_size => 32, |
|
229 | nb_data_by_buffer_size => 32, | |
230 | nb_word_by_buffer_size => 30, |
|
230 | nb_word_by_buffer_size => 30, | |
231 | nb_snapshot_param_size => 32, |
|
231 | nb_snapshot_param_size => 32, | |
232 | delta_vector_size => 32, |
|
232 | delta_vector_size => 32, | |
233 | delta_vector_size_f0_2 => 32, |
|
233 | delta_vector_size_f0_2 => 32, | |
234 | pindex => INDEX_WAVEFORM_PICKER, |
|
234 | pindex => INDEX_WAVEFORM_PICKER, | |
235 | paddr => ADDR_WAVEFORM_PICKER, |
|
235 | paddr => ADDR_WAVEFORM_PICKER, | |
236 | pmask => 16#fff#, |
|
236 | pmask => 16#fff#, | |
237 | pirq_ms => 6, |
|
237 | pirq_ms => 6, | |
238 | pirq_wfp => 14, |
|
238 | pirq_wfp => 14, | |
239 | hindex => 0, |
|
239 | hindex => 0, | |
240 | top_lfr_version => X"00000001") |
|
240 | top_lfr_version => X"00000001") | |
241 | PORT MAP ( |
|
241 | PORT MAP ( | |
242 | clk => clk25MHz, |
|
242 | clk => clk25MHz, | |
243 | rstn => rstn, |
|
243 | rstn => rstn, | |
244 | sample_B => sample(2 DOWNTO 0), |
|
244 | sample_B => sample(2 DOWNTO 0), | |
245 | sample_E => sample(7 DOWNTO 3), |
|
245 | sample_E => sample(7 DOWNTO 3), | |
246 | sample_val => sample_val, |
|
246 | sample_val => sample_val, | |
247 | apbi => apbi, |
|
247 | apbi => apbi, | |
248 | apbo => apbo(15), |
|
248 | apbo => apbo(15), | |
249 | ahbi => ahbmi, |
|
249 | ahbi => ahbmi, | |
250 | ahbo => ahbmo(0), |
|
250 | ahbo => ahbmo(0), | |
251 | coarse_time => coarse_time, |
|
251 | coarse_time => coarse_time, | |
252 | fine_time => fine_time, |
|
252 | fine_time => fine_time, | |
253 | data_shaping_BW => bias_fail_bw); |
|
253 | data_shaping_BW => bias_fail_bw); | |
254 |
|
254 | |||
255 | ----------------------------------------------------------------------------- |
|
255 | ----------------------------------------------------------------------------- | |
256 | --- AHB CONTROLLER ------------------------------------------------- |
|
256 | --- AHB CONTROLLER ------------------------------------------------- | |
257 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
257 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
258 | GENERIC MAP (defmast => 0, split => 0, |
|
258 | GENERIC MAP (defmast => 0, split => 0, | |
259 | rrobin => 1, ioaddr => 16#FFF#, |
|
259 | rrobin => 1, ioaddr => 16#FFF#, | |
260 | ioen => 0, nahbm => 1, nahbs => 1) |
|
260 | ioen => 0, nahbm => 1, nahbs => 1) | |
261 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
261 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); | |
262 |
|
262 | |||
263 | --- AHB RAM ---------------------------------------------------------- |
|
263 | --- AHB RAM ---------------------------------------------------------- | |
264 | --ahbram0 : ahbram |
|
264 | --ahbram0 : ahbram | |
265 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) |
|
265 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) | |
266 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); |
|
266 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); | |
267 | --ahbram1 : ahbram |
|
267 | --ahbram1 : ahbram | |
268 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) |
|
268 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) | |
269 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); |
|
269 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); | |
270 | --ahbram2 : ahbram |
|
270 | --ahbram2 : ahbram | |
271 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) |
|
271 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) | |
272 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); |
|
272 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); | |
273 | --ahbram3 : ahbram |
|
273 | --ahbram3 : ahbram | |
274 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) |
|
274 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) | |
275 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); |
|
275 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); | |
276 |
|
276 | |||
277 | ----------------------------------------------------------------------------- |
|
277 | ----------------------------------------------------------------------------- | |
278 | ---------------------------------------------------------------------- |
|
278 | ---------------------------------------------------------------------- | |
279 | --- Memory controllers --------------------------------------------- |
|
279 | --- Memory controllers --------------------------------------------- | |
280 | ---------------------------------------------------------------------- |
|
280 | ---------------------------------------------------------------------- | |
281 | memctrlr : mctrl GENERIC MAP ( |
|
281 | memctrlr : mctrl GENERIC MAP ( | |
282 | hindex => 0, |
|
282 | hindex => 0, | |
283 | pindex => 0, |
|
283 | pindex => 0, | |
284 | paddr => 0, |
|
284 | paddr => 0, | |
285 | srbanks => 1 |
|
285 | srbanks => 1 | |
286 | ) |
|
286 | ) | |
287 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
287 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
288 |
|
288 | |||
289 | memi.brdyn <= '1'; |
|
289 | memi.brdyn <= '1'; | |
290 | memi.bexcn <= '1'; |
|
290 | memi.bexcn <= '1'; | |
291 | memi.writen <= '1'; |
|
291 | memi.writen <= '1'; | |
292 | memi.wrn <= "1111"; |
|
292 | memi.wrn <= "1111"; | |
293 | memi.bwidth <= "10"; |
|
293 | memi.bwidth <= "10"; | |
294 |
|
294 | |||
295 | bdr : FOR i IN 0 TO 3 GENERATE |
|
295 | bdr : FOR i IN 0 TO 3 GENERATE | |
296 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
296 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
297 | PORT MAP ( |
|
297 | PORT MAP ( | |
298 | data(31-i*8 DOWNTO 24-i*8), |
|
298 | data(31-i*8 DOWNTO 24-i*8), | |
299 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
299 | memo.data(31-i*8 DOWNTO 24-i*8), | |
300 | memo.bdrive(i), |
|
300 | memo.bdrive(i), | |
301 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
301 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
302 | END GENERATE; |
|
302 | END GENERATE; | |
303 |
|
303 | |||
304 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
304 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
305 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
305 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
306 |
|
306 | |||
307 | not_ramsn_0 <= NOT(memo.ramsn(0)); |
|
307 | not_ramsn_0 <= NOT(memo.ramsn(0)); | |
308 |
|
308 | |||
309 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); |
|
309 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); | |
310 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
310 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
311 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
311 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
312 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
312 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
313 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
313 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
314 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
314 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
315 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
315 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
316 |
|
316 | |||
317 | async_1Mx16_0: CY7C1061DV33 |
|
317 | async_1Mx16_0: CY7C1061DV33 | |
318 | GENERIC MAP ( |
|
318 | GENERIC MAP ( | |
319 | ADDR_BITS => 20, |
|
319 | ADDR_BITS => 20, | |
320 | DATA_BITS => 16, |
|
320 | DATA_BITS => 16, | |
321 | depth => 1048576, |
|
321 | depth => 1048576, | |
322 | TimingInfo => TRUE, |
|
322 | TimingInfo => TRUE, | |
323 | TimingChecks => '1') |
|
323 | TimingChecks => '1') | |
324 | PORT MAP ( |
|
324 | PORT MAP ( | |
325 | CE1_b => '0', |
|
325 | CE1_b => '0', | |
326 | CE2 => nSRAM_CE, |
|
326 | CE2 => nSRAM_CE, | |
327 | WE_b => nSRAM_WE, |
|
327 | WE_b => nSRAM_WE, | |
328 | OE_b => nSRAM_OE, |
|
328 | OE_b => nSRAM_OE, | |
329 | BHE_b => nSRAM_BE1, |
|
329 | BHE_b => nSRAM_BE1, | |
330 | BLE_b => nSRAM_BE0, |
|
330 | BLE_b => nSRAM_BE0, | |
331 | A => address, |
|
331 | A => address, | |
332 | DQ => data(15 DOWNTO 0)); |
|
332 | DQ => data(15 DOWNTO 0)); | |
333 |
|
333 | |||
334 | async_1Mx16_1: CY7C1061DV33 |
|
334 | async_1Mx16_1: CY7C1061DV33 | |
335 | GENERIC MAP ( |
|
335 | GENERIC MAP ( | |
336 | ADDR_BITS => 20, |
|
336 | ADDR_BITS => 20, | |
337 | DATA_BITS => 16, |
|
337 | DATA_BITS => 16, | |
338 | depth => 1048576, |
|
338 | depth => 1048576, | |
339 | TimingInfo => TRUE, |
|
339 | TimingInfo => TRUE, | |
340 | TimingChecks => '1') |
|
340 | TimingChecks => '1') | |
341 | PORT MAP ( |
|
341 | PORT MAP ( | |
342 | CE1_b => '0', |
|
342 | CE1_b => '0', | |
343 | CE2 => nSRAM_CE, |
|
343 | CE2 => nSRAM_CE, | |
344 | WE_b => nSRAM_WE, |
|
344 | WE_b => nSRAM_WE, | |
345 | OE_b => nSRAM_OE, |
|
345 | OE_b => nSRAM_OE, | |
346 | BHE_b => nSRAM_BE3, |
|
346 | BHE_b => nSRAM_BE3, | |
347 | BLE_b => nSRAM_BE2, |
|
347 | BLE_b => nSRAM_BE2, | |
348 | A => address, |
|
348 | A => address, | |
349 | DQ => data(31 DOWNTO 16)); |
|
349 | DQ => data(31 DOWNTO 16)); | |
350 |
|
350 | |||
351 |
|
351 | |||
352 | ----------------------------------------------------------------------------- |
|
352 | ----------------------------------------------------------------------------- | |
353 |
|
353 | |||
354 | WaveGen_Proc : PROCESS |
|
354 | WaveGen_Proc : PROCESS | |
355 | BEGIN |
|
355 | BEGIN | |
356 |
|
356 | |||
357 | -- insert signal assignments here |
|
357 | -- insert signal assignments here | |
358 | WAIT UNTIL clk25MHz = '1'; |
|
358 | WAIT UNTIL clk25MHz = '1'; | |
359 | rstn <= '0'; |
|
359 | rstn <= '0'; | |
360 | apbi.psel(15) <= '0'; |
|
360 | apbi.psel(15) <= '0'; | |
361 | apbi.pwrite <= '0'; |
|
361 | apbi.pwrite <= '0'; | |
362 | apbi.penable <= '0'; |
|
362 | apbi.penable <= '0'; | |
363 | apbi.paddr <= (OTHERS => '0'); |
|
363 | apbi.paddr <= (OTHERS => '0'); | |
364 | apbi.pwdata <= (OTHERS => '0'); |
|
364 | apbi.pwdata <= (OTHERS => '0'); | |
365 | fine_time <= (OTHERS => '0'); |
|
365 | fine_time <= (OTHERS => '0'); | |
366 | coarse_time <= (OTHERS => '0'); |
|
366 | coarse_time <= (OTHERS => '0'); | |
367 | WAIT UNTIL clk25MHz = '1'; |
|
367 | WAIT UNTIL clk25MHz = '1'; | |
368 | -- ahbmi.HGRANT(2) <= '1'; |
|
368 | -- ahbmi.HGRANT(2) <= '1'; | |
369 | -- ahbmi.HREADY <= '1'; |
|
369 | -- ahbmi.HREADY <= '1'; | |
370 | -- ahbmi.HRESP <= HRESP_OKAY; |
|
370 | -- ahbmi.HRESP <= HRESP_OKAY; | |
371 |
|
371 | |||
372 | WAIT UNTIL clk25MHz = '1'; |
|
372 | WAIT UNTIL clk25MHz = '1'; | |
373 | WAIT UNTIL clk25MHz = '1'; |
|
373 | WAIT UNTIL clk25MHz = '1'; | |
374 | rstn <= '1'; |
|
374 | rstn <= '1'; | |
375 | WAIT UNTIL clk25MHz = '1'; |
|
375 | WAIT UNTIL clk25MHz = '1'; | |
376 | WAIT UNTIL clk25MHz = '1'; |
|
376 | WAIT UNTIL clk25MHz = '1'; | |
377 | --------------------------------------------------------------------------- |
|
377 | --------------------------------------------------------------------------- | |
378 | -- CONFIGURATION STEP |
|
378 | -- CONFIGURATION STEP | |
379 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); |
|
379 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); | |
380 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40 |
|
380 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); | |
381 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40 |
|
381 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); | |
382 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40 |
|
382 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); | |
383 |
|
383 | |||
384 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"000000 |
|
384 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020" | |
385 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"000000 |
|
385 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019" | |
386 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"0000000 |
|
386 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" | |
387 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"000000 |
|
387 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019" | |
388 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" |
|
388 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" | |
389 |
|
389 | |||
390 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" |
|
390 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" | |
391 | -- |
|
391 | -- | |
392 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); |
|
392 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); | |
393 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); |
|
393 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); | |
394 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); |
|
394 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); | |
395 |
|
395 | |||
396 |
|
396 | |||
397 | WAIT UNTIL clk25MHz = '1'; |
|
397 | WAIT UNTIL clk25MHz = '1'; | |
398 | WAIT UNTIL clk25MHz = '1'; |
|
398 | WAIT UNTIL clk25MHz = '1'; | |
399 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"0000008 |
|
399 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); | |
400 | WAIT UNTIL clk25MHz = '1'; |
|
400 | WAIT UNTIL clk25MHz = '1'; | |
401 | WAIT UNTIL clk25MHz = '1'; |
|
401 | WAIT UNTIL clk25MHz = '1'; | |
402 | WAIT UNTIL clk25MHz = '1'; |
|
402 | WAIT UNTIL clk25MHz = '1'; | |
403 | WAIT UNTIL clk25MHz = '1'; |
|
403 | WAIT UNTIL clk25MHz = '1'; | |
404 | WAIT UNTIL clk25MHz = '1'; |
|
404 | WAIT UNTIL clk25MHz = '1'; | |
405 | WAIT UNTIL clk25MHz = '1'; |
|
405 | WAIT UNTIL clk25MHz = '1'; | |
406 | WAIT FOR 1 us; |
|
406 | WAIT FOR 1 us; | |
407 | coarse_time <= X"00000001"; |
|
407 | coarse_time <= X"00000001"; | |
408 | --------------------------------------------------------------------------- |
|
408 | --------------------------------------------------------------------------- | |
409 | -- RUN STEP |
|
409 | -- RUN STEP | |
410 | WAIT FOR 200 ms; |
|
410 | WAIT FOR 200 ms; | |
411 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
411 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
412 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); |
|
412 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); | |
413 | WAIT FOR 10 us; |
|
413 | WAIT FOR 10 us; | |
414 | WAIT UNTIL clk25MHz = '1'; |
|
414 | WAIT UNTIL clk25MHz = '1'; | |
415 | WAIT UNTIL clk25MHz = '1'; |
|
415 | WAIT UNTIL clk25MHz = '1'; | |
416 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); |
|
416 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); | |
417 | WAIT UNTIL clk25MHz = '1'; |
|
417 | WAIT UNTIL clk25MHz = '1'; | |
418 | coarse_time <= X"00000010"; |
|
418 | coarse_time <= X"00000010"; | |
419 | WAIT FOR 100 ms; |
|
419 | WAIT FOR 100 ms; | |
420 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
420 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
421 | WAIT FOR 10 us; |
|
421 | WAIT FOR 10 us; | |
422 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); |
|
422 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); | |
423 | WAIT FOR 200 ms; |
|
423 | WAIT FOR 200 ms; | |
424 | REPORT "*** END simulation ***" SEVERITY failure; |
|
424 | REPORT "*** END simulation ***" SEVERITY failure; | |
425 |
|
425 | |||
426 |
|
426 | |||
427 | WAIT; |
|
427 | WAIT; | |
428 |
|
428 | |||
429 | END PROCESS WaveGen_Proc; |
|
429 | END PROCESS WaveGen_Proc; | |
430 | ----------------------------------------------------------------------------- |
|
430 | ----------------------------------------------------------------------------- | |
431 |
|
431 | |||
432 | ----------------------------------------------------------------------------- |
|
432 | ----------------------------------------------------------------------------- | |
433 | -- IRQ |
|
433 | -- IRQ | |
434 | ----------------------------------------------------------------------------- |
|
434 | ----------------------------------------------------------------------------- | |
435 | PROCESS (clk25MHz, rstn) |
|
435 | PROCESS (clk25MHz, rstn) | |
436 | BEGIN -- PROCESS |
|
436 | BEGIN -- PROCESS | |
437 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
437 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
438 |
|
438 | |||
439 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
439 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge | |
440 |
|
440 | |||
441 | END IF; |
|
441 | END IF; | |
442 | END PROCESS; |
|
442 | END PROCESS; | |
443 | ----------------------------------------------------------------------------- |
|
443 | ----------------------------------------------------------------------------- | |
444 |
|
444 | |||
445 | END; |
|
445 | END; |
@@ -1,658 +1,662 | |||||
1 | --************************************************************************ |
|
1 | --************************************************************************ | |
2 | --** MODEL : async_1Mx16.vhd ** |
|
2 | --** MODEL : async_1Mx16.vhd ** | |
3 | --** COMPANY : Cypress Semiconductor ** |
|
3 | --** COMPANY : Cypress Semiconductor ** | |
4 | --** REVISION: 1.0 Created new base model ** |
|
4 | --** REVISION: 1.0 Created new base model ** | |
5 | --************************************************************************ |
|
5 | --************************************************************************ | |
6 |
|
6 | |||
7 | -------------------------------------------------------------------------------JC\/ |
|
7 | -------------------------------------------------------------------------------JC\/ | |
8 | --Library ieee,work; |
|
8 | --Library ieee,work; | |
9 | LIBRARY ieee; |
|
9 | LIBRARY ieee; | |
10 | -------------------------------------------------------------------------------JC/\ |
|
10 | -------------------------------------------------------------------------------JC/\ | |
11 | USE IEEE.Std_Logic_1164.ALL; |
|
11 | USE IEEE.Std_Logic_1164.ALL; | |
12 | USE IEEE.Std_Logic_unsigned.ALL; |
|
12 | USE IEEE.Std_Logic_unsigned.ALL; | |
13 |
|
13 | |||
14 | -------------------------------------------------------------------------------JC\/ |
|
14 | -------------------------------------------------------------------------------JC\/ | |
15 | --use work.package_timing.all; |
|
15 | --use work.package_timing.all; | |
16 | --use work.package_utility.all; |
|
16 | --use work.package_utility.all; | |
17 | LIBRARY lpp; |
|
17 | LIBRARY lpp; | |
18 | USE lpp.package_timing.ALL; |
|
18 | USE lpp.package_timing.ALL; | |
19 | USE lpp.package_utility.ALL; |
|
19 | USE lpp.package_utility.ALL; | |
20 | -------------------------------------------------------------------------------JC/\ |
|
20 | -------------------------------------------------------------------------------JC/\ | |
21 |
|
21 | |||
22 | ------------------------ |
|
22 | ------------------------ | |
23 | -- Entity Description |
|
23 | -- Entity Description | |
24 | ------------------------ |
|
24 | ------------------------ | |
25 |
|
25 | |||
26 | ENTITY CY7C1061DV33 IS |
|
26 | ENTITY CY7C1061DV33 IS | |
27 | GENERIC |
|
27 | GENERIC | |
28 | (ADDR_BITS : INTEGER := 20; |
|
28 | (ADDR_BITS : INTEGER := 20; | |
29 | DATA_BITS : INTEGER := 16; |
|
29 | DATA_BITS : INTEGER := 16; | |
30 | depth : INTEGER := 1048576; |
|
30 | depth : INTEGER := 1048576; | |
31 |
|
31 | |||
32 | TimingInfo : BOOLEAN := true; |
|
32 | TimingInfo : BOOLEAN := true; | |
33 | TimingChecks : STD_LOGIC := '1' |
|
33 | TimingChecks : STD_LOGIC := '1' | |
34 | ); |
|
34 | ); | |
35 | PORT ( |
|
35 | PORT ( | |
36 | CE1_b : IN STD_LOGIC; -- Chip Enable CE1# |
|
36 | CE1_b : IN STD_LOGIC; -- Chip Enable CE1# | |
37 | CE2 : IN STD_LOGIC; -- Chip Enable CE2 |
|
37 | CE2 : IN STD_LOGIC; -- Chip Enable CE2 | |
38 | WE_b : IN STD_LOGIC; -- Write Enable WE# |
|
38 | WE_b : IN STD_LOGIC; -- Write Enable WE# | |
39 | OE_b : IN STD_LOGIC; -- Output Enable OE# |
|
39 | OE_b : IN STD_LOGIC; -- Output Enable OE# | |
40 | BHE_b : IN STD_LOGIC; -- Byte Enable High BHE# |
|
40 | BHE_b : IN STD_LOGIC; -- Byte Enable High BHE# | |
41 | BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE# |
|
41 | BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE# | |
42 | A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A |
|
42 | A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A | |
43 | DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO; |
|
43 | DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO; | |
44 | ); |
|
44 | ); | |
45 | END CY7C1061DV33; |
|
45 | END CY7C1061DV33; | |
46 |
|
46 | |||
47 | ----------------------------- |
|
47 | ----------------------------- | |
48 | -- End Entity Description |
|
48 | -- End Entity Description | |
49 | ----------------------------- |
|
49 | ----------------------------- | |
50 | ----------------------------- |
|
50 | ----------------------------- | |
51 | -- Architecture Description |
|
51 | -- Architecture Description | |
52 | ----------------------------- |
|
52 | ----------------------------- | |
53 |
|
53 | |||
54 | ARCHITECTURE behave_arch OF CY7C1061DV33 IS |
|
54 | ARCHITECTURE behave_arch OF CY7C1061DV33 IS | |
55 |
|
55 | |||
56 | TYPE mem_array_type IS ARRAY (depth-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); |
|
56 | TYPE mem_array_type IS ARRAY (depth-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); | |
57 |
|
57 | |||
58 | SIGNAL write_enable : STD_LOGIC; |
|
58 | SIGNAL write_enable : STD_LOGIC; | |
59 | SIGNAL read_enable : STD_LOGIC; |
|
59 | SIGNAL read_enable : STD_LOGIC; | |
60 | SIGNAL byte_enable : STD_LOGIC; |
|
60 | SIGNAL byte_enable : STD_LOGIC; | |
61 | SIGNAL CE_b : STD_LOGIC; |
|
61 | SIGNAL CE_b : STD_LOGIC; | |
62 |
|
62 | |||
63 | SIGNAL data_skew : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); |
|
63 | SIGNAL data_skew : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); | |
64 |
|
64 | |||
65 | SIGNAL address_internal, address_skew : STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); |
|
65 | SIGNAL address_internal, address_skew : STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); | |
66 |
|
66 | |||
67 | CONSTANT tSD_dataskew : TIME := tSD - 1 ns; |
|
67 | CONSTANT tSD_dataskew : TIME := tSD - 1 ns; | |
68 | CONSTANT tskew : TIME := 1 ns; |
|
68 | CONSTANT tskew : TIME := 1 ns; | |
69 |
|
69 | |||
70 | -------------------------------------------------------------------------------JC\/ |
|
70 | -------------------------------------------------------------------------------JC\/ | |
71 |
TYPE mem_array_type_t IS ARRAY (1 |
|
71 | TYPE mem_array_type_t IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); | |
72 |
SIGNAL mem_array_ |
|
72 | SIGNAL mem_array_0 : mem_array_type_t; | |
|
73 | SIGNAL mem_array_1 : mem_array_type_t; | |||
|
74 | SIGNAL mem_array_2 : mem_array_type_t; | |||
|
75 | SIGNAL mem_array_3 : mem_array_type_t; | |||
73 | -------------------------------------------------------------------------------JC/\ |
|
76 | -------------------------------------------------------------------------------JC/\ | |
74 |
|
77 | |||
75 |
|
78 | |||
76 |
|
79 | |||
77 | BEGIN |
|
80 | BEGIN | |
78 | CE_b <= CE1_b OR NOT(CE2); |
|
81 | CE_b <= CE1_b OR NOT(CE2); | |
79 | byte_enable <= NOT(BHE_b AND BLE_b); |
|
82 | byte_enable <= NOT(BHE_b AND BLE_b); | |
80 | write_enable <= NOT(CE1_b) AND CE2 AND NOT(WE_b) AND NOT(BHE_b AND BLE_b); |
|
83 | write_enable <= NOT(CE1_b) AND CE2 AND NOT(WE_b) AND NOT(BHE_b AND BLE_b); | |
81 | read_enable <= NOT(CE1_b) AND CE2 AND (WE_b) AND NOT(OE_b) AND NOT(BHE_b AND BLE_b); |
|
84 | read_enable <= NOT(CE1_b) AND CE2 AND (WE_b) AND NOT(OE_b) AND NOT(BHE_b AND BLE_b); | |
82 |
|
85 | |||
83 | data_skew <= DQ AFTER 1 ns; -- changed on feb 15 |
|
86 | data_skew <= DQ AFTER 1 ns; -- changed on feb 15 | |
84 | address_skew <= A AFTER 1 ns; |
|
87 | address_skew <= A AFTER 1 ns; | |
85 |
|
88 | |||
86 | PROCESS (OE_b) |
|
89 | PROCESS (OE_b) | |
87 | BEGIN |
|
90 | BEGIN | |
88 | IF (OE_b'EVENT AND OE_b = '1' AND write_enable /= '1') THEN |
|
91 | IF (OE_b'EVENT AND OE_b = '1' AND write_enable /= '1') THEN | |
89 | DQ <= (OTHERS => 'Z') after tHZOE; |
|
92 | DQ <= (OTHERS => 'Z') after tHZOE; | |
90 | END IF; |
|
93 | END IF; | |
91 | END PROCESS; |
|
94 | END PROCESS; | |
92 |
|
95 | |||
93 | PROCESS (CE_b) |
|
96 | PROCESS (CE_b) | |
94 | BEGIN |
|
97 | BEGIN | |
95 | IF (CE_b'EVENT AND CE_b = '1') THEN |
|
98 | IF (CE_b'EVENT AND CE_b = '1') THEN | |
96 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
99 | DQ <= (OTHERS => 'Z') after tHZCE; | |
97 | END IF; |
|
100 | END IF; | |
98 | END PROCESS; |
|
101 | END PROCESS; | |
99 |
|
102 | |||
100 | PROCESS (write_enable'DELAYED(tHA)) |
|
103 | PROCESS (write_enable'DELAYED(tHA)) | |
101 | BEGIN |
|
104 | BEGIN | |
102 | IF (write_enable'DELAYED(tHA) = '0' AND TimingInfo) THEN |
|
105 | IF (write_enable'DELAYED(tHA) = '0' AND TimingInfo) THEN | |
103 | ASSERT (A'LAST_EVENT = 0 ns) OR (A'LAST_EVENT > tHA) |
|
106 | ASSERT (A'LAST_EVENT = 0 ns) OR (A'LAST_EVENT > tHA) | |
104 | REPORT "Address hold time tHA violated"; |
|
107 | REPORT "Address hold time tHA violated"; | |
105 | END IF; |
|
108 | END IF; | |
106 | END PROCESS; |
|
109 | END PROCESS; | |
107 |
|
110 | |||
108 | PROCESS (write_enable'DELAYED(tHD)) |
|
111 | PROCESS (write_enable'DELAYED(tHD)) | |
109 | BEGIN |
|
112 | BEGIN | |
110 | IF (write_enable'DELAYED(tHD) = '0' AND TimingInfo) THEN |
|
113 | IF (write_enable'DELAYED(tHD) = '0' AND TimingInfo) THEN | |
111 | ASSERT (DQ'LAST_EVENT > tHD) OR (DQ'LAST_EVENT = 0 ns) |
|
114 | ASSERT (DQ'LAST_EVENT > tHD) OR (DQ'LAST_EVENT = 0 ns) | |
112 | REPORT "Data hold time tHD violated"; |
|
115 | REPORT "Data hold time tHD violated"; | |
113 | END IF; |
|
116 | END IF; | |
114 | END PROCESS; |
|
117 | END PROCESS; | |
115 |
|
118 | |||
116 | -- main process |
|
119 | -- main process | |
117 | PROCESS |
|
120 | PROCESS | |
118 |
|
121 | |||
119 | VARIABLE mem_array : mem_array_type; |
|
122 | VARIABLE mem_array : mem_array_type; | |
120 |
|
123 | |||
121 | --- Variables for timing checks |
|
124 | --- Variables for timing checks | |
122 | VARIABLE tPWE_chk : TIME := -10 ns; |
|
125 | VARIABLE tPWE_chk : TIME := -10 ns; | |
123 | VARIABLE tAW_chk : TIME := -10 ns; |
|
126 | VARIABLE tAW_chk : TIME := -10 ns; | |
124 | VARIABLE tSD_chk : TIME := -10 ns; |
|
127 | VARIABLE tSD_chk : TIME := -10 ns; | |
125 | VARIABLE tRC_chk : TIME := 0 ns; |
|
128 | VARIABLE tRC_chk : TIME := 0 ns; | |
126 | VARIABLE tBAW_chk : TIME := 0 ns; |
|
129 | VARIABLE tBAW_chk : TIME := 0 ns; | |
127 | VARIABLE tBBW_chk : TIME := 0 ns; |
|
130 | VARIABLE tBBW_chk : TIME := 0 ns; | |
128 | VARIABLE tBCW_chk : TIME := 0 ns; |
|
131 | VARIABLE tBCW_chk : TIME := 0 ns; | |
129 | VARIABLE tBDW_chk : TIME := 0 ns; |
|
132 | VARIABLE tBDW_chk : TIME := 0 ns; | |
130 | VARIABLE tSA_chk : TIME := 0 ns; |
|
133 | VARIABLE tSA_chk : TIME := 0 ns; | |
131 | VARIABLE tSA_skew : TIME := 0 ns; |
|
134 | VARIABLE tSA_skew : TIME := 0 ns; | |
132 | VARIABLE tAint_chk : TIME := -10 ns; |
|
135 | VARIABLE tAint_chk : TIME := -10 ns; | |
133 |
|
136 | |||
134 | VARIABLE write_flag : BOOLEAN := true; |
|
137 | VARIABLE write_flag : BOOLEAN := true; | |
135 |
|
138 | |||
136 | VARIABLE accesstime : TIME := 0 ns; |
|
139 | VARIABLE accesstime : TIME := 0 ns; | |
137 |
|
140 | |||
138 | BEGIN |
|
141 | BEGIN | |
139 | IF (address_skew'EVENT) THEN |
|
142 | IF (address_skew'EVENT) THEN | |
140 | tSA_skew := NOW; |
|
143 | tSA_skew := NOW; | |
141 | END IF; |
|
144 | END IF; | |
142 |
|
145 | |||
143 | -- start of write |
|
146 | -- start of write | |
144 | IF (write_enable = '1' AND write_enable'EVENT) THEN |
|
147 | IF (write_enable = '1' AND write_enable'EVENT) THEN | |
145 |
|
148 | |||
146 | DQ(DATA_BITS-1 DOWNTO 0) <= (OTHERS => 'Z') after tHZWE; |
|
149 | DQ(DATA_BITS-1 DOWNTO 0) <= (OTHERS => 'Z') after tHZWE; | |
147 |
|
150 | |||
148 | IF (A'LAST_EVENT >= tSA) THEN |
|
151 | IF (A'LAST_EVENT >= tSA) THEN | |
149 | address_internal <= A; |
|
152 | address_internal <= A; | |
150 | tPWE_chk := NOW; |
|
153 | tPWE_chk := NOW; | |
151 | tAW_chk := A'LAST_EVENT; |
|
154 | tAW_chk := A'LAST_EVENT; | |
152 | tAint_chk := NOW; |
|
155 | tAint_chk := NOW; | |
153 | write_flag := true; |
|
156 | write_flag := true; | |
154 |
|
157 | |||
155 | ELSE |
|
158 | ELSE | |
156 | IF (TimingInfo) THEN |
|
159 | IF (TimingInfo) THEN | |
157 | ASSERT false |
|
160 | ASSERT false | |
158 | REPORT "Address setup violated"; |
|
161 | REPORT "Address setup violated"; | |
159 | END IF; |
|
162 | END IF; | |
160 | write_flag := false; |
|
163 | write_flag := false; | |
161 |
|
164 | |||
162 | END IF; |
|
165 | END IF; | |
163 |
|
166 | |||
164 | -- end of write (with CE high or WE high) |
|
167 | -- end of write (with CE high or WE high) | |
165 | ELSIF (write_enable = '0' AND write_enable'EVENT) THEN |
|
168 | ELSIF (write_enable = '0' AND write_enable'EVENT) THEN | |
166 |
|
169 | |||
167 | --- check for pulse width |
|
170 | --- check for pulse width | |
168 | IF (NOW - tPWE_chk >= tPWE OR NOW - tPWE_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
171 | IF (NOW - tPWE_chk >= tPWE OR NOW - tPWE_chk <= 0.1 ns OR NOW = 0 ns) THEN | |
169 | --- pulse width OK, do nothing |
|
172 | --- pulse width OK, do nothing | |
170 | ELSE |
|
173 | ELSE | |
171 | IF (TimingInfo) THEN |
|
174 | IF (TimingInfo) THEN | |
172 | ASSERT false |
|
175 | ASSERT false | |
173 | REPORT "Pulse Width violation"; |
|
176 | REPORT "Pulse Width violation"; | |
174 | END IF; |
|
177 | END IF; | |
175 |
|
178 | |||
176 | write_flag := false; |
|
179 | write_flag := false; | |
177 | END IF; |
|
180 | END IF; | |
178 |
|
181 | |||
179 |
|
182 | |||
180 | IF (NOW > 0 ns) THEN |
|
183 | IF (NOW > 0 ns) THEN | |
181 | IF (tSA_skew - tAint_chk > tskew) THEN |
|
184 | IF (tSA_skew - tAint_chk > tskew) THEN | |
182 | ASSERT false |
|
185 | ASSERT false | |
183 | REPORT "Negative address setup"; |
|
186 | REPORT "Negative address setup"; | |
184 | write_flag := false; |
|
187 | write_flag := false; | |
185 | END IF; |
|
188 | END IF; | |
186 | END IF; |
|
189 | END IF; | |
187 |
|
190 | |||
188 | --- check for address setup with write end, i.e., tAW |
|
191 | --- check for address setup with write end, i.e., tAW | |
189 | IF (NOW - tAW_chk >= tAW OR NOW = 0 ns) THEN |
|
192 | IF (NOW - tAW_chk >= tAW OR NOW = 0 ns) THEN | |
190 | --- tAW OK, do nothing |
|
193 | --- tAW OK, do nothing | |
191 | ELSE |
|
194 | ELSE | |
192 | IF (TimingInfo) THEN |
|
195 | IF (TimingInfo) THEN | |
193 | ASSERT false |
|
196 | ASSERT false | |
194 | REPORT "Address setup tAW violation"; |
|
197 | REPORT "Address setup tAW violation"; | |
195 | END IF; |
|
198 | END IF; | |
196 |
|
199 | |||
197 | write_flag := false; |
|
200 | write_flag := false; | |
198 | END IF; |
|
201 | END IF; | |
199 |
|
202 | |||
200 | --- check for data setup with write end, i.e., tSD |
|
203 | --- check for data setup with write end, i.e., tSD | |
201 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
204 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN | |
202 | --- tSD OK, do nothing |
|
205 | --- tSD OK, do nothing | |
203 | ELSE |
|
206 | ELSE | |
204 | IF (TimingInfo) THEN |
|
207 | IF (TimingInfo) THEN | |
205 | ASSERT false |
|
208 | ASSERT false | |
206 | REPORT "Data setup tSD violation"; |
|
209 | REPORT "Data setup tSD violation"; | |
207 | END IF; |
|
210 | END IF; | |
208 | write_flag := false; |
|
211 | write_flag := false; | |
209 | END IF; |
|
212 | END IF; | |
210 |
|
213 | |||
211 | -- perform write operation if no violations |
|
214 | -- perform write operation if no violations | |
212 | IF (write_flag = true) THEN |
|
215 | IF (write_flag = true) THEN | |
213 |
|
216 | |||
214 | IF (BLE_b = '1' AND BLE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN |
|
217 | IF (BLE_b = '1' AND BLE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN | |
215 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
218 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); | |
216 | END IF; |
|
219 | END IF; | |
217 |
|
220 | |||
218 | IF (BHE_b = '1' AND BHE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN |
|
221 | IF (BHE_b = '1' AND BHE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN | |
219 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
222 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); | |
220 | END IF; |
|
223 | END IF; | |
221 |
|
224 | |||
222 | IF (BLE_b = '0' AND NOW - tBAW_chk >= tBW) THEN |
|
225 | IF (BLE_b = '0' AND NOW - tBAW_chk >= tBW) THEN | |
223 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
226 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); | |
224 | ELSIF (NOW - tBAW_chk < tBW AND NOW - tBAW_chk > 0.1 ns AND NOW > 0 ns) THEN |
|
227 | ELSIF (NOW - tBAW_chk < tBW AND NOW - tBAW_chk > 0.1 ns AND NOW > 0 ns) THEN | |
225 | ASSERT false REPORT "Insufficient pulse width for lower byte to be written"; |
|
228 | ASSERT false REPORT "Insufficient pulse width for lower byte to be written"; | |
226 | END IF; |
|
229 | END IF; | |
227 |
|
230 | |||
228 | IF (BHE_b = '0' AND NOW - tBBW_chk >= tBW) THEN |
|
231 | IF (BHE_b = '0' AND NOW - tBBW_chk >= tBW) THEN | |
229 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
232 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); | |
230 | ELSIF (NOW - tBBW_chk < tBW AND NOW - tBBW_chk > 0.1 ns AND NOW > 0 ns) THEN |
|
233 | ELSIF (NOW - tBBW_chk < tBW AND NOW - tBBW_chk > 0.1 ns AND NOW > 0 ns) THEN | |
231 | ASSERT false REPORT "Insufficient pulse width for higher byte to be written"; |
|
234 | ASSERT false REPORT "Insufficient pulse width for higher byte to be written"; | |
232 | END IF; |
|
235 | END IF; | |
233 |
|
236 | |||
234 |
|
237 | |||
235 | -------------------------------------------------------------------------------JC\/ |
|
238 | -------------------------------------------------------------------------------JC\/ | |
236 |
all_mem_array_obs: FOR I IN 0 TO 1 |
|
239 | all_mem_array_obs: FOR I IN 0 TO 31 LOOP | |
237 | IF I < depth THEN |
|
240 | IF I + ((2**15) *0) < depth THEN mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF; | |
238 |
mem_array_ |
|
241 | IF I + ((2**15) *1) < depth THEN mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF; | |
239 | END IF; |
|
242 | IF I + ((2**15) *2) < depth THEN mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF; | |
|
243 | IF I + ((2**15) *3) < depth THEN mem_array_3(I) <= mem_array(I+((2**15) *3)); END IF; | |||
240 | END LOOP all_mem_array_obs; |
|
244 | END LOOP all_mem_array_obs; | |
241 | -------------------------------------------------------------------------------JC/\ |
|
245 | -------------------------------------------------------------------------------JC/\ | |
242 |
|
246 | |||
243 | END IF; |
|
247 | END IF; | |
244 |
|
248 | |||
245 | -- end of write (with BLE high) |
|
249 | -- end of write (with BLE high) | |
246 | ELSIF (BLE_b'EVENT AND NOT(BHE_b'EVENT) AND write_enable = '1') THEN |
|
250 | ELSIF (BLE_b'EVENT AND NOT(BHE_b'EVENT) AND write_enable = '1') THEN | |
247 |
|
251 | |||
248 | IF (BLE_b = '0') THEN |
|
252 | IF (BLE_b = '0') THEN | |
249 |
|
253 | |||
250 | --- Reset timing variables |
|
254 | --- Reset timing variables | |
251 | tAW_chk := A'LAST_EVENT; |
|
255 | tAW_chk := A'LAST_EVENT; | |
252 | tBAW_chk := NOW; |
|
256 | tBAW_chk := NOW; | |
253 | write_flag := true; |
|
257 | write_flag := true; | |
254 |
|
258 | |||
255 | ELSIF (BLE_b = '1') THEN |
|
259 | ELSIF (BLE_b = '1') THEN | |
256 |
|
260 | |||
257 | --- check for pulse width |
|
261 | --- check for pulse width | |
258 | IF (NOW - tPWE_chk >= tPWE) THEN |
|
262 | IF (NOW - tPWE_chk >= tPWE) THEN | |
259 | --- tPWE OK, do nothing |
|
263 | --- tPWE OK, do nothing | |
260 | ELSE |
|
264 | ELSE | |
261 | IF (TimingInfo) THEN |
|
265 | IF (TimingInfo) THEN | |
262 | ASSERT false |
|
266 | ASSERT false | |
263 | REPORT "Pulse Width violation"; |
|
267 | REPORT "Pulse Width violation"; | |
264 | END IF; |
|
268 | END IF; | |
265 |
|
269 | |||
266 | write_flag := false; |
|
270 | write_flag := false; | |
267 | END IF; |
|
271 | END IF; | |
268 |
|
272 | |||
269 | --- check for address setup with write end, i.e., tAW |
|
273 | --- check for address setup with write end, i.e., tAW | |
270 | IF (NOW - tAW_chk >= tAW) THEN |
|
274 | IF (NOW - tAW_chk >= tAW) THEN | |
271 | --- tAW OK, do nothing |
|
275 | --- tAW OK, do nothing | |
272 | ELSE |
|
276 | ELSE | |
273 | IF (TimingInfo) THEN |
|
277 | IF (TimingInfo) THEN | |
274 | ASSERT false |
|
278 | ASSERT false | |
275 | REPORT "Address setup tAW violation for Lower Byte Write"; |
|
279 | REPORT "Address setup tAW violation for Lower Byte Write"; | |
276 | END IF; |
|
280 | END IF; | |
277 |
|
281 | |||
278 | write_flag := false; |
|
282 | write_flag := false; | |
279 | END IF; |
|
283 | END IF; | |
280 |
|
284 | |||
281 | --- check for byte write setup with write end, i.e., tBW |
|
285 | --- check for byte write setup with write end, i.e., tBW | |
282 | IF (NOW - tBAW_chk >= tBW) THEN |
|
286 | IF (NOW - tBAW_chk >= tBW) THEN | |
283 | --- tBW OK, do nothing |
|
287 | --- tBW OK, do nothing | |
284 | ELSE |
|
288 | ELSE | |
285 | IF (TimingInfo) THEN |
|
289 | IF (TimingInfo) THEN | |
286 | ASSERT false |
|
290 | ASSERT false | |
287 | REPORT "Lower Byte setup tBW violation"; |
|
291 | REPORT "Lower Byte setup tBW violation"; | |
288 | END IF; |
|
292 | END IF; | |
289 |
|
293 | |||
290 | write_flag := false; |
|
294 | write_flag := false; | |
291 | END IF; |
|
295 | END IF; | |
292 |
|
296 | |||
293 | --- check for data setup with write end, i.e., tSD |
|
297 | --- check for data setup with write end, i.e., tSD | |
294 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
298 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN | |
295 | --- tSD OK, do nothing |
|
299 | --- tSD OK, do nothing | |
296 | ELSE |
|
300 | ELSE | |
297 | IF (TimingInfo) THEN |
|
301 | IF (TimingInfo) THEN | |
298 | ASSERT false |
|
302 | ASSERT false | |
299 | REPORT "Data setup tSD violation for Lower Byte Write"; |
|
303 | REPORT "Data setup tSD violation for Lower Byte Write"; | |
300 | END IF; |
|
304 | END IF; | |
301 |
|
305 | |||
302 | write_flag := false; |
|
306 | write_flag := false; | |
303 | END IF; |
|
307 | END IF; | |
304 |
|
308 | |||
305 | --- perform WRITE operation if no violations |
|
309 | --- perform WRITE operation if no violations | |
306 | IF (write_flag = true) THEN |
|
310 | IF (write_flag = true) THEN | |
307 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
311 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); | |
308 | IF (BHE_b = '0') THEN |
|
312 | IF (BHE_b = '0') THEN | |
309 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
313 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); | |
310 | END IF; |
|
314 | END IF; | |
311 | END IF; |
|
315 | END IF; | |
312 |
|
316 | |||
313 | --- Reset timing variables |
|
317 | --- Reset timing variables | |
314 | tAW_chk := A'LAST_EVENT; |
|
318 | tAW_chk := A'LAST_EVENT; | |
315 | tBAW_chk := NOW; |
|
319 | tBAW_chk := NOW; | |
316 | write_flag := true; |
|
320 | write_flag := true; | |
317 |
|
321 | |||
318 | END IF; |
|
322 | END IF; | |
319 |
|
323 | |||
320 | -- end of write (with BHE high) |
|
324 | -- end of write (with BHE high) | |
321 | ELSIF (BHE_b'EVENT AND NOT(BLE_b'EVENT) AND write_enable = '1') THEN |
|
325 | ELSIF (BHE_b'EVENT AND NOT(BLE_b'EVENT) AND write_enable = '1') THEN | |
322 |
|
326 | |||
323 | IF (BHE_b = '0') THEN |
|
327 | IF (BHE_b = '0') THEN | |
324 |
|
328 | |||
325 | --- Reset timing variables |
|
329 | --- Reset timing variables | |
326 | tAW_chk := A'LAST_EVENT; |
|
330 | tAW_chk := A'LAST_EVENT; | |
327 | tBBW_chk := NOW; |
|
331 | tBBW_chk := NOW; | |
328 | write_flag := true; |
|
332 | write_flag := true; | |
329 |
|
333 | |||
330 | ELSIF (BHE_b = '1') THEN |
|
334 | ELSIF (BHE_b = '1') THEN | |
331 |
|
335 | |||
332 | --- check for pulse width |
|
336 | --- check for pulse width | |
333 | IF (NOW - tPWE_chk >= tPWE) THEN |
|
337 | IF (NOW - tPWE_chk >= tPWE) THEN | |
334 | --- tPWE OK, do nothing |
|
338 | --- tPWE OK, do nothing | |
335 | ELSE |
|
339 | ELSE | |
336 | IF (TimingInfo) THEN |
|
340 | IF (TimingInfo) THEN | |
337 | ASSERT false |
|
341 | ASSERT false | |
338 | REPORT "Pulse Width violation"; |
|
342 | REPORT "Pulse Width violation"; | |
339 | END IF; |
|
343 | END IF; | |
340 |
|
344 | |||
341 | write_flag := false; |
|
345 | write_flag := false; | |
342 | END IF; |
|
346 | END IF; | |
343 |
|
347 | |||
344 | --- check for address setup with write end, i.e., tAW |
|
348 | --- check for address setup with write end, i.e., tAW | |
345 | IF (NOW - tAW_chk >= tAW) THEN |
|
349 | IF (NOW - tAW_chk >= tAW) THEN | |
346 | --- tAW OK, do nothing |
|
350 | --- tAW OK, do nothing | |
347 | ELSE |
|
351 | ELSE | |
348 | IF (TimingInfo) THEN |
|
352 | IF (TimingInfo) THEN | |
349 | ASSERT false |
|
353 | ASSERT false | |
350 | REPORT "Address setup tAW violation for Upper Byte Write"; |
|
354 | REPORT "Address setup tAW violation for Upper Byte Write"; | |
351 | END IF; |
|
355 | END IF; | |
352 | write_flag := false; |
|
356 | write_flag := false; | |
353 | END IF; |
|
357 | END IF; | |
354 |
|
358 | |||
355 | --- check for byte setup with write end, i.e., tBW |
|
359 | --- check for byte setup with write end, i.e., tBW | |
356 | IF (NOW - tBBW_chk >= tBW) THEN |
|
360 | IF (NOW - tBBW_chk >= tBW) THEN | |
357 | --- tBW OK, do nothing |
|
361 | --- tBW OK, do nothing | |
358 | ELSE |
|
362 | ELSE | |
359 | IF (TimingInfo) THEN |
|
363 | IF (TimingInfo) THEN | |
360 | ASSERT false |
|
364 | ASSERT false | |
361 | REPORT "Upper Byte setup tBW violation"; |
|
365 | REPORT "Upper Byte setup tBW violation"; | |
362 | END IF; |
|
366 | END IF; | |
363 |
|
367 | |||
364 | write_flag := false; |
|
368 | write_flag := false; | |
365 | END IF; |
|
369 | END IF; | |
366 |
|
370 | |||
367 | --- check for data setup with write end, i.e., tSD |
|
371 | --- check for data setup with write end, i.e., tSD | |
368 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
372 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN | |
369 | --- tSD OK, do nothing |
|
373 | --- tSD OK, do nothing | |
370 | ELSE |
|
374 | ELSE | |
371 | IF (TimingInfo) THEN |
|
375 | IF (TimingInfo) THEN | |
372 | ASSERT false |
|
376 | ASSERT false | |
373 | REPORT "Data setup tSD violation for Upper Byte Write"; |
|
377 | REPORT "Data setup tSD violation for Upper Byte Write"; | |
374 | END IF; |
|
378 | END IF; | |
375 |
|
379 | |||
376 | write_flag := false; |
|
380 | write_flag := false; | |
377 | END IF; |
|
381 | END IF; | |
378 |
|
382 | |||
379 | --- perform WRITE operation if no violations |
|
383 | --- perform WRITE operation if no violations | |
380 |
|
384 | |||
381 | IF (write_flag = true) THEN |
|
385 | IF (write_flag = true) THEN | |
382 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
386 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); | |
383 | IF (BLE_b = '0') THEN |
|
387 | IF (BLE_b = '0') THEN | |
384 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
388 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); | |
385 | END IF; |
|
389 | END IF; | |
386 |
|
390 | |||
387 | END IF; |
|
391 | END IF; | |
388 |
|
392 | |||
389 | --- Reset timing variables |
|
393 | --- Reset timing variables | |
390 | tAW_chk := A'LAST_EVENT; |
|
394 | tAW_chk := A'LAST_EVENT; | |
391 | tBBW_chk := NOW; |
|
395 | tBBW_chk := NOW; | |
392 | write_flag := true; |
|
396 | write_flag := true; | |
393 |
|
397 | |||
394 | END IF; |
|
398 | END IF; | |
395 |
|
399 | |||
396 | END IF; |
|
400 | END IF; | |
397 | --- END OF WRITE |
|
401 | --- END OF WRITE | |
398 |
|
402 | |||
399 | IF (data_skew'EVENT AND read_enable /= '1') THEN |
|
403 | IF (data_skew'EVENT AND read_enable /= '1') THEN | |
400 | tSD_chk := NOW; |
|
404 | tSD_chk := NOW; | |
401 | END IF; |
|
405 | END IF; | |
402 |
|
406 | |||
403 | --- START of READ |
|
407 | --- START of READ | |
404 |
|
408 | |||
405 | --- Tri-state the data bus if CE or OE disabled |
|
409 | --- Tri-state the data bus if CE or OE disabled | |
406 | IF (read_enable = '0' AND read_enable'EVENT) THEN |
|
410 | IF (read_enable = '0' AND read_enable'EVENT) THEN | |
407 | IF (OE_b'LAST_EVENT >= CE_b'LAST_EVENT) THEN |
|
411 | IF (OE_b'LAST_EVENT >= CE_b'LAST_EVENT) THEN | |
408 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
412 | DQ <= (OTHERS => 'Z') after tHZCE; | |
409 | ELSIF (CE_b'LAST_EVENT > OE_b'LAST_EVENT) THEN |
|
413 | ELSIF (CE_b'LAST_EVENT > OE_b'LAST_EVENT) THEN | |
410 | DQ <= (OTHERS => 'Z') after tHZOE; |
|
414 | DQ <= (OTHERS => 'Z') after tHZOE; | |
411 | END IF; |
|
415 | END IF; | |
412 | END IF; |
|
416 | END IF; | |
413 |
|
417 | |||
414 | --- Address-controlled READ operation |
|
418 | --- Address-controlled READ operation | |
415 | IF (A'EVENT) THEN |
|
419 | IF (A'EVENT) THEN | |
416 | IF (A'LAST_EVENT = CE_b'LAST_EVENT AND CE_b = '1') THEN |
|
420 | IF (A'LAST_EVENT = CE_b'LAST_EVENT AND CE_b = '1') THEN | |
417 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
421 | DQ <= (OTHERS => 'Z') after tHZCE; | |
418 | END IF; |
|
422 | END IF; | |
419 |
|
423 | |||
420 | IF (NOW - tRC_chk >= tRC OR NOW - tRC_chk <= 0.1 ns OR tRC_chk = 0 ns) THEN |
|
424 | IF (NOW - tRC_chk >= tRC OR NOW - tRC_chk <= 0.1 ns OR tRC_chk = 0 ns) THEN | |
421 | --- tRC OK, do nothing |
|
425 | --- tRC OK, do nothing | |
422 | ELSE |
|
426 | ELSE | |
423 |
|
427 | |||
424 | IF (TimingInfo) THEN |
|
428 | IF (TimingInfo) THEN | |
425 | ASSERT false |
|
429 | ASSERT false | |
426 | REPORT "Read Cycle time tRC violation"; |
|
430 | REPORT "Read Cycle time tRC violation"; | |
427 | END IF; |
|
431 | END IF; | |
428 |
|
432 | |||
429 | END IF; |
|
433 | END IF; | |
430 |
|
434 | |||
431 | IF (read_enable = '1') THEN |
|
435 | IF (read_enable = '1') THEN | |
432 |
|
436 | |||
433 | IF (BLE_b = '0') THEN |
|
437 | IF (BLE_b = '0') THEN | |
434 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A))(7 DOWNTO 0) AFTER tAA; |
|
438 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A))(7 DOWNTO 0) AFTER tAA; | |
435 | END IF; |
|
439 | END IF; | |
436 |
|
440 | |||
437 | IF (BHE_b = '0') THEN |
|
441 | IF (BHE_b = '0') THEN | |
438 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A))(15 DOWNTO 8) AFTER tAA; |
|
442 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A))(15 DOWNTO 8) AFTER tAA; | |
439 | END IF; |
|
443 | END IF; | |
440 |
|
444 | |||
441 | tRC_chk := NOW; |
|
445 | tRC_chk := NOW; | |
442 |
|
446 | |||
443 | END IF; |
|
447 | END IF; | |
444 |
|
448 | |||
445 | IF (write_enable = '1') THEN |
|
449 | IF (write_enable = '1') THEN | |
446 | --- do nothing |
|
450 | --- do nothing | |
447 | END IF; |
|
451 | END IF; | |
448 |
|
452 | |||
449 | END IF; |
|
453 | END IF; | |
450 |
|
454 | |||
451 | IF (read_enable = '0' AND read_enable'EVENT) THEN |
|
455 | IF (read_enable = '0' AND read_enable'EVENT) THEN | |
452 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
456 | DQ <= (OTHERS => 'Z') after tHZCE; | |
453 | IF (NOW - tRC_chk >= tRC OR tRC_chk = 0 ns OR A'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
457 | IF (NOW - tRC_chk >= tRC OR tRC_chk = 0 ns OR A'LAST_EVENT = read_enable'LAST_EVENT) THEN | |
454 | --- tRC_chk needs to be reset when read ends |
|
458 | --- tRC_chk needs to be reset when read ends | |
455 | tRC_CHK := 0 ns; |
|
459 | tRC_CHK := 0 ns; | |
456 | ELSE |
|
460 | ELSE | |
457 | IF (TimingInfo) THEN |
|
461 | IF (TimingInfo) THEN | |
458 | ASSERT false |
|
462 | ASSERT false | |
459 | REPORT "Read Cycle time tRC violation"; |
|
463 | REPORT "Read Cycle time tRC violation"; | |
460 | END IF; |
|
464 | END IF; | |
461 | tRC_CHK := 0 ns; |
|
465 | tRC_CHK := 0 ns; | |
462 | END IF; |
|
466 | END IF; | |
463 |
|
467 | |||
464 | END IF; |
|
468 | END IF; | |
465 |
|
469 | |||
466 | --- READ operation triggered by CE/OE/BHE/BLE |
|
470 | --- READ operation triggered by CE/OE/BHE/BLE | |
467 | IF (read_enable = '1' AND read_enable'EVENT) THEN |
|
471 | IF (read_enable = '1' AND read_enable'EVENT) THEN | |
468 |
|
472 | |||
469 | tRC_chk := NOW; |
|
473 | tRC_chk := NOW; | |
470 |
|
474 | |||
471 | --- CE triggered READ |
|
475 | --- CE triggered READ | |
472 | IF (CE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN -- changed rev2 |
|
476 | IF (CE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN -- changed rev2 | |
473 |
|
477 | |||
474 | IF (BLE_b = '0') THEN |
|
478 | IF (BLE_b = '0') THEN | |
475 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; |
|
479 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; | |
476 | END IF; |
|
480 | END IF; | |
477 |
|
481 | |||
478 | IF (BHE_b = '0') THEN |
|
482 | IF (BHE_b = '0') THEN | |
479 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; |
|
483 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; | |
480 | END IF; |
|
484 | END IF; | |
481 |
|
485 | |||
482 | END IF; |
|
486 | END IF; | |
483 |
|
487 | |||
484 |
|
488 | |||
485 | --- OE triggered READ |
|
489 | --- OE triggered READ | |
486 | IF (OE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
490 | IF (OE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN | |
487 |
|
491 | |||
488 | -- if address or CE changes before OE such that tAA/tACE > tDOE |
|
492 | -- if address or CE changes before OE such that tAA/tACE > tDOE | |
489 | IF (CE_b'LAST_EVENT < tACE - tDOE AND A'LAST_EVENT < tAA - tDOE) THEN |
|
493 | IF (CE_b'LAST_EVENT < tACE - tDOE AND A'LAST_EVENT < tAA - tDOE) THEN | |
490 |
|
494 | |||
491 | IF (A'LAST_EVENT < CE_b'LAST_EVENT) THEN |
|
495 | IF (A'LAST_EVENT < CE_b'LAST_EVENT) THEN | |
492 |
|
496 | |||
493 | accesstime := tAA-A'LAST_EVENT; |
|
497 | accesstime := tAA-A'LAST_EVENT; | |
494 | IF (BLE_b = '0') THEN |
|
498 | IF (BLE_b = '0') THEN | |
495 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
499 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; | |
496 | END IF; |
|
500 | END IF; | |
497 |
|
501 | |||
498 | IF (BHE_b = '0') THEN |
|
502 | IF (BHE_b = '0') THEN | |
499 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
503 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; | |
500 | END IF; |
|
504 | END IF; | |
501 |
|
505 | |||
502 | ELSE |
|
506 | ELSE | |
503 | accesstime := tACE-CE_b'LAST_EVENT; |
|
507 | accesstime := tACE-CE_b'LAST_EVENT; | |
504 | IF (BLE_b = '0') THEN |
|
508 | IF (BLE_b = '0') THEN | |
505 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
509 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; | |
506 | END IF; |
|
510 | END IF; | |
507 |
|
511 | |||
508 | IF (BHE_b = '0') THEN |
|
512 | IF (BHE_b = '0') THEN | |
509 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
513 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; | |
510 | END IF; |
|
514 | END IF; | |
511 | END IF; |
|
515 | END IF; | |
512 |
|
516 | |||
513 | -- if address changes before OE such that tAA > tDOE |
|
517 | -- if address changes before OE such that tAA > tDOE | |
514 | ELSIF (A'LAST_EVENT < tAA - tDOE) THEN |
|
518 | ELSIF (A'LAST_EVENT < tAA - tDOE) THEN | |
515 |
|
519 | |||
516 | accesstime := tAA-A'LAST_EVENT; |
|
520 | accesstime := tAA-A'LAST_EVENT; | |
517 | IF (BLE_b = '0') THEN |
|
521 | IF (BLE_b = '0') THEN | |
518 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
522 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; | |
519 | END IF; |
|
523 | END IF; | |
520 |
|
524 | |||
521 | IF (BHE_b = '0') THEN |
|
525 | IF (BHE_b = '0') THEN | |
522 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
526 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; | |
523 | END IF; |
|
527 | END IF; | |
524 |
|
528 | |||
525 | -- if CE changes before OE such that tACE > tDOE |
|
529 | -- if CE changes before OE such that tACE > tDOE | |
526 | ELSIF (CE_b'LAST_EVENT < tACE - tDOE) THEN |
|
530 | ELSIF (CE_b'LAST_EVENT < tACE - tDOE) THEN | |
527 |
|
531 | |||
528 | accesstime := tACE-CE_b'LAST_EVENT; |
|
532 | accesstime := tACE-CE_b'LAST_EVENT; | |
529 | IF (BLE_b = '0') THEN |
|
533 | IF (BLE_b = '0') THEN | |
530 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
534 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; | |
531 | END IF; |
|
535 | END IF; | |
532 |
|
536 | |||
533 | IF (BHE_b = '0') THEN |
|
537 | IF (BHE_b = '0') THEN | |
534 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
538 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; | |
535 | END IF; |
|
539 | END IF; | |
536 |
|
540 | |||
537 | -- if OE changes such that tDOE > tAA/tACE |
|
541 | -- if OE changes such that tDOE > tAA/tACE | |
538 | ELSE |
|
542 | ELSE | |
539 | IF (BLE_b = '0') THEN |
|
543 | IF (BLE_b = '0') THEN | |
540 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDOE; |
|
544 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDOE; | |
541 | END IF; |
|
545 | END IF; | |
542 |
|
546 | |||
543 | IF (BHE_b = '0') THEN |
|
547 | IF (BHE_b = '0') THEN | |
544 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDOE; |
|
548 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDOE; | |
545 | END IF; |
|
549 | END IF; | |
546 |
|
550 | |||
547 | END IF; |
|
551 | END IF; | |
548 |
|
552 | |||
549 | END IF; |
|
553 | END IF; | |
550 | --- END of OE triggered READ |
|
554 | --- END of OE triggered READ | |
551 |
|
555 | |||
552 | --- BLE/BHE triggered READ |
|
556 | --- BLE/BHE triggered READ | |
553 | IF (BLE_b'LAST_EVENT = read_enable'LAST_EVENT OR BHE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
557 | IF (BLE_b'LAST_EVENT = read_enable'LAST_EVENT OR BHE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN | |
554 |
|
558 | |||
555 | -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE |
|
559 | -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE | |
556 | IF (CE_b'LAST_EVENT < tACE - tDBE AND A'LAST_EVENT < tAA - tDBE) THEN |
|
560 | IF (CE_b'LAST_EVENT < tACE - tDBE AND A'LAST_EVENT < tAA - tDBE) THEN | |
557 |
|
561 | |||
558 | IF (A'LAST_EVENT < BLE_b'LAST_EVENT) THEN |
|
562 | IF (A'LAST_EVENT < BLE_b'LAST_EVENT) THEN | |
559 | accesstime := tAA-A'LAST_EVENT; |
|
563 | accesstime := tAA-A'LAST_EVENT; | |
560 |
|
564 | |||
561 | IF (BLE_b = '0') THEN |
|
565 | IF (BLE_b = '0') THEN | |
562 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
566 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; | |
563 | END IF; |
|
567 | END IF; | |
564 |
|
568 | |||
565 | IF (BHE_b = '0') THEN |
|
569 | IF (BHE_b = '0') THEN | |
566 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
570 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; | |
567 | END IF; |
|
571 | END IF; | |
568 |
|
572 | |||
569 | ELSE |
|
573 | ELSE | |
570 | accesstime := tACE-CE_b'LAST_EVENT; |
|
574 | accesstime := tACE-CE_b'LAST_EVENT; | |
571 |
|
575 | |||
572 | IF (BLE_b = '0') THEN |
|
576 | IF (BLE_b = '0') THEN | |
573 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
577 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; | |
574 | END IF; |
|
578 | END IF; | |
575 |
|
579 | |||
576 | IF (BHE_b = '0') THEN |
|
580 | IF (BHE_b = '0') THEN | |
577 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
581 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; | |
578 | END IF; |
|
582 | END IF; | |
579 | END IF; |
|
583 | END IF; | |
580 |
|
584 | |||
581 | -- if address changes before BHE/BLE such that tAA > tDBE |
|
585 | -- if address changes before BHE/BLE such that tAA > tDBE | |
582 | ELSIF (A'LAST_EVENT < tAA - tDBE) THEN |
|
586 | ELSIF (A'LAST_EVENT < tAA - tDBE) THEN | |
583 | accesstime := tAA-A'LAST_EVENT; |
|
587 | accesstime := tAA-A'LAST_EVENT; | |
584 |
|
588 | |||
585 | IF (BLE_b = '0') THEN |
|
589 | IF (BLE_b = '0') THEN | |
586 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
590 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; | |
587 | END IF; |
|
591 | END IF; | |
588 |
|
592 | |||
589 | IF (BHE_b = '0') THEN |
|
593 | IF (BHE_b = '0') THEN | |
590 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
594 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; | |
591 | END IF; |
|
595 | END IF; | |
592 |
|
596 | |||
593 | -- if CE changes before BHE/BLE such that tACE > tDBE |
|
597 | -- if CE changes before BHE/BLE such that tACE > tDBE | |
594 | ELSIF (CE_b'LAST_EVENT < tACE - tDBE) THEN |
|
598 | ELSIF (CE_b'LAST_EVENT < tACE - tDBE) THEN | |
595 | accesstime := tACE-CE_b'LAST_EVENT; |
|
599 | accesstime := tACE-CE_b'LAST_EVENT; | |
596 |
|
600 | |||
597 | IF (BLE_b = '0') THEN |
|
601 | IF (BLE_b = '0') THEN | |
598 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
602 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; | |
599 | END IF; |
|
603 | END IF; | |
600 |
|
604 | |||
601 | IF (BHE_b = '0') THEN |
|
605 | IF (BHE_b = '0') THEN | |
602 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
606 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; | |
603 | END IF; |
|
607 | END IF; | |
604 |
|
608 | |||
605 | -- if BHE/BLE changes such that tDBE > tAA/tACE |
|
609 | -- if BHE/BLE changes such that tDBE > tAA/tACE | |
606 | ELSE |
|
610 | ELSE | |
607 | IF (BLE_b = '0') THEN |
|
611 | IF (BLE_b = '0') THEN | |
608 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; |
|
612 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; | |
609 | END IF; |
|
613 | END IF; | |
610 |
|
614 | |||
611 | IF (BHE_b = '0') THEN |
|
615 | IF (BHE_b = '0') THEN | |
612 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; |
|
616 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; | |
613 | END IF; |
|
617 | END IF; | |
614 |
|
618 | |||
615 | END IF; |
|
619 | END IF; | |
616 |
|
620 | |||
617 | END IF; |
|
621 | END IF; | |
618 | -- END of BHE/BLE controlled READ |
|
622 | -- END of BHE/BLE controlled READ | |
619 |
|
623 | |||
620 | IF (WE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
624 | IF (WE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN | |
621 |
|
625 | |||
622 | IF (BLE_b = '0') THEN |
|
626 | IF (BLE_b = '0') THEN | |
623 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; |
|
627 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; | |
624 | END IF; |
|
628 | END IF; | |
625 |
|
629 | |||
626 | IF (BHE_b = '0') THEN |
|
630 | IF (BHE_b = '0') THEN | |
627 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; |
|
631 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; | |
628 | END IF; |
|
632 | END IF; | |
629 |
|
633 | |||
630 | END IF; |
|
634 | END IF; | |
631 |
|
635 | |||
632 | END IF; |
|
636 | END IF; | |
633 | --- END OF CE/OE/BHE/BLE controlled READ |
|
637 | --- END OF CE/OE/BHE/BLE controlled READ | |
634 |
|
638 | |||
635 | --- If either BHE or BLE toggle during read mode |
|
639 | --- If either BHE or BLE toggle during read mode | |
636 | IF (BLE_b'EVENT AND BLE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN |
|
640 | IF (BLE_b'EVENT AND BLE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN | |
637 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; |
|
641 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; | |
638 | END IF; |
|
642 | END IF; | |
639 |
|
643 | |||
640 | IF (BHE_b'EVENT AND BHE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN |
|
644 | IF (BHE_b'EVENT AND BHE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN | |
641 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; |
|
645 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; | |
642 | END IF; |
|
646 | END IF; | |
643 |
|
647 | |||
644 | --- tri-state bus depending on BHE/BLE |
|
648 | --- tri-state bus depending on BHE/BLE | |
645 | IF (BLE_b'EVENT AND BLE_b = '1') THEN |
|
649 | IF (BLE_b'EVENT AND BLE_b = '1') THEN | |
646 | DQ (7 DOWNTO 0) <= (OTHERS => 'Z') after tHZBE; |
|
650 | DQ (7 DOWNTO 0) <= (OTHERS => 'Z') after tHZBE; | |
647 | END IF; |
|
651 | END IF; | |
648 |
|
652 | |||
649 | IF (BHE_b'EVENT AND BHE_b = '1') THEN |
|
653 | IF (BHE_b'EVENT AND BHE_b = '1') THEN | |
650 | DQ (15 DOWNTO 8) <= (OTHERS => 'Z') after tHZBE; |
|
654 | DQ (15 DOWNTO 8) <= (OTHERS => 'Z') after tHZBE; | |
651 | END IF; |
|
655 | END IF; | |
652 |
|
656 | |||
653 | WAIT ON write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew, address_skew; |
|
657 | WAIT ON write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew, address_skew; | |
654 |
|
658 | |||
655 | END PROCESS; |
|
659 | END PROCESS; | |
656 |
|
660 | |||
657 |
|
661 | |||
658 | END behave_arch; |
|
662 | END behave_arch; |
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