@@ -1,48 +1,54 | |||
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1 | 1 | onerror {resume} |
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2 | 2 | quietly WaveActivateNextPane {} 0 |
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3 | 3 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot |
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4 | 4 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run |
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5 | 5 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out |
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6 | 6 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out |
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7 | 7 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out |
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8 | 8 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid |
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9 | 9 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid |
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10 | 10 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid |
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11 | add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd | |
|
12 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_1/mem_array_t | |
|
13 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_t | |
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14 |
add wave -noupdate |
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15 |
add wave -noupdate |
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16 |
add wave -noupdate |
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17 |
add wave -noupdate |
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18 |
add wave -noupdate |
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19 |
add wave -noupdate |
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20 |
add wave -noupdate |
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21 |
add wave -noupdate |
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22 |
add wave -noupdate |
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23 |
add wave -noupdate |
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24 |
add wave -noupdate |
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25 |
add wave -noupdate |
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26 | add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin | |
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27 | add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout | |
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28 | add wave -noupdate -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain | |
|
11 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd | |
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12 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address | |
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13 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in | |
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14 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out | |
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15 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data | |
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16 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay | |
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17 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done | |
|
18 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex | |
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19 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn | |
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20 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren | |
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21 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run | |
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22 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send | |
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23 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst | |
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24 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin | |
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25 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout | |
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26 | add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain | |
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29 | 27 | add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data |
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30 | 28 | add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant |
|
31 |
add wave -noupdate |
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29 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout | |
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30 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0 | |
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31 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_0 | |
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32 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1 | |
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33 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1 | |
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34 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2 | |
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35 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 | |
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36 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3 | |
|
37 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_3 | |
|
32 | 38 | TreeUpdate [SetDefaultTree] |
|
33 |
WaveRestoreCursors {{Cursor 1} {12 |
|
|
39 | WaveRestoreCursors {{Cursor 1} {12913873180 ps} 0} | |
|
34 | 40 | configure wave -namecolwidth 540 |
|
35 | 41 | configure wave -valuecolwidth 316 |
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36 | 42 | configure wave -justifyvalue left |
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37 | 43 | configure wave -signalnamewidth 0 |
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38 | 44 | configure wave -snapdistance 10 |
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39 | 45 | configure wave -datasetprefix 0 |
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40 | 46 | configure wave -rowmargin 4 |
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41 | 47 | configure wave -childrowmargin 2 |
|
42 | 48 | configure wave -gridoffset 0 |
|
43 | 49 | configure wave -gridperiod 1 |
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44 | 50 | configure wave -griddelta 40 |
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45 | 51 | configure wave -timeline 0 |
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46 | 52 | configure wave -timelineunits ns |
|
47 | 53 | update |
|
48 |
WaveRestoreZoom {0 ps} { |
|
|
54 | WaveRestoreZoom {0 ps} {63240778126 ps} |
@@ -1,445 +1,445 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- LEON3 Demonstration design test bench |
|
3 | 3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
4 | 4 | ------------------------------------------------------------------------------ |
|
5 | 5 | -- This file is a part of the GRLIB VHDL IP LIBRARY |
|
6 | 6 | -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. |
|
7 | 7 | -- |
|
8 | 8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN |
|
9 | 9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED |
|
10 | 10 | -- IN ADVANCE IN WRITING. |
|
11 | 11 | ------------------------------------------------------------------------------ |
|
12 | 12 | |
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13 | 13 | LIBRARY ieee; |
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14 | 14 | USE ieee.std_logic_1164.ALL; |
|
15 | 15 | |
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16 | 16 | --LIBRARY std; |
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17 | 17 | --USE std.textio.ALL; |
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18 | 18 | |
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19 | 19 | LIBRARY grlib; |
|
20 | 20 | USE grlib.amba.ALL; |
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21 | 21 | USE grlib.stdlib.ALL; |
|
22 | 22 | LIBRARY gaisler; |
|
23 | 23 | USE gaisler.memctrl.ALL; |
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24 | 24 | USE gaisler.leon3.ALL; |
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25 | 25 | USE gaisler.uart.ALL; |
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26 | 26 | USE gaisler.misc.ALL; |
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27 | 27 | USE gaisler.libdcom.ALL; |
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28 | 28 | USE gaisler.sim.ALL; |
|
29 | 29 | USE gaisler.jtagtst.ALL; |
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30 | 30 | USE gaisler.misc.ALL; |
|
31 | 31 | LIBRARY techmap; |
|
32 | 32 | USE techmap.gencomp.ALL; |
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33 | 33 | LIBRARY esa; |
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34 | 34 | USE esa.memoryctrl.ALL; |
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35 | 35 | --LIBRARY micron; |
|
36 | 36 | --USE micron.components.ALL; |
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37 | 37 | LIBRARY lpp; |
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38 | 38 | USE lpp.lpp_waveform_pkg.ALL; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | USE lpp.testbench_package.ALL; |
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42 | 42 | USE lpp.lpp_lfr_pkg.ALL; |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.CY7C1061DV33_pkg.ALL; |
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46 | 46 | |
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47 | 47 | ENTITY testbench IS |
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48 | 48 | END; |
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49 | 49 | |
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50 | 50 | ARCHITECTURE behav OF testbench IS |
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51 | 51 | -- REG ADDRESS |
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52 | 52 | CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15; |
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53 | 53 | CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15; |
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54 | 54 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; |
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55 | 55 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; |
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56 | 56 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; |
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57 | 57 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; |
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58 | 58 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; |
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59 | 59 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; |
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60 | 60 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; |
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61 | 61 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; |
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62 | 62 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; |
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63 | 63 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; |
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64 | 64 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; |
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65 | 65 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; |
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66 | 66 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; |
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67 | 67 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; |
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68 | 68 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; |
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69 | 69 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; |
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70 | 70 | -- RAM ADDRESS |
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71 | 71 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; |
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72 | 72 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
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73 | 73 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; |
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74 | 74 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; |
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75 | 75 | |
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76 | 76 | |
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77 | 77 | -- Common signal |
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78 | 78 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; |
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79 | 79 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
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80 | 80 | SIGNAL rstn : STD_LOGIC := '0'; |
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81 | 81 | |
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82 | 82 | -- ADC interface |
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83 | 83 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT |
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84 | 84 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT |
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85 | 85 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN |
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86 | 86 | |
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87 | 87 | -- AD Converter RHF1401 |
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88 | 88 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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89 | 89 | SIGNAL sample_val : STD_LOGIC; |
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90 | 90 | |
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91 | 91 | -- AHB/APB SIGNAL |
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92 | 92 | SIGNAL apbi : apb_slv_in_type; |
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93 | 93 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
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94 | 94 | SIGNAL ahbsi : ahb_slv_in_type; |
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95 | 95 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
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96 | 96 | SIGNAL ahbmi : ahb_mst_in_type; |
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97 | 97 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
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98 | 98 | |
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99 | 99 | SIGNAL bias_fail_bw : STD_LOGIC; |
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100 | 100 | |
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101 | 101 | ----------------------------------------------------------------------------- |
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102 | 102 | -- LPP_WAVEFORM |
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103 | 103 | ----------------------------------------------------------------------------- |
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104 | 104 | CONSTANT data_size : INTEGER := 96; |
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105 | 105 | CONSTANT nb_burst_available_size : INTEGER := 50; |
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106 | 106 | CONSTANT nb_snapshot_param_size : INTEGER := 2; |
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107 | 107 | CONSTANT delta_vector_size : INTEGER := 2; |
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108 | 108 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; |
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109 | 109 | |
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110 | 110 | SIGNAL reg_run : STD_LOGIC; |
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111 | 111 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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112 | 112 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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113 | 113 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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114 | 114 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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115 | 115 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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116 | 116 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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117 | 117 | SIGNAL enable_f0 : STD_LOGIC; |
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118 | 118 | SIGNAL enable_f1 : STD_LOGIC; |
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119 | 119 | SIGNAL enable_f2 : STD_LOGIC; |
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120 | 120 | SIGNAL enable_f3 : STD_LOGIC; |
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121 | 121 | SIGNAL burst_f0 : STD_LOGIC; |
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122 | 122 | SIGNAL burst_f1 : STD_LOGIC; |
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123 | 123 | SIGNAL burst_f2 : STD_LOGIC; |
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124 | 124 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
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125 | 125 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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126 | 126 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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127 | 127 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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128 | 128 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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129 | 129 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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130 | 130 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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131 | 131 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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132 | 132 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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133 | 133 | SIGNAL data_f0_in_valid : STD_LOGIC; |
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134 | 134 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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135 | 135 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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136 | 136 | SIGNAL data_f1_in_valid : STD_LOGIC; |
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137 | 137 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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138 | 138 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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139 | 139 | SIGNAL data_f2_in_valid : STD_LOGIC; |
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140 | 140 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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141 | 141 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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142 | 142 | SIGNAL data_f3_in_valid : STD_LOGIC; |
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143 | 143 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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144 | 144 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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145 | 145 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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146 | 146 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
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147 | 147 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
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148 | 148 | SIGNAL data_f0_data_out_ack : STD_LOGIC; |
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149 | 149 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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150 | 150 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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151 | 151 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
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152 | 152 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
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153 | 153 | SIGNAL data_f1_data_out_ack : STD_LOGIC; |
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154 | 154 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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155 | 155 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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156 | 156 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
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157 | 157 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
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158 | 158 | SIGNAL data_f2_data_out_ack : STD_LOGIC; |
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159 | 159 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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160 | 160 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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161 | 161 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
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162 | 162 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
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163 | 163 | SIGNAL data_f3_data_out_ack : STD_LOGIC; |
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164 | 164 | |
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165 | 165 | --MEM CTRLR |
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166 | 166 | SIGNAL memi : memory_in_type; |
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167 | 167 | SIGNAL memo : memory_out_type; |
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168 | 168 | SIGNAL wpo : wprot_out_type; |
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169 | 169 | SIGNAL sdo : sdram_out_type; |
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170 | 170 | |
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171 | 171 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0); |
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172 | 172 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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173 | 173 | SIGNAL nSRAM_BE0 : STD_LOGIC; |
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174 | 174 | SIGNAL nSRAM_BE1 : STD_LOGIC; |
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175 | 175 | SIGNAL nSRAM_BE2 : STD_LOGIC; |
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176 | 176 | SIGNAL nSRAM_BE3 : STD_LOGIC; |
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177 | 177 | SIGNAL nSRAM_WE : STD_LOGIC; |
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178 | 178 | SIGNAL nSRAM_CE : STD_LOGIC; |
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179 | 179 | SIGNAL nSRAM_OE : STD_LOGIC; |
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180 | 180 | |
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181 | 181 | CONSTANT padtech : INTEGER := inferred; |
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182 | 182 | SIGNAL not_ramsn_0 : STD_LOGIC; |
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183 | 183 | |
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184 | 184 | |
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185 | 185 | BEGIN |
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186 | 186 | |
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187 | 187 | ----------------------------------------------------------------------------- |
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188 | 188 | |
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189 | 189 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
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190 | 190 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz |
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191 | 191 | |
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192 | 192 | ----------------------------------------------------------------------------- |
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193 | 193 | |
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194 | 194 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
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195 | 195 | TestModule_RHF1401_1 : TestModule_RHF1401 |
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196 | 196 | GENERIC MAP ( |
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197 | 197 | freq => 24*(I+1), |
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198 | 198 | amplitude => 8000/(I+1), |
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199 | 199 | impulsion => 0) |
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200 | 200 | PORT MAP ( |
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201 | 201 | ADC_smpclk => ADC_smpclk, |
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202 | 202 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
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203 | 203 | ADC_data => ADC_data); |
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204 | 204 | END GENERATE MODULE_RHF1401; |
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205 | 205 | |
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206 | 206 | ----------------------------------------------------------------------------- |
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207 | 207 | |
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208 | 208 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
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209 | 209 | GENERIC MAP ( |
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210 | 210 | ChanelCount => 8, |
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211 | 211 | ncycle_cnv_high => 79, |
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212 | 212 | ncycle_cnv => 500) |
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213 | 213 | PORT MAP ( |
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214 | 214 | cnv_clk => clk49_152MHz, |
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215 | 215 | cnv_rstn => rstn, |
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216 | 216 | cnv => ADC_smpclk, |
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217 | 217 | clk => clk25MHz, |
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218 | 218 | rstn => rstn, |
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219 | 219 | ADC_data => ADC_data, |
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220 | 220 | ADC_nOE => ADC_OEB_bar_CH, |
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221 | 221 | sample => sample, |
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222 | 222 | sample_val => sample_val); |
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223 | 223 | |
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224 | 224 | ----------------------------------------------------------------------------- |
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225 | 225 | |
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226 | 226 | lpp_lfr_1 : lpp_lfr |
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227 | 227 | GENERIC MAP ( |
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228 | 228 | Mem_use => use_CEL, -- use_RAM |
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229 | 229 | nb_data_by_buffer_size => 32, |
|
230 | 230 | nb_word_by_buffer_size => 30, |
|
231 | 231 | nb_snapshot_param_size => 32, |
|
232 | 232 | delta_vector_size => 32, |
|
233 | 233 | delta_vector_size_f0_2 => 32, |
|
234 | 234 | pindex => INDEX_WAVEFORM_PICKER, |
|
235 | 235 | paddr => ADDR_WAVEFORM_PICKER, |
|
236 | 236 | pmask => 16#fff#, |
|
237 | 237 | pirq_ms => 6, |
|
238 | 238 | pirq_wfp => 14, |
|
239 | 239 | hindex => 0, |
|
240 | 240 | top_lfr_version => X"00000001") |
|
241 | 241 | PORT MAP ( |
|
242 | 242 | clk => clk25MHz, |
|
243 | 243 | rstn => rstn, |
|
244 | 244 | sample_B => sample(2 DOWNTO 0), |
|
245 | 245 | sample_E => sample(7 DOWNTO 3), |
|
246 | 246 | sample_val => sample_val, |
|
247 | 247 | apbi => apbi, |
|
248 | 248 | apbo => apbo(15), |
|
249 | 249 | ahbi => ahbmi, |
|
250 | 250 | ahbo => ahbmo(0), |
|
251 | 251 | coarse_time => coarse_time, |
|
252 | 252 | fine_time => fine_time, |
|
253 | 253 | data_shaping_BW => bias_fail_bw); |
|
254 | 254 | |
|
255 | 255 | ----------------------------------------------------------------------------- |
|
256 | 256 | --- AHB CONTROLLER ------------------------------------------------- |
|
257 | 257 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
258 | 258 | GENERIC MAP (defmast => 0, split => 0, |
|
259 | 259 | rrobin => 1, ioaddr => 16#FFF#, |
|
260 | 260 | ioen => 0, nahbm => 1, nahbs => 1) |
|
261 | 261 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
262 | 262 | |
|
263 | 263 | --- AHB RAM ---------------------------------------------------------- |
|
264 | 264 | --ahbram0 : ahbram |
|
265 | 265 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) |
|
266 | 266 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); |
|
267 | 267 | --ahbram1 : ahbram |
|
268 | 268 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) |
|
269 | 269 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); |
|
270 | 270 | --ahbram2 : ahbram |
|
271 | 271 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) |
|
272 | 272 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); |
|
273 | 273 | --ahbram3 : ahbram |
|
274 | 274 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) |
|
275 | 275 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); |
|
276 | 276 | |
|
277 | 277 | ----------------------------------------------------------------------------- |
|
278 | 278 | ---------------------------------------------------------------------- |
|
279 | 279 | --- Memory controllers --------------------------------------------- |
|
280 | 280 | ---------------------------------------------------------------------- |
|
281 | 281 | memctrlr : mctrl GENERIC MAP ( |
|
282 | 282 | hindex => 0, |
|
283 | 283 | pindex => 0, |
|
284 | 284 | paddr => 0, |
|
285 | 285 | srbanks => 1 |
|
286 | 286 | ) |
|
287 | 287 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
288 | 288 | |
|
289 | 289 | memi.brdyn <= '1'; |
|
290 | 290 | memi.bexcn <= '1'; |
|
291 | 291 | memi.writen <= '1'; |
|
292 | 292 | memi.wrn <= "1111"; |
|
293 | 293 | memi.bwidth <= "10"; |
|
294 | 294 | |
|
295 | 295 | bdr : FOR i IN 0 TO 3 GENERATE |
|
296 | 296 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
297 | 297 | PORT MAP ( |
|
298 | 298 | data(31-i*8 DOWNTO 24-i*8), |
|
299 | 299 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
300 | 300 | memo.bdrive(i), |
|
301 | 301 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
302 | 302 | END GENERATE; |
|
303 | 303 | |
|
304 | 304 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
305 | 305 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
306 | 306 | |
|
307 | 307 | not_ramsn_0 <= NOT(memo.ramsn(0)); |
|
308 | 308 | |
|
309 | 309 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); |
|
310 | 310 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
311 | 311 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
312 | 312 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
313 | 313 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
314 | 314 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
315 | 315 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
316 | 316 | |
|
317 | 317 | async_1Mx16_0: CY7C1061DV33 |
|
318 | 318 | GENERIC MAP ( |
|
319 | 319 | ADDR_BITS => 20, |
|
320 | 320 | DATA_BITS => 16, |
|
321 | 321 | depth => 1048576, |
|
322 | 322 | TimingInfo => TRUE, |
|
323 | 323 | TimingChecks => '1') |
|
324 | 324 | PORT MAP ( |
|
325 | 325 | CE1_b => '0', |
|
326 | 326 | CE2 => nSRAM_CE, |
|
327 | 327 | WE_b => nSRAM_WE, |
|
328 | 328 | OE_b => nSRAM_OE, |
|
329 | 329 | BHE_b => nSRAM_BE1, |
|
330 | 330 | BLE_b => nSRAM_BE0, |
|
331 | 331 | A => address, |
|
332 | 332 | DQ => data(15 DOWNTO 0)); |
|
333 | 333 | |
|
334 | 334 | async_1Mx16_1: CY7C1061DV33 |
|
335 | 335 | GENERIC MAP ( |
|
336 | 336 | ADDR_BITS => 20, |
|
337 | 337 | DATA_BITS => 16, |
|
338 | 338 | depth => 1048576, |
|
339 | 339 | TimingInfo => TRUE, |
|
340 | 340 | TimingChecks => '1') |
|
341 | 341 | PORT MAP ( |
|
342 | 342 | CE1_b => '0', |
|
343 | 343 | CE2 => nSRAM_CE, |
|
344 | 344 | WE_b => nSRAM_WE, |
|
345 | 345 | OE_b => nSRAM_OE, |
|
346 | 346 | BHE_b => nSRAM_BE3, |
|
347 | 347 | BLE_b => nSRAM_BE2, |
|
348 | 348 | A => address, |
|
349 | 349 | DQ => data(31 DOWNTO 16)); |
|
350 | 350 | |
|
351 | 351 | |
|
352 | 352 | ----------------------------------------------------------------------------- |
|
353 | 353 | |
|
354 | 354 | WaveGen_Proc : PROCESS |
|
355 | 355 | BEGIN |
|
356 | 356 | |
|
357 | 357 | -- insert signal assignments here |
|
358 | 358 | WAIT UNTIL clk25MHz = '1'; |
|
359 | 359 | rstn <= '0'; |
|
360 | 360 | apbi.psel(15) <= '0'; |
|
361 | 361 | apbi.pwrite <= '0'; |
|
362 | 362 | apbi.penable <= '0'; |
|
363 | 363 | apbi.paddr <= (OTHERS => '0'); |
|
364 | 364 | apbi.pwdata <= (OTHERS => '0'); |
|
365 | 365 | fine_time <= (OTHERS => '0'); |
|
366 | 366 | coarse_time <= (OTHERS => '0'); |
|
367 | 367 | WAIT UNTIL clk25MHz = '1'; |
|
368 | 368 | -- ahbmi.HGRANT(2) <= '1'; |
|
369 | 369 | -- ahbmi.HREADY <= '1'; |
|
370 | 370 | -- ahbmi.HRESP <= HRESP_OKAY; |
|
371 | 371 | |
|
372 | 372 | WAIT UNTIL clk25MHz = '1'; |
|
373 | 373 | WAIT UNTIL clk25MHz = '1'; |
|
374 | 374 | rstn <= '1'; |
|
375 | 375 | WAIT UNTIL clk25MHz = '1'; |
|
376 | 376 | WAIT UNTIL clk25MHz = '1'; |
|
377 | 377 | --------------------------------------------------------------------------- |
|
378 | 378 | -- CONFIGURATION STEP |
|
379 | 379 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); |
|
380 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40 |
|
|
381 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40 |
|
|
382 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40 |
|
|
380 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); | |
|
381 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); | |
|
382 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); | |
|
383 | 383 | |
|
384 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"000000 |
|
|
385 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"000000 |
|
|
386 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"0000000 |
|
|
387 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"000000 |
|
|
384 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020" | |
|
385 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019" | |
|
386 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" | |
|
387 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019" | |
|
388 | 388 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" |
|
389 | 389 | |
|
390 | 390 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" |
|
391 | 391 | -- |
|
392 | 392 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); |
|
393 | 393 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); |
|
394 | 394 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); |
|
395 | 395 | |
|
396 | 396 | |
|
397 | 397 | WAIT UNTIL clk25MHz = '1'; |
|
398 | 398 | WAIT UNTIL clk25MHz = '1'; |
|
399 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"0000008 |
|
|
399 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); | |
|
400 | 400 | WAIT UNTIL clk25MHz = '1'; |
|
401 | 401 | WAIT UNTIL clk25MHz = '1'; |
|
402 | 402 | WAIT UNTIL clk25MHz = '1'; |
|
403 | 403 | WAIT UNTIL clk25MHz = '1'; |
|
404 | 404 | WAIT UNTIL clk25MHz = '1'; |
|
405 | 405 | WAIT UNTIL clk25MHz = '1'; |
|
406 | 406 | WAIT FOR 1 us; |
|
407 | 407 | coarse_time <= X"00000001"; |
|
408 | 408 | --------------------------------------------------------------------------- |
|
409 | 409 | -- RUN STEP |
|
410 | 410 | WAIT FOR 200 ms; |
|
411 | 411 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
412 | 412 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); |
|
413 | 413 | WAIT FOR 10 us; |
|
414 | 414 | WAIT UNTIL clk25MHz = '1'; |
|
415 | 415 | WAIT UNTIL clk25MHz = '1'; |
|
416 | 416 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); |
|
417 | 417 | WAIT UNTIL clk25MHz = '1'; |
|
418 | 418 | coarse_time <= X"00000010"; |
|
419 | 419 | WAIT FOR 100 ms; |
|
420 | 420 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
421 | 421 | WAIT FOR 10 us; |
|
422 | 422 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); |
|
423 | 423 | WAIT FOR 200 ms; |
|
424 | 424 | REPORT "*** END simulation ***" SEVERITY failure; |
|
425 | 425 | |
|
426 | 426 | |
|
427 | 427 | WAIT; |
|
428 | 428 | |
|
429 | 429 | END PROCESS WaveGen_Proc; |
|
430 | 430 | ----------------------------------------------------------------------------- |
|
431 | 431 | |
|
432 | 432 | ----------------------------------------------------------------------------- |
|
433 | 433 | -- IRQ |
|
434 | 434 | ----------------------------------------------------------------------------- |
|
435 | 435 | PROCESS (clk25MHz, rstn) |
|
436 | 436 | BEGIN -- PROCESS |
|
437 | 437 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
438 | 438 | |
|
439 | 439 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
440 | 440 | |
|
441 | 441 | END IF; |
|
442 | 442 | END PROCESS; |
|
443 | 443 | ----------------------------------------------------------------------------- |
|
444 | 444 | |
|
445 | 445 | END; |
@@ -1,658 +1,662 | |||
|
1 | 1 | --************************************************************************ |
|
2 | 2 | --** MODEL : async_1Mx16.vhd ** |
|
3 | 3 | --** COMPANY : Cypress Semiconductor ** |
|
4 | 4 | --** REVISION: 1.0 Created new base model ** |
|
5 | 5 | --************************************************************************ |
|
6 | 6 | |
|
7 | 7 | -------------------------------------------------------------------------------JC\/ |
|
8 | 8 | --Library ieee,work; |
|
9 | 9 | LIBRARY ieee; |
|
10 | 10 | -------------------------------------------------------------------------------JC/\ |
|
11 | 11 | USE IEEE.Std_Logic_1164.ALL; |
|
12 | 12 | USE IEEE.Std_Logic_unsigned.ALL; |
|
13 | 13 | |
|
14 | 14 | -------------------------------------------------------------------------------JC\/ |
|
15 | 15 | --use work.package_timing.all; |
|
16 | 16 | --use work.package_utility.all; |
|
17 | 17 | LIBRARY lpp; |
|
18 | 18 | USE lpp.package_timing.ALL; |
|
19 | 19 | USE lpp.package_utility.ALL; |
|
20 | 20 | -------------------------------------------------------------------------------JC/\ |
|
21 | 21 | |
|
22 | 22 | ------------------------ |
|
23 | 23 | -- Entity Description |
|
24 | 24 | ------------------------ |
|
25 | 25 | |
|
26 | 26 | ENTITY CY7C1061DV33 IS |
|
27 | 27 | GENERIC |
|
28 | 28 | (ADDR_BITS : INTEGER := 20; |
|
29 | 29 | DATA_BITS : INTEGER := 16; |
|
30 | 30 | depth : INTEGER := 1048576; |
|
31 | 31 | |
|
32 | 32 | TimingInfo : BOOLEAN := true; |
|
33 | 33 | TimingChecks : STD_LOGIC := '1' |
|
34 | 34 | ); |
|
35 | 35 | PORT ( |
|
36 | 36 | CE1_b : IN STD_LOGIC; -- Chip Enable CE1# |
|
37 | 37 | CE2 : IN STD_LOGIC; -- Chip Enable CE2 |
|
38 | 38 | WE_b : IN STD_LOGIC; -- Write Enable WE# |
|
39 | 39 | OE_b : IN STD_LOGIC; -- Output Enable OE# |
|
40 | 40 | BHE_b : IN STD_LOGIC; -- Byte Enable High BHE# |
|
41 | 41 | BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE# |
|
42 | 42 | A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A |
|
43 | 43 | DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO; |
|
44 | 44 | ); |
|
45 | 45 | END CY7C1061DV33; |
|
46 | 46 | |
|
47 | 47 | ----------------------------- |
|
48 | 48 | -- End Entity Description |
|
49 | 49 | ----------------------------- |
|
50 | 50 | ----------------------------- |
|
51 | 51 | -- Architecture Description |
|
52 | 52 | ----------------------------- |
|
53 | 53 | |
|
54 | 54 | ARCHITECTURE behave_arch OF CY7C1061DV33 IS |
|
55 | 55 | |
|
56 | 56 | TYPE mem_array_type IS ARRAY (depth-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); |
|
57 | 57 | |
|
58 | 58 | SIGNAL write_enable : STD_LOGIC; |
|
59 | 59 | SIGNAL read_enable : STD_LOGIC; |
|
60 | 60 | SIGNAL byte_enable : STD_LOGIC; |
|
61 | 61 | SIGNAL CE_b : STD_LOGIC; |
|
62 | 62 | |
|
63 | 63 | SIGNAL data_skew : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); |
|
64 | 64 | |
|
65 | 65 | SIGNAL address_internal, address_skew : STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); |
|
66 | 66 | |
|
67 | 67 | CONSTANT tSD_dataskew : TIME := tSD - 1 ns; |
|
68 | 68 | CONSTANT tskew : TIME := 1 ns; |
|
69 | 69 | |
|
70 | 70 | -------------------------------------------------------------------------------JC\/ |
|
71 |
TYPE mem_array_type_t IS ARRAY (1 |
|
|
72 |
SIGNAL mem_array_ |
|
|
71 | TYPE mem_array_type_t IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); | |
|
72 | SIGNAL mem_array_0 : mem_array_type_t; | |
|
73 | SIGNAL mem_array_1 : mem_array_type_t; | |
|
74 | SIGNAL mem_array_2 : mem_array_type_t; | |
|
75 | SIGNAL mem_array_3 : mem_array_type_t; | |
|
73 | 76 | -------------------------------------------------------------------------------JC/\ |
|
74 | 77 | |
|
75 | 78 | |
|
76 | 79 | |
|
77 | 80 | BEGIN |
|
78 | 81 | CE_b <= CE1_b OR NOT(CE2); |
|
79 | 82 | byte_enable <= NOT(BHE_b AND BLE_b); |
|
80 | 83 | write_enable <= NOT(CE1_b) AND CE2 AND NOT(WE_b) AND NOT(BHE_b AND BLE_b); |
|
81 | 84 | read_enable <= NOT(CE1_b) AND CE2 AND (WE_b) AND NOT(OE_b) AND NOT(BHE_b AND BLE_b); |
|
82 | 85 | |
|
83 | 86 | data_skew <= DQ AFTER 1 ns; -- changed on feb 15 |
|
84 | 87 | address_skew <= A AFTER 1 ns; |
|
85 | 88 | |
|
86 | 89 | PROCESS (OE_b) |
|
87 | 90 | BEGIN |
|
88 | 91 | IF (OE_b'EVENT AND OE_b = '1' AND write_enable /= '1') THEN |
|
89 | 92 | DQ <= (OTHERS => 'Z') after tHZOE; |
|
90 | 93 | END IF; |
|
91 | 94 | END PROCESS; |
|
92 | 95 | |
|
93 | 96 | PROCESS (CE_b) |
|
94 | 97 | BEGIN |
|
95 | 98 | IF (CE_b'EVENT AND CE_b = '1') THEN |
|
96 | 99 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
97 | 100 | END IF; |
|
98 | 101 | END PROCESS; |
|
99 | 102 | |
|
100 | 103 | PROCESS (write_enable'DELAYED(tHA)) |
|
101 | 104 | BEGIN |
|
102 | 105 | IF (write_enable'DELAYED(tHA) = '0' AND TimingInfo) THEN |
|
103 | 106 | ASSERT (A'LAST_EVENT = 0 ns) OR (A'LAST_EVENT > tHA) |
|
104 | 107 | REPORT "Address hold time tHA violated"; |
|
105 | 108 | END IF; |
|
106 | 109 | END PROCESS; |
|
107 | 110 | |
|
108 | 111 | PROCESS (write_enable'DELAYED(tHD)) |
|
109 | 112 | BEGIN |
|
110 | 113 | IF (write_enable'DELAYED(tHD) = '0' AND TimingInfo) THEN |
|
111 | 114 | ASSERT (DQ'LAST_EVENT > tHD) OR (DQ'LAST_EVENT = 0 ns) |
|
112 | 115 | REPORT "Data hold time tHD violated"; |
|
113 | 116 | END IF; |
|
114 | 117 | END PROCESS; |
|
115 | 118 | |
|
116 | 119 | -- main process |
|
117 | 120 | PROCESS |
|
118 | 121 | |
|
119 | 122 | VARIABLE mem_array : mem_array_type; |
|
120 | 123 | |
|
121 | 124 | --- Variables for timing checks |
|
122 | 125 | VARIABLE tPWE_chk : TIME := -10 ns; |
|
123 | 126 | VARIABLE tAW_chk : TIME := -10 ns; |
|
124 | 127 | VARIABLE tSD_chk : TIME := -10 ns; |
|
125 | 128 | VARIABLE tRC_chk : TIME := 0 ns; |
|
126 | 129 | VARIABLE tBAW_chk : TIME := 0 ns; |
|
127 | 130 | VARIABLE tBBW_chk : TIME := 0 ns; |
|
128 | 131 | VARIABLE tBCW_chk : TIME := 0 ns; |
|
129 | 132 | VARIABLE tBDW_chk : TIME := 0 ns; |
|
130 | 133 | VARIABLE tSA_chk : TIME := 0 ns; |
|
131 | 134 | VARIABLE tSA_skew : TIME := 0 ns; |
|
132 | 135 | VARIABLE tAint_chk : TIME := -10 ns; |
|
133 | 136 | |
|
134 | 137 | VARIABLE write_flag : BOOLEAN := true; |
|
135 | 138 | |
|
136 | 139 | VARIABLE accesstime : TIME := 0 ns; |
|
137 | 140 | |
|
138 | 141 | BEGIN |
|
139 | 142 | IF (address_skew'EVENT) THEN |
|
140 | 143 | tSA_skew := NOW; |
|
141 | 144 | END IF; |
|
142 | 145 | |
|
143 | 146 | -- start of write |
|
144 | 147 | IF (write_enable = '1' AND write_enable'EVENT) THEN |
|
145 | 148 | |
|
146 | 149 | DQ(DATA_BITS-1 DOWNTO 0) <= (OTHERS => 'Z') after tHZWE; |
|
147 | 150 | |
|
148 | 151 | IF (A'LAST_EVENT >= tSA) THEN |
|
149 | 152 | address_internal <= A; |
|
150 | 153 | tPWE_chk := NOW; |
|
151 | 154 | tAW_chk := A'LAST_EVENT; |
|
152 | 155 | tAint_chk := NOW; |
|
153 | 156 | write_flag := true; |
|
154 | 157 | |
|
155 | 158 | ELSE |
|
156 | 159 | IF (TimingInfo) THEN |
|
157 | 160 | ASSERT false |
|
158 | 161 | REPORT "Address setup violated"; |
|
159 | 162 | END IF; |
|
160 | 163 | write_flag := false; |
|
161 | 164 | |
|
162 | 165 | END IF; |
|
163 | 166 | |
|
164 | 167 | -- end of write (with CE high or WE high) |
|
165 | 168 | ELSIF (write_enable = '0' AND write_enable'EVENT) THEN |
|
166 | 169 | |
|
167 | 170 | --- check for pulse width |
|
168 | 171 | IF (NOW - tPWE_chk >= tPWE OR NOW - tPWE_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
169 | 172 | --- pulse width OK, do nothing |
|
170 | 173 | ELSE |
|
171 | 174 | IF (TimingInfo) THEN |
|
172 | 175 | ASSERT false |
|
173 | 176 | REPORT "Pulse Width violation"; |
|
174 | 177 | END IF; |
|
175 | 178 | |
|
176 | 179 | write_flag := false; |
|
177 | 180 | END IF; |
|
178 | 181 | |
|
179 | 182 | |
|
180 | 183 | IF (NOW > 0 ns) THEN |
|
181 | 184 | IF (tSA_skew - tAint_chk > tskew) THEN |
|
182 | 185 | ASSERT false |
|
183 | 186 | REPORT "Negative address setup"; |
|
184 | 187 | write_flag := false; |
|
185 | 188 | END IF; |
|
186 | 189 | END IF; |
|
187 | 190 | |
|
188 | 191 | --- check for address setup with write end, i.e., tAW |
|
189 | 192 | IF (NOW - tAW_chk >= tAW OR NOW = 0 ns) THEN |
|
190 | 193 | --- tAW OK, do nothing |
|
191 | 194 | ELSE |
|
192 | 195 | IF (TimingInfo) THEN |
|
193 | 196 | ASSERT false |
|
194 | 197 | REPORT "Address setup tAW violation"; |
|
195 | 198 | END IF; |
|
196 | 199 | |
|
197 | 200 | write_flag := false; |
|
198 | 201 | END IF; |
|
199 | 202 | |
|
200 | 203 | --- check for data setup with write end, i.e., tSD |
|
201 | 204 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
202 | 205 | --- tSD OK, do nothing |
|
203 | 206 | ELSE |
|
204 | 207 | IF (TimingInfo) THEN |
|
205 | 208 | ASSERT false |
|
206 | 209 | REPORT "Data setup tSD violation"; |
|
207 | 210 | END IF; |
|
208 | 211 | write_flag := false; |
|
209 | 212 | END IF; |
|
210 | 213 | |
|
211 | 214 | -- perform write operation if no violations |
|
212 | 215 | IF (write_flag = true) THEN |
|
213 | 216 | |
|
214 | 217 | IF (BLE_b = '1' AND BLE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN |
|
215 | 218 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
216 | 219 | END IF; |
|
217 | 220 | |
|
218 | 221 | IF (BHE_b = '1' AND BHE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN |
|
219 | 222 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
220 | 223 | END IF; |
|
221 | 224 | |
|
222 | 225 | IF (BLE_b = '0' AND NOW - tBAW_chk >= tBW) THEN |
|
223 | 226 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
224 | 227 | ELSIF (NOW - tBAW_chk < tBW AND NOW - tBAW_chk > 0.1 ns AND NOW > 0 ns) THEN |
|
225 | 228 | ASSERT false REPORT "Insufficient pulse width for lower byte to be written"; |
|
226 | 229 | END IF; |
|
227 | 230 | |
|
228 | 231 | IF (BHE_b = '0' AND NOW - tBBW_chk >= tBW) THEN |
|
229 | 232 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
230 | 233 | ELSIF (NOW - tBBW_chk < tBW AND NOW - tBBW_chk > 0.1 ns AND NOW > 0 ns) THEN |
|
231 | 234 | ASSERT false REPORT "Insufficient pulse width for higher byte to be written"; |
|
232 | 235 | END IF; |
|
233 | 236 | |
|
234 | 237 | |
|
235 | 238 | -------------------------------------------------------------------------------JC\/ |
|
236 |
all_mem_array_obs: FOR I IN 0 TO 1 |
|
|
237 | IF I < depth THEN | |
|
238 |
mem_array_ |
|
|
239 | END IF; | |
|
239 | all_mem_array_obs: FOR I IN 0 TO 31 LOOP | |
|
240 | IF I + ((2**15) *0) < depth THEN mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF; | |
|
241 | IF I + ((2**15) *1) < depth THEN mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF; | |
|
242 | IF I + ((2**15) *2) < depth THEN mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF; | |
|
243 | IF I + ((2**15) *3) < depth THEN mem_array_3(I) <= mem_array(I+((2**15) *3)); END IF; | |
|
240 | 244 | END LOOP all_mem_array_obs; |
|
241 | 245 | -------------------------------------------------------------------------------JC/\ |
|
242 | 246 | |
|
243 | 247 | END IF; |
|
244 | 248 | |
|
245 | 249 | -- end of write (with BLE high) |
|
246 | 250 | ELSIF (BLE_b'EVENT AND NOT(BHE_b'EVENT) AND write_enable = '1') THEN |
|
247 | 251 | |
|
248 | 252 | IF (BLE_b = '0') THEN |
|
249 | 253 | |
|
250 | 254 | --- Reset timing variables |
|
251 | 255 | tAW_chk := A'LAST_EVENT; |
|
252 | 256 | tBAW_chk := NOW; |
|
253 | 257 | write_flag := true; |
|
254 | 258 | |
|
255 | 259 | ELSIF (BLE_b = '1') THEN |
|
256 | 260 | |
|
257 | 261 | --- check for pulse width |
|
258 | 262 | IF (NOW - tPWE_chk >= tPWE) THEN |
|
259 | 263 | --- tPWE OK, do nothing |
|
260 | 264 | ELSE |
|
261 | 265 | IF (TimingInfo) THEN |
|
262 | 266 | ASSERT false |
|
263 | 267 | REPORT "Pulse Width violation"; |
|
264 | 268 | END IF; |
|
265 | 269 | |
|
266 | 270 | write_flag := false; |
|
267 | 271 | END IF; |
|
268 | 272 | |
|
269 | 273 | --- check for address setup with write end, i.e., tAW |
|
270 | 274 | IF (NOW - tAW_chk >= tAW) THEN |
|
271 | 275 | --- tAW OK, do nothing |
|
272 | 276 | ELSE |
|
273 | 277 | IF (TimingInfo) THEN |
|
274 | 278 | ASSERT false |
|
275 | 279 | REPORT "Address setup tAW violation for Lower Byte Write"; |
|
276 | 280 | END IF; |
|
277 | 281 | |
|
278 | 282 | write_flag := false; |
|
279 | 283 | END IF; |
|
280 | 284 | |
|
281 | 285 | --- check for byte write setup with write end, i.e., tBW |
|
282 | 286 | IF (NOW - tBAW_chk >= tBW) THEN |
|
283 | 287 | --- tBW OK, do nothing |
|
284 | 288 | ELSE |
|
285 | 289 | IF (TimingInfo) THEN |
|
286 | 290 | ASSERT false |
|
287 | 291 | REPORT "Lower Byte setup tBW violation"; |
|
288 | 292 | END IF; |
|
289 | 293 | |
|
290 | 294 | write_flag := false; |
|
291 | 295 | END IF; |
|
292 | 296 | |
|
293 | 297 | --- check for data setup with write end, i.e., tSD |
|
294 | 298 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
295 | 299 | --- tSD OK, do nothing |
|
296 | 300 | ELSE |
|
297 | 301 | IF (TimingInfo) THEN |
|
298 | 302 | ASSERT false |
|
299 | 303 | REPORT "Data setup tSD violation for Lower Byte Write"; |
|
300 | 304 | END IF; |
|
301 | 305 | |
|
302 | 306 | write_flag := false; |
|
303 | 307 | END IF; |
|
304 | 308 | |
|
305 | 309 | --- perform WRITE operation if no violations |
|
306 | 310 | IF (write_flag = true) THEN |
|
307 | 311 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
308 | 312 | IF (BHE_b = '0') THEN |
|
309 | 313 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
310 | 314 | END IF; |
|
311 | 315 | END IF; |
|
312 | 316 | |
|
313 | 317 | --- Reset timing variables |
|
314 | 318 | tAW_chk := A'LAST_EVENT; |
|
315 | 319 | tBAW_chk := NOW; |
|
316 | 320 | write_flag := true; |
|
317 | 321 | |
|
318 | 322 | END IF; |
|
319 | 323 | |
|
320 | 324 | -- end of write (with BHE high) |
|
321 | 325 | ELSIF (BHE_b'EVENT AND NOT(BLE_b'EVENT) AND write_enable = '1') THEN |
|
322 | 326 | |
|
323 | 327 | IF (BHE_b = '0') THEN |
|
324 | 328 | |
|
325 | 329 | --- Reset timing variables |
|
326 | 330 | tAW_chk := A'LAST_EVENT; |
|
327 | 331 | tBBW_chk := NOW; |
|
328 | 332 | write_flag := true; |
|
329 | 333 | |
|
330 | 334 | ELSIF (BHE_b = '1') THEN |
|
331 | 335 | |
|
332 | 336 | --- check for pulse width |
|
333 | 337 | IF (NOW - tPWE_chk >= tPWE) THEN |
|
334 | 338 | --- tPWE OK, do nothing |
|
335 | 339 | ELSE |
|
336 | 340 | IF (TimingInfo) THEN |
|
337 | 341 | ASSERT false |
|
338 | 342 | REPORT "Pulse Width violation"; |
|
339 | 343 | END IF; |
|
340 | 344 | |
|
341 | 345 | write_flag := false; |
|
342 | 346 | END IF; |
|
343 | 347 | |
|
344 | 348 | --- check for address setup with write end, i.e., tAW |
|
345 | 349 | IF (NOW - tAW_chk >= tAW) THEN |
|
346 | 350 | --- tAW OK, do nothing |
|
347 | 351 | ELSE |
|
348 | 352 | IF (TimingInfo) THEN |
|
349 | 353 | ASSERT false |
|
350 | 354 | REPORT "Address setup tAW violation for Upper Byte Write"; |
|
351 | 355 | END IF; |
|
352 | 356 | write_flag := false; |
|
353 | 357 | END IF; |
|
354 | 358 | |
|
355 | 359 | --- check for byte setup with write end, i.e., tBW |
|
356 | 360 | IF (NOW - tBBW_chk >= tBW) THEN |
|
357 | 361 | --- tBW OK, do nothing |
|
358 | 362 | ELSE |
|
359 | 363 | IF (TimingInfo) THEN |
|
360 | 364 | ASSERT false |
|
361 | 365 | REPORT "Upper Byte setup tBW violation"; |
|
362 | 366 | END IF; |
|
363 | 367 | |
|
364 | 368 | write_flag := false; |
|
365 | 369 | END IF; |
|
366 | 370 | |
|
367 | 371 | --- check for data setup with write end, i.e., tSD |
|
368 | 372 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
369 | 373 | --- tSD OK, do nothing |
|
370 | 374 | ELSE |
|
371 | 375 | IF (TimingInfo) THEN |
|
372 | 376 | ASSERT false |
|
373 | 377 | REPORT "Data setup tSD violation for Upper Byte Write"; |
|
374 | 378 | END IF; |
|
375 | 379 | |
|
376 | 380 | write_flag := false; |
|
377 | 381 | END IF; |
|
378 | 382 | |
|
379 | 383 | --- perform WRITE operation if no violations |
|
380 | 384 | |
|
381 | 385 | IF (write_flag = true) THEN |
|
382 | 386 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
383 | 387 | IF (BLE_b = '0') THEN |
|
384 | 388 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
385 | 389 | END IF; |
|
386 | 390 | |
|
387 | 391 | END IF; |
|
388 | 392 | |
|
389 | 393 | --- Reset timing variables |
|
390 | 394 | tAW_chk := A'LAST_EVENT; |
|
391 | 395 | tBBW_chk := NOW; |
|
392 | 396 | write_flag := true; |
|
393 | 397 | |
|
394 | 398 | END IF; |
|
395 | 399 | |
|
396 | 400 | END IF; |
|
397 | 401 | --- END OF WRITE |
|
398 | 402 | |
|
399 | 403 | IF (data_skew'EVENT AND read_enable /= '1') THEN |
|
400 | 404 | tSD_chk := NOW; |
|
401 | 405 | END IF; |
|
402 | 406 | |
|
403 | 407 | --- START of READ |
|
404 | 408 | |
|
405 | 409 | --- Tri-state the data bus if CE or OE disabled |
|
406 | 410 | IF (read_enable = '0' AND read_enable'EVENT) THEN |
|
407 | 411 | IF (OE_b'LAST_EVENT >= CE_b'LAST_EVENT) THEN |
|
408 | 412 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
409 | 413 | ELSIF (CE_b'LAST_EVENT > OE_b'LAST_EVENT) THEN |
|
410 | 414 | DQ <= (OTHERS => 'Z') after tHZOE; |
|
411 | 415 | END IF; |
|
412 | 416 | END IF; |
|
413 | 417 | |
|
414 | 418 | --- Address-controlled READ operation |
|
415 | 419 | IF (A'EVENT) THEN |
|
416 | 420 | IF (A'LAST_EVENT = CE_b'LAST_EVENT AND CE_b = '1') THEN |
|
417 | 421 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
418 | 422 | END IF; |
|
419 | 423 | |
|
420 | 424 | IF (NOW - tRC_chk >= tRC OR NOW - tRC_chk <= 0.1 ns OR tRC_chk = 0 ns) THEN |
|
421 | 425 | --- tRC OK, do nothing |
|
422 | 426 | ELSE |
|
423 | 427 | |
|
424 | 428 | IF (TimingInfo) THEN |
|
425 | 429 | ASSERT false |
|
426 | 430 | REPORT "Read Cycle time tRC violation"; |
|
427 | 431 | END IF; |
|
428 | 432 | |
|
429 | 433 | END IF; |
|
430 | 434 | |
|
431 | 435 | IF (read_enable = '1') THEN |
|
432 | 436 | |
|
433 | 437 | IF (BLE_b = '0') THEN |
|
434 | 438 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A))(7 DOWNTO 0) AFTER tAA; |
|
435 | 439 | END IF; |
|
436 | 440 | |
|
437 | 441 | IF (BHE_b = '0') THEN |
|
438 | 442 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A))(15 DOWNTO 8) AFTER tAA; |
|
439 | 443 | END IF; |
|
440 | 444 | |
|
441 | 445 | tRC_chk := NOW; |
|
442 | 446 | |
|
443 | 447 | END IF; |
|
444 | 448 | |
|
445 | 449 | IF (write_enable = '1') THEN |
|
446 | 450 | --- do nothing |
|
447 | 451 | END IF; |
|
448 | 452 | |
|
449 | 453 | END IF; |
|
450 | 454 | |
|
451 | 455 | IF (read_enable = '0' AND read_enable'EVENT) THEN |
|
452 | 456 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
453 | 457 | IF (NOW - tRC_chk >= tRC OR tRC_chk = 0 ns OR A'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
454 | 458 | --- tRC_chk needs to be reset when read ends |
|
455 | 459 | tRC_CHK := 0 ns; |
|
456 | 460 | ELSE |
|
457 | 461 | IF (TimingInfo) THEN |
|
458 | 462 | ASSERT false |
|
459 | 463 | REPORT "Read Cycle time tRC violation"; |
|
460 | 464 | END IF; |
|
461 | 465 | tRC_CHK := 0 ns; |
|
462 | 466 | END IF; |
|
463 | 467 | |
|
464 | 468 | END IF; |
|
465 | 469 | |
|
466 | 470 | --- READ operation triggered by CE/OE/BHE/BLE |
|
467 | 471 | IF (read_enable = '1' AND read_enable'EVENT) THEN |
|
468 | 472 | |
|
469 | 473 | tRC_chk := NOW; |
|
470 | 474 | |
|
471 | 475 | --- CE triggered READ |
|
472 | 476 | IF (CE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN -- changed rev2 |
|
473 | 477 | |
|
474 | 478 | IF (BLE_b = '0') THEN |
|
475 | 479 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; |
|
476 | 480 | END IF; |
|
477 | 481 | |
|
478 | 482 | IF (BHE_b = '0') THEN |
|
479 | 483 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; |
|
480 | 484 | END IF; |
|
481 | 485 | |
|
482 | 486 | END IF; |
|
483 | 487 | |
|
484 | 488 | |
|
485 | 489 | --- OE triggered READ |
|
486 | 490 | IF (OE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
487 | 491 | |
|
488 | 492 | -- if address or CE changes before OE such that tAA/tACE > tDOE |
|
489 | 493 | IF (CE_b'LAST_EVENT < tACE - tDOE AND A'LAST_EVENT < tAA - tDOE) THEN |
|
490 | 494 | |
|
491 | 495 | IF (A'LAST_EVENT < CE_b'LAST_EVENT) THEN |
|
492 | 496 | |
|
493 | 497 | accesstime := tAA-A'LAST_EVENT; |
|
494 | 498 | IF (BLE_b = '0') THEN |
|
495 | 499 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
496 | 500 | END IF; |
|
497 | 501 | |
|
498 | 502 | IF (BHE_b = '0') THEN |
|
499 | 503 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
500 | 504 | END IF; |
|
501 | 505 | |
|
502 | 506 | ELSE |
|
503 | 507 | accesstime := tACE-CE_b'LAST_EVENT; |
|
504 | 508 | IF (BLE_b = '0') THEN |
|
505 | 509 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
506 | 510 | END IF; |
|
507 | 511 | |
|
508 | 512 | IF (BHE_b = '0') THEN |
|
509 | 513 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
510 | 514 | END IF; |
|
511 | 515 | END IF; |
|
512 | 516 | |
|
513 | 517 | -- if address changes before OE such that tAA > tDOE |
|
514 | 518 | ELSIF (A'LAST_EVENT < tAA - tDOE) THEN |
|
515 | 519 | |
|
516 | 520 | accesstime := tAA-A'LAST_EVENT; |
|
517 | 521 | IF (BLE_b = '0') THEN |
|
518 | 522 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
519 | 523 | END IF; |
|
520 | 524 | |
|
521 | 525 | IF (BHE_b = '0') THEN |
|
522 | 526 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
523 | 527 | END IF; |
|
524 | 528 | |
|
525 | 529 | -- if CE changes before OE such that tACE > tDOE |
|
526 | 530 | ELSIF (CE_b'LAST_EVENT < tACE - tDOE) THEN |
|
527 | 531 | |
|
528 | 532 | accesstime := tACE-CE_b'LAST_EVENT; |
|
529 | 533 | IF (BLE_b = '0') THEN |
|
530 | 534 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
531 | 535 | END IF; |
|
532 | 536 | |
|
533 | 537 | IF (BHE_b = '0') THEN |
|
534 | 538 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
535 | 539 | END IF; |
|
536 | 540 | |
|
537 | 541 | -- if OE changes such that tDOE > tAA/tACE |
|
538 | 542 | ELSE |
|
539 | 543 | IF (BLE_b = '0') THEN |
|
540 | 544 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDOE; |
|
541 | 545 | END IF; |
|
542 | 546 | |
|
543 | 547 | IF (BHE_b = '0') THEN |
|
544 | 548 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDOE; |
|
545 | 549 | END IF; |
|
546 | 550 | |
|
547 | 551 | END IF; |
|
548 | 552 | |
|
549 | 553 | END IF; |
|
550 | 554 | --- END of OE triggered READ |
|
551 | 555 | |
|
552 | 556 | --- BLE/BHE triggered READ |
|
553 | 557 | IF (BLE_b'LAST_EVENT = read_enable'LAST_EVENT OR BHE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
554 | 558 | |
|
555 | 559 | -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE |
|
556 | 560 | IF (CE_b'LAST_EVENT < tACE - tDBE AND A'LAST_EVENT < tAA - tDBE) THEN |
|
557 | 561 | |
|
558 | 562 | IF (A'LAST_EVENT < BLE_b'LAST_EVENT) THEN |
|
559 | 563 | accesstime := tAA-A'LAST_EVENT; |
|
560 | 564 | |
|
561 | 565 | IF (BLE_b = '0') THEN |
|
562 | 566 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
563 | 567 | END IF; |
|
564 | 568 | |
|
565 | 569 | IF (BHE_b = '0') THEN |
|
566 | 570 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
567 | 571 | END IF; |
|
568 | 572 | |
|
569 | 573 | ELSE |
|
570 | 574 | accesstime := tACE-CE_b'LAST_EVENT; |
|
571 | 575 | |
|
572 | 576 | IF (BLE_b = '0') THEN |
|
573 | 577 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
574 | 578 | END IF; |
|
575 | 579 | |
|
576 | 580 | IF (BHE_b = '0') THEN |
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577 | 581 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
578 | 582 | END IF; |
|
579 | 583 | END IF; |
|
580 | 584 | |
|
581 | 585 | -- if address changes before BHE/BLE such that tAA > tDBE |
|
582 | 586 | ELSIF (A'LAST_EVENT < tAA - tDBE) THEN |
|
583 | 587 | accesstime := tAA-A'LAST_EVENT; |
|
584 | 588 | |
|
585 | 589 | IF (BLE_b = '0') THEN |
|
586 | 590 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
587 | 591 | END IF; |
|
588 | 592 | |
|
589 | 593 | IF (BHE_b = '0') THEN |
|
590 | 594 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
591 | 595 | END IF; |
|
592 | 596 | |
|
593 | 597 | -- if CE changes before BHE/BLE such that tACE > tDBE |
|
594 | 598 | ELSIF (CE_b'LAST_EVENT < tACE - tDBE) THEN |
|
595 | 599 | accesstime := tACE-CE_b'LAST_EVENT; |
|
596 | 600 | |
|
597 | 601 | IF (BLE_b = '0') THEN |
|
598 | 602 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
599 | 603 | END IF; |
|
600 | 604 | |
|
601 | 605 | IF (BHE_b = '0') THEN |
|
602 | 606 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
603 | 607 | END IF; |
|
604 | 608 | |
|
605 | 609 | -- if BHE/BLE changes such that tDBE > tAA/tACE |
|
606 | 610 | ELSE |
|
607 | 611 | IF (BLE_b = '0') THEN |
|
608 | 612 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; |
|
609 | 613 | END IF; |
|
610 | 614 | |
|
611 | 615 | IF (BHE_b = '0') THEN |
|
612 | 616 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; |
|
613 | 617 | END IF; |
|
614 | 618 | |
|
615 | 619 | END IF; |
|
616 | 620 | |
|
617 | 621 | END IF; |
|
618 | 622 | -- END of BHE/BLE controlled READ |
|
619 | 623 | |
|
620 | 624 | IF (WE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
621 | 625 | |
|
622 | 626 | IF (BLE_b = '0') THEN |
|
623 | 627 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; |
|
624 | 628 | END IF; |
|
625 | 629 | |
|
626 | 630 | IF (BHE_b = '0') THEN |
|
627 | 631 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; |
|
628 | 632 | END IF; |
|
629 | 633 | |
|
630 | 634 | END IF; |
|
631 | 635 | |
|
632 | 636 | END IF; |
|
633 | 637 | --- END OF CE/OE/BHE/BLE controlled READ |
|
634 | 638 | |
|
635 | 639 | --- If either BHE or BLE toggle during read mode |
|
636 | 640 | IF (BLE_b'EVENT AND BLE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN |
|
637 | 641 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; |
|
638 | 642 | END IF; |
|
639 | 643 | |
|
640 | 644 | IF (BHE_b'EVENT AND BHE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN |
|
641 | 645 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; |
|
642 | 646 | END IF; |
|
643 | 647 | |
|
644 | 648 | --- tri-state bus depending on BHE/BLE |
|
645 | 649 | IF (BLE_b'EVENT AND BLE_b = '1') THEN |
|
646 | 650 | DQ (7 DOWNTO 0) <= (OTHERS => 'Z') after tHZBE; |
|
647 | 651 | END IF; |
|
648 | 652 | |
|
649 | 653 | IF (BHE_b'EVENT AND BHE_b = '1') THEN |
|
650 | 654 | DQ (15 DOWNTO 8) <= (OTHERS => 'Z') after tHZBE; |
|
651 | 655 | END IF; |
|
652 | 656 | |
|
653 | 657 | WAIT ON write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew, address_skew; |
|
654 | 658 | |
|
655 | 659 | END PROCESS; |
|
656 | 660 | |
|
657 | 661 | |
|
658 | 662 | END behave_arch; |
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