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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 3 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- Author : Jean-christophe Pellion | |||
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------- | |||
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22 | LIBRARY IEEE; | |||
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23 | USE IEEE.numeric_std.ALL; | |||
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24 | USE IEEE.std_logic_1164.ALL; | |||
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25 | LIBRARY grlib; | |||
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26 | USE grlib.amba.ALL; | |||
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27 | USE grlib.stdlib.ALL; | |||
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28 | LIBRARY techmap; | |||
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29 | USE techmap.gencomp.ALL; | |||
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30 | LIBRARY gaisler; | |||
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31 | USE gaisler.memctrl.ALL; | |||
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32 | USE gaisler.leon3.ALL; | |||
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33 | USE gaisler.uart.ALL; | |||
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34 | USE gaisler.misc.ALL; | |||
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35 | USE gaisler.spacewire.ALL; | |||
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36 | LIBRARY esa; | |||
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37 | USE esa.memoryctrl.ALL; | |||
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38 | LIBRARY lpp; | |||
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39 | USE lpp.lpp_memory.ALL; | |||
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40 | USE lpp.lpp_ad_conv.ALL; | |||
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |||
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |||
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43 | USE lpp.iir_filter.ALL; | |||
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44 | USE lpp.general_purpose.ALL; | |||
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45 | USE lpp.lpp_lfr_time_management.ALL; | |||
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |||
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47 | ||||
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48 | ENTITY LFR_em IS | |||
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49 | ||||
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50 | PORT ( | |||
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51 | clk100MHz : IN STD_ULOGIC; | |||
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52 | clk49_152MHz : IN STD_ULOGIC; | |||
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53 | reset : IN STD_ULOGIC; | |||
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54 | ||||
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55 | errorn : OUT STD_ULOGIC; | |||
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56 | -- UART AHB --------------------------------------------------------------- | |||
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57 | ahbrxd : IN STD_ULOGIC; -- DSU rx data | |||
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58 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data | |||
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59 | -- UART APB --------------------------------------------------------------- | |||
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60 | urxd1 : IN STD_ULOGIC; -- UART1 rx data | |||
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61 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data | |||
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62 | -- RAM -------------------------------------------------------------------- | |||
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63 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |||
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64 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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65 | nSRAM_BE0 : OUT STD_LOGIC; | |||
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66 | nSRAM_BE1 : OUT STD_LOGIC; | |||
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67 | nSRAM_BE2 : OUT STD_LOGIC; | |||
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68 | nSRAM_BE3 : OUT STD_LOGIC; | |||
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69 | nSRAM_WE : OUT STD_LOGIC; | |||
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70 | nSRAM_CE : OUT STD_LOGIC; | |||
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71 | nSRAM_OE : OUT STD_LOGIC; | |||
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72 | -- SPW -------------------------------------------------------------------- | |||
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73 | spw1_din : IN STD_LOGIC; | |||
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74 | spw1_sin : IN STD_LOGIC; | |||
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75 | spw1_dout : OUT STD_LOGIC; | |||
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76 | spw1_sout : OUT STD_LOGIC; | |||
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77 | spw2_din : IN STD_LOGIC; | |||
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78 | spw2_sin : IN STD_LOGIC; | |||
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79 | spw2_dout : OUT STD_LOGIC; | |||
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80 | spw2_sout : OUT STD_LOGIC; | |||
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81 | -- ADC -------------------------------------------------------------------- | |||
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82 | bias_fail_sw : OUT STD_LOGIC; | |||
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83 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
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84 | ADC_smpclk : OUT STD_LOGIC; | |||
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85 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); | |||
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86 | --------------------------------------------------------------------------- | |||
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87 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) | |||
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88 | ); | |||
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89 | ||||
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90 | END LFR_em; | |||
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91 | ||||
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92 | ||||
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93 | ARCHITECTURE beh OF LFR_em IS | |||
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94 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |||
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95 | SIGNAL clk_25 : STD_LOGIC := '0'; | |||
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96 | SIGNAL clk_24 : STD_LOGIC := '0'; | |||
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97 | ----------------------------------------------------------------------------- | |||
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98 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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99 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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100 | -- | |||
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101 | -- UART AHB --------------------------------------------------------------- | |||
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102 | --SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |||
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103 | --SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |||
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104 | ||||
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105 | -- UART APB --------------------------------------------------------------- | |||
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106 | --SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |||
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107 | --SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |||
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108 | -- | |||
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109 | -- CONSTANTS | |||
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110 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |||
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111 | -- | |||
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112 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |||
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113 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |||
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114 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |||
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115 | ||||
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116 | SIGNAL apbi_ext : apb_slv_in_type; | |||
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117 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |||
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118 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |||
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119 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |||
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120 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |||
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121 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |||
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122 | ||||
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123 | -- Spacewire signals | |||
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124 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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125 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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126 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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127 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |||
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128 | SIGNAL spw_rxclkn : STD_ULOGIC; | |||
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129 | SIGNAL spw_clk : STD_LOGIC; | |||
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130 | SIGNAL swni : grspw_in_type; | |||
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131 | SIGNAL swno : grspw_out_type; | |||
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132 | -- SIGNAL clkmn : STD_ULOGIC; | |||
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133 | -- SIGNAL txclk : STD_ULOGIC; | |||
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134 | ||||
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135 | --GPIO | |||
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136 | SIGNAL gpioi : gpio_in_type; | |||
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137 | SIGNAL gpioo : gpio_out_type; | |||
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138 | ||||
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139 | -- AD Converter ADS7886 | |||
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140 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |||
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141 | SIGNAL sample_val : STD_LOGIC; | |||
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142 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |||
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143 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |||
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144 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
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145 | ||||
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146 | --SIGNAL bias_fail_sw_sig : STD_LOGIC; | |||
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147 | ||||
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148 | ----------------------------------------------------------------------------- | |||
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149 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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150 | ||||
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151 | ----------------------------------------------------------------------------- | |||
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152 | SIGNAL rstn : STD_LOGIC; | |||
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153 | BEGIN -- beh | |||
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154 | ||||
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155 | ----------------------------------------------------------------------------- | |||
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156 | -- CLK | |||
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157 | ----------------------------------------------------------------------------- | |||
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158 | rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN); | |||
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159 | ||||
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160 | PROCESS(clk100MHz) | |||
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161 | BEGIN | |||
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162 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN | |||
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163 | clk_50_s <= NOT clk_50_s; | |||
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164 | END IF; | |||
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165 | END PROCESS; | |||
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166 | ||||
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167 | PROCESS(clk_50_s) | |||
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168 | BEGIN | |||
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169 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |||
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170 | clk_25 <= NOT clk_25; | |||
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171 | END IF; | |||
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172 | END PROCESS; | |||
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173 | ||||
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174 | PROCESS(clk49_152MHz) | |||
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175 | BEGIN | |||
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176 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN | |||
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177 | clk_24 <= NOT clk_24; | |||
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178 | END IF; | |||
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179 | END PROCESS; | |||
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180 | ||||
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181 | ----------------------------------------------------------------------------- | |||
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182 | ||||
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183 | PROCESS (clk_25, rstn) | |||
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184 | BEGIN -- PROCESS | |||
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185 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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186 | led(0) <= '0'; | |||
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187 | led(1) <= '0'; | |||
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188 | led(2) <= '0'; | |||
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189 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |||
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190 | led(0) <= '0'; | |||
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191 | led(1) <= '1'; | |||
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192 | led(2) <= '1'; | |||
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193 | END IF; | |||
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194 | END PROCESS; | |||
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195 | ||||
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196 | -- | |||
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197 | leon3_soc_1 : leon3_soc | |||
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198 | GENERIC MAP ( | |||
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199 | fabtech => apa3e, | |||
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200 | memtech => apa3e, | |||
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201 | padtech => inferred, | |||
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202 | clktech => inferred, | |||
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203 | disas => 0, | |||
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204 | dbguart => 0, | |||
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205 | pclow => 2, | |||
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206 | clk_freq => 25000, | |||
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207 | NB_CPU => 1, | |||
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208 | ENABLE_FPU => 1, | |||
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209 | FPU_NETLIST => 0, | |||
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210 | ENABLE_DSU => 1, | |||
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211 | ENABLE_AHB_UART => 1, | |||
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212 | ENABLE_APB_UART => 1, | |||
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213 | ENABLE_IRQMP => 1, | |||
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214 | ENABLE_GPT => 1, | |||
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215 | NB_AHB_MASTER => NB_AHB_MASTER, | |||
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216 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |||
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217 | NB_APB_SLAVE => NB_APB_SLAVE) | |||
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218 | PORT MAP ( | |||
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219 | clk => clk_25, | |||
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220 | reset => rstn, | |||
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221 | errorn => errorn, | |||
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222 | ahbrxd => ahbrxd, | |||
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223 | ahbtxd => ahbtxd, | |||
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224 | urxd1 => urxd1, | |||
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225 | utxd1 => utxd1, | |||
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226 | address => address, | |||
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227 | data => data, | |||
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228 | nSRAM_BE0 => nSRAM_BE0, | |||
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229 | nSRAM_BE1 => nSRAM_BE1, | |||
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230 | nSRAM_BE2 => nSRAM_BE2, | |||
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231 | nSRAM_BE3 => nSRAM_BE3, | |||
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232 | nSRAM_WE => nSRAM_WE, | |||
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233 | nSRAM_CE => nSRAM_CE, | |||
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234 | nSRAM_OE => nSRAM_OE, | |||
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235 | ||||
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236 | apbi_ext => apbi_ext, | |||
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237 | apbo_ext => apbo_ext, | |||
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238 | ahbi_s_ext => ahbi_s_ext, | |||
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239 | ahbo_s_ext => ahbo_s_ext, | |||
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240 | ahbi_m_ext => ahbi_m_ext, | |||
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241 | ahbo_m_ext => ahbo_m_ext); | |||
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242 | ||||
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243 | ------------------------------------------------------------------------------- | |||
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244 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |||
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245 | ------------------------------------------------------------------------------- | |||
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246 | apb_lfr_time_management_1 : apb_lfr_time_management | |||
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247 | GENERIC MAP ( | |||
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248 | pindex => 6, | |||
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249 | paddr => 6, | |||
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250 | pmask => 16#fff#, | |||
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251 | pirq => 12, | |||
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252 | nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 | |||
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253 | PORT MAP ( | |||
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254 | clk25MHz => clk_25, | |||
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255 | clk49_152MHz => clk_24, -- 49.152MHz/2 | |||
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256 | resetn => rstn, | |||
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257 | grspw_tick => swno.tickout, | |||
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258 | apbi => apbi_ext, | |||
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259 | apbo => apbo_ext(6), | |||
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260 | coarse_time => coarse_time, | |||
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261 | fine_time => fine_time); | |||
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262 | ||||
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263 | ----------------------------------------------------------------------- | |||
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264 | --- SpaceWire -------------------------------------------------------- | |||
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265 | ----------------------------------------------------------------------- | |||
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266 | ||||
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267 | -- SPW_EN <= '1'; | |||
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268 | ||||
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269 | spw_clk <= clk_50_s; | |||
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270 | spw_rxtxclk <= spw_clk; | |||
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271 | spw_rxclkn <= NOT spw_rxtxclk; | |||
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272 | ||||
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273 | -- PADS for SPW1 | |||
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274 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |||
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275 | PORT MAP (spw1_din, dtmp(0)); | |||
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276 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |||
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277 | PORT MAP (spw1_sin, stmp(0)); | |||
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278 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |||
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279 | PORT MAP (spw1_dout, swno.d(0)); | |||
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280 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |||
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281 | PORT MAP (spw1_sout, swno.s(0)); | |||
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282 | -- PADS FOR SPW2 | |||
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283 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |||
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284 | PORT MAP (spw2_sin, dtmp(1)); | |||
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285 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |||
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286 | PORT MAP (spw2_din, stmp(1)); | |||
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287 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |||
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288 | PORT MAP (spw2_dout, swno.d(1)); | |||
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289 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |||
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290 | PORT MAP (spw2_sout, swno.s(1)); | |||
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291 | ||||
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292 | -- GRSPW PHY | |||
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293 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |||
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294 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |||
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295 | spw_phy0 : grspw_phy | |||
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296 | GENERIC MAP( | |||
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297 | tech => apa3e, | |||
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298 | rxclkbuftype => 1, | |||
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299 | scantest => 0) | |||
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300 | PORT MAP( | |||
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301 | rxrst => swno.rxrst, | |||
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302 | di => dtmp(j), | |||
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303 | si => stmp(j), | |||
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304 | rxclko => spw_rxclk(j), | |||
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305 | do => swni.d(j), | |||
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306 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |||
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307 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |||
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308 | END GENERATE spw_inputloop; | |||
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309 | ||||
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310 | -- SPW core | |||
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311 | sw0 : grspwm GENERIC MAP( | |||
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312 | tech => apa3e, | |||
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313 | hindex => 1, | |||
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314 | pindex => 5, | |||
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315 | paddr => 5, | |||
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316 | pirq => 11, | |||
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317 | sysfreq => 25000, -- CPU_FREQ | |||
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318 | rmap => 1, | |||
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319 | rmapcrc => 1, | |||
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320 | fifosize1 => 16, | |||
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321 | fifosize2 => 16, | |||
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322 | rxclkbuftype => 1, | |||
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323 | rxunaligned => 0, | |||
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324 | rmapbufs => 4, | |||
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325 | ft => 0, | |||
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326 | netlist => 0, | |||
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327 | ports => 2, | |||
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328 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |||
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329 | memtech => apa3e, | |||
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330 | destkey => 2, | |||
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331 | spwcore => 1 | |||
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332 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |||
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333 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |||
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334 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |||
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335 | ) | |||
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336 | PORT MAP(rstn, clk_25, spw_rxclk(0), | |||
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337 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |||
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338 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |||
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339 | swni, swno); | |||
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340 | ||||
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341 | swni.tickin <= '0'; | |||
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342 | swni.rmapen <= '1'; | |||
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343 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |||
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344 | swni.tickinraw <= '0'; | |||
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345 | swni.timein <= (OTHERS => '0'); | |||
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346 | swni.dcrstval <= (OTHERS => '0'); | |||
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347 | swni.timerrstval <= (OTHERS => '0'); | |||
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348 | ||||
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349 | ------------------------------------------------------------------------------- | |||
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350 | -- LFR ------------------------------------------------------------------------ | |||
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351 | ------------------------------------------------------------------------------- | |||
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352 | lpp_lfr_1 : lpp_lfr_WFP_nMS | |||
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353 | GENERIC MAP ( | |||
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354 | Mem_use => use_RAM, | |||
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355 | nb_data_by_buffer_size => 32, | |||
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356 | nb_word_by_buffer_size => 30, | |||
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357 | nb_snapshot_param_size => 32, | |||
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358 | delta_vector_size => 32, | |||
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359 | delta_vector_size_f0_2 => 7, -- log2(96) | |||
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360 | pindex => 15, | |||
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361 | paddr => 15, | |||
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362 | pmask => 16#fff#, | |||
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363 | pirq_ms => 6, | |||
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364 | pirq_wfp => 14, | |||
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365 | hindex => 2, | |||
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366 | top_lfr_version => X"010000") -- aa.bb.cc version | |||
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367 | -- AA : BOARD NUMBER | |||
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368 | -- 0 => MINI_LFR | |||
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369 | -- 1 => EM | |||
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370 | PORT MAP ( | |||
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371 | clk => clk_25, | |||
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372 | rstn => rstn, | |||
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373 | sample_B => sample(2 DOWNTO 0), | |||
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374 | sample_E => sample(7 DOWNTO 3), | |||
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375 | sample_val => sample_val, | |||
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376 | apbi => apbi_ext, | |||
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377 | apbo => apbo_ext(15), | |||
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378 | ahbi => ahbi_m_ext, | |||
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379 | ahbo => ahbo_m_ext(2), | |||
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380 | coarse_time => coarse_time, | |||
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381 | fine_time => fine_time, | |||
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382 | data_shaping_BW => bias_fail_sw, | |||
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383 | observation_reg => observation_reg); | |||
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384 | ||||
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385 | ----------------------------------------------------------------------------- | |||
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386 | -- | |||
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387 | ----------------------------------------------------------------------------- | |||
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388 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 | |||
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389 | GENERIC MAP ( | |||
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390 | ChanelCount => 8, | |||
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391 | ncycle_cnv_high => 40, -- TODO : 79 | |||
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392 | ncycle_cnv => 250) -- TODO : 500 | |||
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393 | PORT MAP ( | |||
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394 | cnv_clk => clk_24, -- TODO : 49.152 | |||
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395 | cnv_rstn => rstn, -- ok | |||
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396 | cnv => ADC_smpclk, -- ok | |||
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397 | clk => clk_25, -- ok | |||
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398 | rstn => rstn, -- ok | |||
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399 | ADC_data => ADC_data, -- ok | |||
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400 | ADC_nOE => ADC_OEB_bar_CH, -- ok | |||
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401 | sample => sample, -- ok | |||
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402 | sample_val => sample_val); -- ok | |||
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403 | ||||
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404 | END beh; No newline at end of file |
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1 | LIBRARY ieee; | |||
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2 | USE ieee.std_logic_1164.ALL; | |||
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3 | USE ieee.numeric_std.ALL; | |||
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4 | ||||
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5 | LIBRARY lpp; | |||
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6 | USE lpp.lpp_ad_conv.ALL; | |||
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7 | USE lpp.iir_filter.ALL; | |||
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8 | USE lpp.FILTERcfg.ALL; | |||
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9 | USE lpp.lpp_memory.ALL; | |||
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10 | USE lpp.lpp_waveform_pkg.ALL; | |||
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11 | USE lpp.lpp_dma_pkg.ALL; | |||
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12 | USE lpp.lpp_top_lfr_pkg.ALL; | |||
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13 | USE lpp.lpp_lfr_pkg.ALL; | |||
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14 | USE lpp.general_purpose.ALL; | |||
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15 | ||||
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16 | LIBRARY techmap; | |||
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17 | USE techmap.gencomp.ALL; | |||
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18 | ||||
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19 | LIBRARY grlib; | |||
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20 | USE grlib.amba.ALL; | |||
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21 | USE grlib.stdlib.ALL; | |||
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22 | USE grlib.devices.ALL; | |||
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23 | USE GRLIB.DMA2AHB_Package.ALL; | |||
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24 | ||||
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25 | ENTITY lpp_lfr_WFP_nMS IS | |||
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26 | GENERIC ( | |||
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27 | Mem_use : INTEGER := use_RAM; | |||
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28 | nb_data_by_buffer_size : INTEGER := 11; | |||
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29 | nb_word_by_buffer_size : INTEGER := 11; | |||
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30 | nb_snapshot_param_size : INTEGER := 11; | |||
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31 | delta_vector_size : INTEGER := 20; | |||
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32 | delta_vector_size_f0_2 : INTEGER := 7; | |||
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33 | ||||
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34 | pindex : INTEGER := 4; | |||
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35 | paddr : INTEGER := 4; | |||
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36 | pmask : INTEGER := 16#fff#; | |||
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37 | pirq_ms : INTEGER := 0; | |||
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38 | pirq_wfp : INTEGER := 1; | |||
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39 | ||||
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40 | hindex : INTEGER := 2; | |||
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41 | ||||
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42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |||
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43 | ||||
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44 | ); | |||
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45 | PORT ( | |||
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46 | clk : IN STD_LOGIC; | |||
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47 | rstn : IN STD_LOGIC; | |||
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48 | -- SAMPLE | |||
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49 | sample_B : IN Samples14v(2 DOWNTO 0); | |||
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50 | sample_E : IN Samples14v(4 DOWNTO 0); | |||
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51 | sample_val : IN STD_LOGIC; | |||
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52 | -- APB | |||
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53 | apbi : IN apb_slv_in_type; | |||
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54 | apbo : OUT apb_slv_out_type; | |||
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55 | -- AHB | |||
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56 | ahbi : IN AHB_Mst_In_Type; | |||
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57 | ahbo : OUT AHB_Mst_Out_Type; | |||
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58 | -- TIME | |||
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59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |||
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60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |||
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61 | -- | |||
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62 | data_shaping_BW : OUT STD_LOGIC; | |||
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63 | -- | |||
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64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
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65 | ||||
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66 | --debug | |||
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67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
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68 | --debug_f0_data_valid : OUT STD_LOGIC; | |||
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69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
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70 | --debug_f1_data_valid : OUT STD_LOGIC; | |||
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71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
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72 | --debug_f2_data_valid : OUT STD_LOGIC; | |||
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73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
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74 | --debug_f3_data_valid : OUT STD_LOGIC; | |||
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75 | ||||
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76 | ---- debug FIFO_IN | |||
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77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |||
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79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |||
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81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |||
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83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |||
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85 | ||||
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86 | ----debug FIFO OUT | |||
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87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |||
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89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |||
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91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |||
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93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |||
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95 | ||||
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96 | ----debug DMA IN | |||
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97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |||
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99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |||
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101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |||
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103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |||
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105 | ); | |||
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106 | END lpp_lfr_WFP_nMS; | |||
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107 | ||||
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108 | ARCHITECTURE beh OF lpp_lfr_WFP_nMS IS | |||
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109 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |||
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110 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |||
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111 | -- | |||
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112 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |||
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113 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |||
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114 | SIGNAL data_shaping_R0 : STD_LOGIC; | |||
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115 | SIGNAL data_shaping_R1 : STD_LOGIC; | |||
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116 | -- | |||
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117 | -- SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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118 | -- SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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119 | -- SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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120 | -- | |||
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121 | SIGNAL sample_f0_val : STD_LOGIC; | |||
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122 | SIGNAL sample_f1_val : STD_LOGIC; | |||
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123 | SIGNAL sample_f2_val : STD_LOGIC; | |||
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124 | SIGNAL sample_f3_val : STD_LOGIC; | |||
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125 | -- | |||
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126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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130 | -- | |||
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131 | --SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
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132 | --SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
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133 | --SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
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134 | ||||
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135 | -- SM | |||
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136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |||
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137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |||
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138 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |||
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139 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |||
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140 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |||
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141 | SIGNAL error_bad_component_error : STD_LOGIC; | |||
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142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |||
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144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |||
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145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |||
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146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |||
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147 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |||
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148 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |||
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149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |||
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150 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |||
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151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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152 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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155 | ||||
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156 | -- WFP | |||
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157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |||
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162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |||
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163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |||
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164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |||
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165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |||
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166 | ||||
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167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |||
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168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |||
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169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
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170 | SIGNAL enable_f0 : STD_LOGIC; | |||
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171 | SIGNAL enable_f1 : STD_LOGIC; | |||
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172 | SIGNAL enable_f2 : STD_LOGIC; | |||
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173 | SIGNAL enable_f3 : STD_LOGIC; | |||
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174 | SIGNAL burst_f0 : STD_LOGIC; | |||
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175 | SIGNAL burst_f1 : STD_LOGIC; | |||
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176 | SIGNAL burst_f2 : STD_LOGIC; | |||
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177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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181 | ||||
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182 | SIGNAL run : STD_LOGIC; | |||
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183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |||
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184 | ||||
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185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |||
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188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |||
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189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |||
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190 | --f1 | |||
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191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |||
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194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |||
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195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |||
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196 | --f2 | |||
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197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |||
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200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |||
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201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |||
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202 | --f3 | |||
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203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |||
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206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |||
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207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |||
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208 | ||||
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209 | ----------------------------------------------------------------------------- | |||
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210 | -- | |||
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211 | ----------------------------------------------------------------------------- | |||
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212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |||
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214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |||
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215 | --f1 | |||
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216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |||
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218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |||
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219 | --f2 | |||
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220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |||
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222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |||
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223 | --f3 | |||
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224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |||
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226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |||
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227 | ||||
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228 | ----------------------------------------------------------------------------- | |||
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229 | -- DMA RR | |||
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230 | ----------------------------------------------------------------------------- | |||
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231 | SIGNAL dma_sel_valid : STD_LOGIC; | |||
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232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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236 | ||||
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237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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239 | ||||
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240 | ----------------------------------------------------------------------------- | |||
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241 | -- DMA_REG | |||
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242 | ----------------------------------------------------------------------------- | |||
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243 | SIGNAL ongoing_reg : STD_LOGIC; | |||
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244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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245 | SIGNAL dma_send_reg : STD_LOGIC; | |||
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246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |||
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247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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249 | ||||
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250 | ||||
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251 | ----------------------------------------------------------------------------- | |||
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252 | -- DMA | |||
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253 | ----------------------------------------------------------------------------- | |||
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254 | SIGNAL dma_send : STD_LOGIC; | |||
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255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |||
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256 | SIGNAL dma_done : STD_LOGIC; | |||
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257 | SIGNAL dma_ren : STD_LOGIC; | |||
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258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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261 | ||||
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262 | ----------------------------------------------------------------------------- | |||
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263 | -- DEBUG | |||
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264 | ----------------------------------------------------------------------------- | |||
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265 | -- | |||
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266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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270 | ||||
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271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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279 | ||||
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280 | ----------------------------------------------------------------------------- | |||
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281 | -- MS | |||
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282 | ----------------------------------------------------------------------------- | |||
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283 | ||||
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284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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286 | SIGNAL data_ms_valid : STD_LOGIC; | |||
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287 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |||
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288 | SIGNAL data_ms_ren : STD_LOGIC; | |||
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289 | SIGNAL data_ms_done : STD_LOGIC; | |||
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290 | ||||
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291 | SIGNAL run_ms : STD_LOGIC; | |||
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292 | --SIGNAL ms_softandhard_rstn : STD_LOGIC; | |||
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293 | ||||
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294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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295 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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298 | ||||
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299 | ||||
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300 | BEGIN | |||
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301 | ||||
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302 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |||
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303 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |||
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304 | ||||
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305 | all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |||
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306 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |||
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307 | END GENERATE all_channel; | |||
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308 | ||||
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309 | ----------------------------------------------------------------------------- | |||
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310 | lpp_lfr_filter_1 : lpp_lfr_filter | |||
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311 | GENERIC MAP ( | |||
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312 | Mem_use => Mem_use) | |||
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313 | PORT MAP ( | |||
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314 | sample => sample_s, | |||
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315 | sample_val => sample_val, | |||
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316 | clk => clk, | |||
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317 | rstn => rstn, | |||
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318 | data_shaping_SP0 => data_shaping_SP0, | |||
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319 | data_shaping_SP1 => data_shaping_SP1, | |||
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320 | data_shaping_R0 => data_shaping_R0, | |||
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321 | data_shaping_R1 => data_shaping_R1, | |||
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322 | sample_f0_val => sample_f0_val, | |||
|
323 | sample_f1_val => sample_f1_val, | |||
|
324 | sample_f2_val => sample_f2_val, | |||
|
325 | sample_f3_val => sample_f3_val, | |||
|
326 | sample_f0_wdata => sample_f0_data, | |||
|
327 | sample_f1_wdata => sample_f1_data, | |||
|
328 | sample_f2_wdata => sample_f2_data, | |||
|
329 | sample_f3_wdata => sample_f3_data); | |||
|
330 | ||||
|
331 | ----------------------------------------------------------------------------- | |||
|
332 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |||
|
333 | GENERIC MAP ( | |||
|
334 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |||
|
335 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |||
|
336 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
337 | delta_vector_size => delta_vector_size, | |||
|
338 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |||
|
339 | pindex => pindex, | |||
|
340 | paddr => paddr, | |||
|
341 | pmask => pmask, | |||
|
342 | pirq_ms => pirq_ms, | |||
|
343 | pirq_wfp => pirq_wfp, | |||
|
344 | top_lfr_version => top_lfr_version) | |||
|
345 | PORT MAP ( | |||
|
346 | HCLK => clk, | |||
|
347 | HRESETn => rstn, | |||
|
348 | apbi => apbi, | |||
|
349 | apbo => apbo, | |||
|
350 | ||||
|
351 | run_ms => run_ms, | |||
|
352 | ||||
|
353 | ready_matrix_f0_0 => ready_matrix_f0_0, | |||
|
354 | ready_matrix_f0_1 => ready_matrix_f0_1, | |||
|
355 | ready_matrix_f1 => ready_matrix_f1, | |||
|
356 | ready_matrix_f2 => ready_matrix_f2, | |||
|
357 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |||
|
358 | error_bad_component_error => error_bad_component_error, | |||
|
359 | debug_reg => debug_reg, | |||
|
360 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |||
|
361 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |||
|
362 | status_ready_matrix_f1 => status_ready_matrix_f1, | |||
|
363 | status_ready_matrix_f2 => status_ready_matrix_f2, | |||
|
364 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |||
|
365 | status_error_bad_component_error => status_error_bad_component_error, | |||
|
366 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
|
367 | config_active_interruption_onError => config_active_interruption_onError, | |||
|
368 | ||||
|
369 | matrix_time_f0_0 => matrix_time_f0_0, | |||
|
370 | matrix_time_f0_1 => matrix_time_f0_1, | |||
|
371 | matrix_time_f1 => matrix_time_f1, | |||
|
372 | matrix_time_f2 => matrix_time_f2, | |||
|
373 | ||||
|
374 | addr_matrix_f0_0 => addr_matrix_f0_0, | |||
|
375 | addr_matrix_f0_1 => addr_matrix_f0_1, | |||
|
376 | addr_matrix_f1 => addr_matrix_f1, | |||
|
377 | addr_matrix_f2 => addr_matrix_f2, | |||
|
378 | status_full => status_full, | |||
|
379 | status_full_ack => status_full_ack, | |||
|
380 | status_full_err => status_full_err, | |||
|
381 | status_new_err => status_new_err, | |||
|
382 | data_shaping_BW => data_shaping_BW, | |||
|
383 | data_shaping_SP0 => data_shaping_SP0, | |||
|
384 | data_shaping_SP1 => data_shaping_SP1, | |||
|
385 | data_shaping_R0 => data_shaping_R0, | |||
|
386 | data_shaping_R1 => data_shaping_R1, | |||
|
387 | delta_snapshot => delta_snapshot, | |||
|
388 | delta_f0 => delta_f0, | |||
|
389 | delta_f0_2 => delta_f0_2, | |||
|
390 | delta_f1 => delta_f1, | |||
|
391 | delta_f2 => delta_f2, | |||
|
392 | nb_data_by_buffer => nb_data_by_buffer, | |||
|
393 | nb_word_by_buffer => nb_word_by_buffer, | |||
|
394 | nb_snapshot_param => nb_snapshot_param, | |||
|
395 | enable_f0 => enable_f0, | |||
|
396 | enable_f1 => enable_f1, | |||
|
397 | enable_f2 => enable_f2, | |||
|
398 | enable_f3 => enable_f3, | |||
|
399 | burst_f0 => burst_f0, | |||
|
400 | burst_f1 => burst_f1, | |||
|
401 | burst_f2 => burst_f2, | |||
|
402 | run => run, | |||
|
403 | addr_data_f0 => addr_data_f0, | |||
|
404 | addr_data_f1 => addr_data_f1, | |||
|
405 | addr_data_f2 => addr_data_f2, | |||
|
406 | addr_data_f3 => addr_data_f3, | |||
|
407 | start_date => start_date, | |||
|
408 | --------------------------------------------------------------------------- | |||
|
409 | debug_reg0 => debug_reg0, | |||
|
410 | debug_reg1 => debug_reg1, | |||
|
411 | debug_reg2 => debug_reg2, | |||
|
412 | debug_reg3 => debug_reg3, | |||
|
413 | debug_reg4 => debug_reg4, | |||
|
414 | debug_reg5 => debug_reg5, | |||
|
415 | debug_reg6 => debug_reg6, | |||
|
416 | debug_reg7 => debug_reg7); | |||
|
417 | ||||
|
418 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |||
|
419 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |||
|
420 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | |||
|
421 | ----------------------------------------------------------------------------- | |||
|
422 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |||
|
423 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |||
|
424 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |||
|
425 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |||
|
426 | ||||
|
427 | ||||
|
428 | ----------------------------------------------------------------------------- | |||
|
429 | lpp_waveform_1 : lpp_waveform | |||
|
430 | GENERIC MAP ( | |||
|
431 | tech => inferred, | |||
|
432 | data_size => 6*16, | |||
|
433 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |||
|
434 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |||
|
435 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
436 | delta_vector_size => delta_vector_size, | |||
|
437 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |||
|
438 | ) | |||
|
439 | PORT MAP ( | |||
|
440 | clk => clk, | |||
|
441 | rstn => rstn, | |||
|
442 | ||||
|
443 | reg_run => run, | |||
|
444 | reg_start_date => start_date, | |||
|
445 | reg_delta_snapshot => delta_snapshot, | |||
|
446 | reg_delta_f0 => delta_f0, | |||
|
447 | reg_delta_f0_2 => delta_f0_2, | |||
|
448 | reg_delta_f1 => delta_f1, | |||
|
449 | reg_delta_f2 => delta_f2, | |||
|
450 | ||||
|
451 | enable_f0 => enable_f0, | |||
|
452 | enable_f1 => enable_f1, | |||
|
453 | enable_f2 => enable_f2, | |||
|
454 | enable_f3 => enable_f3, | |||
|
455 | burst_f0 => burst_f0, | |||
|
456 | burst_f1 => burst_f1, | |||
|
457 | burst_f2 => burst_f2, | |||
|
458 | ||||
|
459 | nb_data_by_buffer => nb_data_by_buffer, | |||
|
460 | nb_word_by_buffer => nb_word_by_buffer, | |||
|
461 | nb_snapshot_param => nb_snapshot_param, | |||
|
462 | status_full => status_full, | |||
|
463 | status_full_ack => status_full_ack, | |||
|
464 | status_full_err => status_full_err, | |||
|
465 | status_new_err => status_new_err, | |||
|
466 | ||||
|
467 | coarse_time => coarse_time, | |||
|
468 | fine_time => fine_time, | |||
|
469 | ||||
|
470 | --f0 | |||
|
471 | addr_data_f0 => addr_data_f0, | |||
|
472 | data_f0_in_valid => sample_f0_val, | |||
|
473 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug | |||
|
474 | --f1 | |||
|
475 | addr_data_f1 => addr_data_f1, | |||
|
476 | data_f1_in_valid => sample_f1_val, | |||
|
477 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, | |||
|
478 | --f2 | |||
|
479 | addr_data_f2 => addr_data_f2, | |||
|
480 | data_f2_in_valid => sample_f2_val, | |||
|
481 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, | |||
|
482 | --f3 | |||
|
483 | addr_data_f3 => addr_data_f3, | |||
|
484 | data_f3_in_valid => sample_f3_val, | |||
|
485 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, | |||
|
486 | -- OUTPUT -- DMA interface | |||
|
487 | --f0 | |||
|
488 | data_f0_addr_out => data_f0_addr_out_s, | |||
|
489 | data_f0_data_out => data_f0_data_out, | |||
|
490 | data_f0_data_out_valid => data_f0_data_out_valid_s, | |||
|
491 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |||
|
492 | data_f0_data_out_ren => data_f0_data_out_ren, | |||
|
493 | --f1 | |||
|
494 | data_f1_addr_out => data_f1_addr_out_s, | |||
|
495 | data_f1_data_out => data_f1_data_out, | |||
|
496 | data_f1_data_out_valid => data_f1_data_out_valid_s, | |||
|
497 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, | |||
|
498 | data_f1_data_out_ren => data_f1_data_out_ren, | |||
|
499 | --f2 | |||
|
500 | data_f2_addr_out => data_f2_addr_out_s, | |||
|
501 | data_f2_data_out => data_f2_data_out, | |||
|
502 | data_f2_data_out_valid => data_f2_data_out_valid_s, | |||
|
503 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, | |||
|
504 | data_f2_data_out_ren => data_f2_data_out_ren, | |||
|
505 | --f3 | |||
|
506 | data_f3_addr_out => data_f3_addr_out_s, | |||
|
507 | data_f3_data_out => data_f3_data_out, | |||
|
508 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |||
|
509 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |||
|
510 | data_f3_data_out_ren => data_f3_data_out_ren , | |||
|
511 | ||||
|
512 | ------------------------------------------------------------------------- | |||
|
513 | observation_reg => OPEN | |||
|
514 | ||||
|
515 | ); | |||
|
516 | ||||
|
517 | ||||
|
518 | ----------------------------------------------------------------------------- | |||
|
519 | -- TEMP | |||
|
520 | ----------------------------------------------------------------------------- | |||
|
521 | ||||
|
522 | PROCESS (clk, rstn) | |||
|
523 | BEGIN -- PROCESS | |||
|
524 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
525 | data_f0_data_out_valid <= '0'; | |||
|
526 | data_f0_data_out_valid_burst <= '0'; | |||
|
527 | data_f1_data_out_valid <= '0'; | |||
|
528 | data_f1_data_out_valid_burst <= '0'; | |||
|
529 | data_f2_data_out_valid <= '0'; | |||
|
530 | data_f2_data_out_valid_burst <= '0'; | |||
|
531 | data_f3_data_out_valid <= '0'; | |||
|
532 | data_f3_data_out_valid_burst <= '0'; | |||
|
533 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
534 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |||
|
535 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |||
|
536 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |||
|
537 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |||
|
538 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | |||
|
539 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |||
|
540 | data_f3_data_out_valid <= data_f3_data_out_valid_s; | |||
|
541 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; | |||
|
542 | END IF; | |||
|
543 | END PROCESS; | |||
|
544 | ||||
|
545 | data_f0_addr_out <= data_f0_addr_out_s; | |||
|
546 | data_f1_addr_out <= data_f1_addr_out_s; | |||
|
547 | data_f2_addr_out <= data_f2_addr_out_s; | |||
|
548 | data_f3_addr_out <= data_f3_addr_out_s; | |||
|
549 | ||||
|
550 | ----------------------------------------------------------------------------- | |||
|
551 | -- RoundRobin Selection For DMA | |||
|
552 | ----------------------------------------------------------------------------- | |||
|
553 | ||||
|
554 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |||
|
555 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |||
|
556 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |||
|
557 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |||
|
558 | ||||
|
559 | RR_Arbiter_4_1 : RR_Arbiter_4 | |||
|
560 | PORT MAP ( | |||
|
561 | clk => clk, | |||
|
562 | rstn => rstn, | |||
|
563 | in_valid => dma_rr_valid, | |||
|
564 | out_grant => dma_rr_grant_s); | |||
|
565 | ||||
|
566 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |||
|
567 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |||
|
568 | dma_rr_valid_ms(2) <= '0'; | |||
|
569 | dma_rr_valid_ms(3) <= '0'; | |||
|
570 | ||||
|
571 | RR_Arbiter_4_2 : RR_Arbiter_4 | |||
|
572 | PORT MAP ( | |||
|
573 | clk => clk, | |||
|
574 | rstn => rstn, | |||
|
575 | in_valid => dma_rr_valid_ms, | |||
|
576 | out_grant => dma_rr_grant_ms); | |||
|
577 | ||||
|
578 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |||
|
579 | ||||
|
580 | ||||
|
581 | ----------------------------------------------------------------------------- | |||
|
582 | -- in : dma_rr_grant | |||
|
583 | -- send | |||
|
584 | -- out : dma_sel | |||
|
585 | -- dma_valid_burst | |||
|
586 | -- dma_sel_valid | |||
|
587 | ----------------------------------------------------------------------------- | |||
|
588 | PROCESS (clk, rstn) | |||
|
589 | BEGIN -- PROCESS | |||
|
590 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
591 | dma_sel <= (OTHERS => '0'); | |||
|
592 | dma_send <= '0'; | |||
|
593 | dma_valid_burst <= '0'; | |||
|
594 | data_ms_done <= '0'; | |||
|
595 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
596 | IF run = '1' THEN | |||
|
597 | data_ms_done <= '0'; | |||
|
598 | IF dma_sel = "00000" OR dma_done = '1' THEN | |||
|
599 | dma_sel <= dma_rr_grant; | |||
|
600 | IF dma_rr_grant(0) = '1' THEN | |||
|
601 | dma_send <= '1'; | |||
|
602 | dma_valid_burst <= data_f0_data_out_valid_burst; | |||
|
603 | dma_sel_valid <= data_f0_data_out_valid; | |||
|
604 | ELSIF dma_rr_grant(1) = '1' THEN | |||
|
605 | dma_send <= '1'; | |||
|
606 | dma_valid_burst <= data_f1_data_out_valid_burst; | |||
|
607 | dma_sel_valid <= data_f1_data_out_valid; | |||
|
608 | ELSIF dma_rr_grant(2) = '1' THEN | |||
|
609 | dma_send <= '1'; | |||
|
610 | dma_valid_burst <= data_f2_data_out_valid_burst; | |||
|
611 | dma_sel_valid <= data_f2_data_out_valid; | |||
|
612 | ELSIF dma_rr_grant(3) = '1' THEN | |||
|
613 | dma_send <= '1'; | |||
|
614 | dma_valid_burst <= data_f3_data_out_valid_burst; | |||
|
615 | dma_sel_valid <= data_f3_data_out_valid; | |||
|
616 | ELSIF dma_rr_grant(4) = '1' THEN | |||
|
617 | dma_send <= '1'; | |||
|
618 | dma_valid_burst <= data_ms_valid_burst; | |||
|
619 | dma_sel_valid <= data_ms_valid; | |||
|
620 | END IF; | |||
|
621 | ||||
|
622 | IF dma_sel(4) = '1' THEN | |||
|
623 | data_ms_done <= '1'; | |||
|
624 | END IF; | |||
|
625 | ELSE | |||
|
626 | dma_sel <= dma_sel; | |||
|
627 | dma_send <= '0'; | |||
|
628 | END IF; | |||
|
629 | ELSE | |||
|
630 | data_ms_done <= '0'; | |||
|
631 | dma_sel <= (OTHERS => '0'); | |||
|
632 | dma_send <= '0'; | |||
|
633 | dma_valid_burst <= '0'; | |||
|
634 | END IF; | |||
|
635 | END IF; | |||
|
636 | END PROCESS; | |||
|
637 | ||||
|
638 | ||||
|
639 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |||
|
640 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |||
|
641 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |||
|
642 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |||
|
643 | data_ms_addr; | |||
|
644 | ||||
|
645 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |||
|
646 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |||
|
647 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | |||
|
648 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE | |||
|
649 | data_ms_data; | |||
|
650 | ||||
|
651 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |||
|
652 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | |||
|
653 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | |||
|
654 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | |||
|
655 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | |||
|
656 | ||||
|
657 | dma_data_2 <= dma_data; | |||
|
658 | ||||
|
659 | ----------------------------------------------------------------------------- | |||
|
660 | -- DMA | |||
|
661 | ----------------------------------------------------------------------------- | |||
|
662 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |||
|
663 | GENERIC MAP ( | |||
|
664 | tech => inferred, | |||
|
665 | hindex => hindex) | |||
|
666 | PORT MAP ( | |||
|
667 | HCLK => clk, | |||
|
668 | HRESETn => rstn, | |||
|
669 | run => run, | |||
|
670 | AHB_Master_In => ahbi, | |||
|
671 | AHB_Master_Out => ahbo, | |||
|
672 | ||||
|
673 | send => dma_send, | |||
|
674 | valid_burst => dma_valid_burst, | |||
|
675 | done => dma_done, | |||
|
676 | ren => dma_ren, | |||
|
677 | address => dma_address, | |||
|
678 | data => dma_data_2); | |||
|
679 | ||||
|
680 | ----------------------------------------------------------------------------- | |||
|
681 | -- Matrix Spectral | |||
|
682 | ----------------------------------------------------------------------------- | |||
|
683 | data_ms_addr <= (OTHERS => '0'); | |||
|
684 | data_ms_data <= (OTHERS => '0'); | |||
|
685 | data_ms_valid <= '0'; | |||
|
686 | data_ms_valid_burst <= '0'; | |||
|
687 | ||||
|
688 | ready_matrix_f0_0 <= '0'; | |||
|
689 | ready_matrix_f0_1 <= '0'; | |||
|
690 | ready_matrix_f1 <= '0'; | |||
|
691 | ready_matrix_f2 <= '0'; | |||
|
692 | error_anticipating_empty_fifo <= '0'; | |||
|
693 | error_bad_component_error <= '0'; | |||
|
694 | observation_reg <= (OTHERS => '0'); | |||
|
695 | ||||
|
696 | matrix_time_f2 <= (OTHERS => '0'); | |||
|
697 | matrix_time_f1 <= (OTHERS => '0'); | |||
|
698 | matrix_time_f0_1 <= (OTHERS => '0'); | |||
|
699 | matrix_time_f0_0 <= (OTHERS => '0'); | |||
|
700 | ||||
|
701 | END beh; |
@@ -1,51 +1,51 | |||||
1 | #GRLIB=../.. |
|
1 | #GRLIB=../.. | |
2 | VHDLIB=../.. |
|
2 | VHDLIB=../.. | |
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
|
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
5 | TOP=leon3mp |
|
5 | TOP=LFR_em | |
6 | BOARD=em-LeonLPP-A3PE3kL-v3-core1 |
|
6 | BOARD=em-LeonLPP-A3PE3kL-v3-core1 | |
7 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc |
|
7 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc | |
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) |
|
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf |
|
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf |
|
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |
11 | EFFORT=high |
|
11 | EFFORT=high | |
12 | XSTOPT= |
|
12 | XSTOPT= | |
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
|
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd |
|
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |
15 | VHDLSYNFILES=config.vhd leon3mp.vhd |
|
15 | #VHDLSYNFILES=config.vhd leon3mp.vhd | |
|
16 | VHDLSYNFILES=LFR-em.vhd | |||
16 | #VHDLSIMFILES=testbench.vhd |
|
17 | #VHDLSIMFILES=testbench.vhd | |
17 | #SIMTOP=testbench |
|
18 | #SIMTOP=testbench | |
18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc |
|
19 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |
19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc |
|
20 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |
20 | PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc |
|
21 | PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc | |
21 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut |
|
22 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |
22 | CLEAN=soft-clean |
|
23 | CLEAN=soft-clean | |
23 |
|
24 | |||
24 | TECHLIBS = proasic3e |
|
25 | TECHLIBS = proasic3e | |
25 |
|
26 | |||
26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
|
27 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |
27 | tmtc openchip hynix ihp gleichmann micron usbhc |
|
28 | tmtc openchip hynix ihp gleichmann micron usbhc | |
28 |
|
29 | |||
29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ |
|
30 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |
30 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ |
|
31 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |
31 | ./amba_lcd_16x2_ctrlr \ |
|
32 | ./amba_lcd_16x2_ctrlr \ | |
32 | ./general_purpose/lpp_AMR \ |
|
33 | ./general_purpose/lpp_AMR \ | |
33 | ./general_purpose/lpp_balise \ |
|
34 | ./general_purpose/lpp_balise \ | |
34 | ./general_purpose/lpp_delay \ |
|
35 | ./general_purpose/lpp_delay \ | |
35 | ./lpp_bootloader \ |
|
36 | ./lpp_bootloader \ | |
36 | ./lpp_cna \ |
|
37 | ./lpp_cna \ | |
37 | ./lpp_uart \ |
|
38 | ./lpp_uart \ | |
38 | ./lpp_usb \ |
|
39 | ./lpp_usb \ | |
39 |
|
40 | |||
40 |
FILESKIP = |
|
41 | FILESKIP = i2cmst.vhd \ | |
41 | i2cmst.vhd \ |
|
|||
42 | APB_MULTI_DIODE.vhd \ |
|
42 | APB_MULTI_DIODE.vhd \ | |
43 | APB_MULTI_DIODE.vhd \ |
|
43 | APB_MULTI_DIODE.vhd \ | |
44 | Top_MatrixSpec.vhd \ |
|
44 | Top_MatrixSpec.vhd \ | |
45 | APB_FFT.vhd |
|
45 | APB_FFT.vhd | |
46 |
|
46 | |||
47 | include $(GRLIB)/bin/Makefile |
|
47 | include $(GRLIB)/bin/Makefile | |
48 | include $(GRLIB)/software/leon3/Makefile |
|
48 | include $(GRLIB)/software/leon3/Makefile | |
49 |
|
49 | |||
50 | ################## project specific targets ########################## |
|
50 | ################## project specific targets ########################## | |
51 |
|
51 |
@@ -1,551 +1,532 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- LEON3 Demonstration design test bench |
|
2 | -- LEON3 Demonstration design test bench | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | ------------------------------------------------------------------------------ |
|
4 | ------------------------------------------------------------------------------ | |
5 | -- This file is a part of the GRLIB VHDL IP LIBRARY |
|
5 | -- This file is a part of the GRLIB VHDL IP LIBRARY | |
6 | -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. |
|
6 | -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. | |
7 | -- |
|
7 | -- | |
8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN |
|
8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN | |
9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED |
|
9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED | |
10 | -- IN ADVANCE IN WRITING. |
|
10 | -- IN ADVANCE IN WRITING. | |
11 | ------------------------------------------------------------------------------ |
|
11 | ------------------------------------------------------------------------------ | |
12 |
|
12 | |||
13 | LIBRARY ieee; |
|
13 | LIBRARY ieee; | |
14 | USE ieee.std_logic_1164.ALL; |
|
14 | USE ieee.std_logic_1164.ALL; | |
15 |
|
15 | |||
16 | --LIBRARY std; |
|
16 | --LIBRARY std; | |
17 | --USE std.textio.ALL; |
|
17 | --USE std.textio.ALL; | |
18 |
|
18 | |||
19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
22 | USE grlib.AMBA_TestPackage.ALL; |
|
22 | USE grlib.AMBA_TestPackage.ALL; | |
23 | LIBRARY gaisler; |
|
23 | LIBRARY gaisler; | |
24 | USE gaisler.memctrl.ALL; |
|
24 | USE gaisler.memctrl.ALL; | |
25 | USE gaisler.leon3.ALL; |
|
25 | USE gaisler.leon3.ALL; | |
26 | USE gaisler.uart.ALL; |
|
26 | USE gaisler.uart.ALL; | |
27 | USE gaisler.misc.ALL; |
|
27 | USE gaisler.misc.ALL; | |
28 | USE gaisler.libdcom.ALL; |
|
28 | USE gaisler.libdcom.ALL; | |
29 | USE gaisler.sim.ALL; |
|
29 | USE gaisler.sim.ALL; | |
30 | USE gaisler.jtagtst.ALL; |
|
30 | USE gaisler.jtagtst.ALL; | |
31 | USE gaisler.misc.ALL; |
|
31 | USE gaisler.misc.ALL; | |
32 | LIBRARY techmap; |
|
32 | LIBRARY techmap; | |
33 | USE techmap.gencomp.ALL; |
|
33 | USE techmap.gencomp.ALL; | |
34 | LIBRARY esa; |
|
34 | LIBRARY esa; | |
35 | USE esa.memoryctrl.ALL; |
|
35 | USE esa.memoryctrl.ALL; | |
36 | --LIBRARY micron; |
|
36 | --LIBRARY micron; | |
37 | --USE micron.components.ALL; |
|
37 | --USE micron.components.ALL; | |
38 | LIBRARY lpp; |
|
38 | LIBRARY lpp; | |
39 | USE lpp.lpp_waveform_pkg.ALL; |
|
39 | USE lpp.lpp_waveform_pkg.ALL; | |
40 | USE lpp.lpp_memory.ALL; |
|
40 | USE lpp.lpp_memory.ALL; | |
41 | USE lpp.lpp_ad_conv.ALL; |
|
41 | USE lpp.lpp_ad_conv.ALL; | |
42 | USE lpp.testbench_package.ALL; |
|
42 | USE lpp.testbench_package.ALL; | |
43 | USE lpp.lpp_lfr_pkg.ALL; |
|
43 | USE lpp.lpp_lfr_pkg.ALL; | |
44 | USE lpp.iir_filter.ALL; |
|
44 | USE lpp.iir_filter.ALL; | |
45 | USE lpp.general_purpose.ALL; |
|
45 | USE lpp.general_purpose.ALL; | |
46 | USE lpp.CY7C1061DV33_pkg.ALL; |
|
46 | USE lpp.CY7C1061DV33_pkg.ALL; | |
47 |
|
47 | |||
48 | ENTITY testbench IS |
|
48 | ENTITY testbench IS | |
49 | END; |
|
49 | END; | |
50 |
|
50 | |||
51 |
|
||||
52 |
|
||||
53 |
|
||||
54 |
|
||||
55 |
|
||||
56 |
|
||||
57 |
|
||||
58 |
|
||||
59 |
|
||||
60 |
|
||||
61 |
|
||||
62 |
|
||||
63 |
|
||||
64 |
|
||||
65 |
|
||||
66 |
|
||||
67 |
|
||||
68 |
|
||||
69 |
|
||||
70 | ARCHITECTURE behav OF testbench IS |
|
51 | ARCHITECTURE behav OF testbench IS | |
71 | CONSTANT INDEX_LFR : INTEGER := 15; |
|
52 | CONSTANT INDEX_LFR : INTEGER := 15; | |
72 | CONSTANT ADDR_LFR : INTEGER := 15; |
|
53 | CONSTANT ADDR_LFR : INTEGER := 15; | |
73 | -- REG MS |
|
54 | -- REG MS | |
74 | CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; |
|
55 | CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; | |
75 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; |
|
56 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; | |
76 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; |
|
57 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; | |
77 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; |
|
58 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; | |
78 |
|
59 | |||
79 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; |
|
60 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; | |
80 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; |
|
61 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; | |
81 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; |
|
62 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; | |
82 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C"; |
|
63 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C"; | |
83 |
|
64 | |||
84 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; |
|
65 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; | |
85 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; |
|
66 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; | |
86 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; |
|
67 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; | |
87 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; |
|
68 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; | |
88 |
|
69 | |||
89 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; |
|
70 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; | |
90 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; |
|
71 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; | |
91 | --X"00000F38"; |
|
72 | --X"00000F38"; | |
92 | CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3F"; |
|
73 | CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3F"; | |
93 |
|
74 | |||
94 | -- REG WAVEFORM |
|
75 | -- REG WAVEFORM | |
95 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; |
|
76 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; | |
96 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; |
|
77 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; | |
97 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; |
|
78 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; | |
98 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; |
|
79 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; | |
99 |
|
80 | |||
100 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; |
|
81 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; | |
101 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; |
|
82 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; | |
102 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; |
|
83 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; | |
103 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; |
|
84 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; | |
104 |
|
85 | |||
105 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60"; |
|
86 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60"; | |
106 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64"; |
|
87 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64"; | |
107 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68"; |
|
88 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68"; | |
108 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C"; |
|
89 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C"; | |
109 |
|
90 | |||
110 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70"; |
|
91 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70"; | |
111 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74"; |
|
92 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74"; | |
112 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78"; |
|
93 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78"; | |
113 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C"; |
|
94 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C"; | |
114 | -- RAM ADDRESS |
|
95 | -- RAM ADDRESS | |
115 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; |
|
96 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; | |
116 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
|
97 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; | |
117 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; |
|
98 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; | |
118 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; |
|
99 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; | |
119 |
|
100 | |||
120 |
|
101 | |||
121 | -- Common signal |
|
102 | -- Common signal | |
122 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; |
|
103 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; | |
123 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
|
104 | SIGNAL clk25MHz : STD_LOGIC := '0'; | |
124 | SIGNAL rstn : STD_LOGIC := '0'; |
|
105 | SIGNAL rstn : STD_LOGIC := '0'; | |
125 |
|
106 | |||
126 | -- ADC interface |
|
107 | -- ADC interface | |
127 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT |
|
108 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT | |
128 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT |
|
109 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT | |
129 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN |
|
110 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN | |
130 |
|
111 | |||
131 | -- AD Converter RHF1401 |
|
112 | -- AD Converter RHF1401 | |
132 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
113 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
133 | SIGNAL sample_val : STD_LOGIC; |
|
114 | SIGNAL sample_val : STD_LOGIC; | |
134 |
|
115 | |||
135 | -- AHB/APB SIGNAL |
|
116 | -- AHB/APB SIGNAL | |
136 | SIGNAL apbi : apb_slv_in_type; |
|
117 | SIGNAL apbi : apb_slv_in_type; | |
137 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
|
118 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
138 | SIGNAL ahbsi : ahb_slv_in_type; |
|
119 | SIGNAL ahbsi : ahb_slv_in_type; | |
139 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
|
120 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
140 | SIGNAL ahbmi : ahb_mst_in_type; |
|
121 | SIGNAL ahbmi : ahb_mst_in_type; | |
141 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
|
122 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
142 |
|
123 | |||
143 | SIGNAL bias_fail_bw : STD_LOGIC; |
|
124 | SIGNAL bias_fail_bw : STD_LOGIC; | |
144 |
|
125 | |||
145 | ----------------------------------------------------------------------------- |
|
126 | ----------------------------------------------------------------------------- | |
146 | -- LPP_WAVEFORM |
|
127 | -- LPP_WAVEFORM | |
147 | ----------------------------------------------------------------------------- |
|
128 | ----------------------------------------------------------------------------- | |
148 | CONSTANT data_size : INTEGER := 96; |
|
129 | CONSTANT data_size : INTEGER := 96; | |
149 | CONSTANT nb_burst_available_size : INTEGER := 50; |
|
130 | CONSTANT nb_burst_available_size : INTEGER := 50; | |
150 | CONSTANT nb_snapshot_param_size : INTEGER := 2; |
|
131 | CONSTANT nb_snapshot_param_size : INTEGER := 2; | |
151 | CONSTANT delta_vector_size : INTEGER := 2; |
|
132 | CONSTANT delta_vector_size : INTEGER := 2; | |
152 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; |
|
133 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; | |
153 |
|
134 | |||
154 | SIGNAL reg_run : STD_LOGIC; |
|
135 | SIGNAL reg_run : STD_LOGIC; | |
155 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
136 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
156 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
137 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
157 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
138 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
158 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
139 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
159 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
140 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
160 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
141 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
161 | SIGNAL enable_f0 : STD_LOGIC; |
|
142 | SIGNAL enable_f0 : STD_LOGIC; | |
162 | SIGNAL enable_f1 : STD_LOGIC; |
|
143 | SIGNAL enable_f1 : STD_LOGIC; | |
163 | SIGNAL enable_f2 : STD_LOGIC; |
|
144 | SIGNAL enable_f2 : STD_LOGIC; | |
164 | SIGNAL enable_f3 : STD_LOGIC; |
|
145 | SIGNAL enable_f3 : STD_LOGIC; | |
165 | SIGNAL burst_f0 : STD_LOGIC; |
|
146 | SIGNAL burst_f0 : STD_LOGIC; | |
166 | SIGNAL burst_f1 : STD_LOGIC; |
|
147 | SIGNAL burst_f1 : STD_LOGIC; | |
167 | SIGNAL burst_f2 : STD_LOGIC; |
|
148 | SIGNAL burst_f2 : STD_LOGIC; | |
168 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
149 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
150 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
170 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
151 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
171 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
152 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
172 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
153 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
173 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
154 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
174 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
155 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
156 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
176 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
157 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
177 | SIGNAL data_f0_in_valid : STD_LOGIC; |
|
158 | SIGNAL data_f0_in_valid : STD_LOGIC; | |
178 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
159 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
179 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
160 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
180 | SIGNAL data_f1_in_valid : STD_LOGIC; |
|
161 | SIGNAL data_f1_in_valid : STD_LOGIC; | |
181 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
162 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
182 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
163 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
183 | SIGNAL data_f2_in_valid : STD_LOGIC; |
|
164 | SIGNAL data_f2_in_valid : STD_LOGIC; | |
184 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
165 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
185 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
166 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
186 | SIGNAL data_f3_in_valid : STD_LOGIC; |
|
167 | SIGNAL data_f3_in_valid : STD_LOGIC; | |
187 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
168 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
188 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
169 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
189 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
170 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
190 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
171 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
191 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
172 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
192 | SIGNAL data_f0_data_out_ack : STD_LOGIC; |
|
173 | SIGNAL data_f0_data_out_ack : STD_LOGIC; | |
193 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
174 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
194 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
195 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
176 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
196 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
177 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
197 | SIGNAL data_f1_data_out_ack : STD_LOGIC; |
|
178 | SIGNAL data_f1_data_out_ack : STD_LOGIC; | |
198 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
179 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
199 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
200 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
181 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
201 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
182 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
202 | SIGNAL data_f2_data_out_ack : STD_LOGIC; |
|
183 | SIGNAL data_f2_data_out_ack : STD_LOGIC; | |
203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
184 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
185 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
186 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
187 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
207 | SIGNAL data_f3_data_out_ack : STD_LOGIC; |
|
188 | SIGNAL data_f3_data_out_ack : STD_LOGIC; | |
208 |
|
189 | |||
209 | --MEM CTRLR |
|
190 | --MEM CTRLR | |
210 | SIGNAL memi : memory_in_type; |
|
191 | SIGNAL memi : memory_in_type; | |
211 | SIGNAL memo : memory_out_type; |
|
192 | SIGNAL memo : memory_out_type; | |
212 | SIGNAL wpo : wprot_out_type; |
|
193 | SIGNAL wpo : wprot_out_type; | |
213 | SIGNAL sdo : sdram_out_type; |
|
194 | SIGNAL sdo : sdram_out_type; | |
214 |
|
195 | |||
215 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; |
|
196 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; | |
216 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
197 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
217 | SIGNAL nSRAM_BE0 : STD_LOGIC; |
|
198 | SIGNAL nSRAM_BE0 : STD_LOGIC; | |
218 | SIGNAL nSRAM_BE1 : STD_LOGIC; |
|
199 | SIGNAL nSRAM_BE1 : STD_LOGIC; | |
219 | SIGNAL nSRAM_BE2 : STD_LOGIC; |
|
200 | SIGNAL nSRAM_BE2 : STD_LOGIC; | |
220 | SIGNAL nSRAM_BE3 : STD_LOGIC; |
|
201 | SIGNAL nSRAM_BE3 : STD_LOGIC; | |
221 | SIGNAL nSRAM_WE : STD_LOGIC; |
|
202 | SIGNAL nSRAM_WE : STD_LOGIC; | |
222 | SIGNAL nSRAM_CE : STD_LOGIC; |
|
203 | SIGNAL nSRAM_CE : STD_LOGIC; | |
223 | SIGNAL nSRAM_OE : STD_LOGIC; |
|
204 | SIGNAL nSRAM_OE : STD_LOGIC; | |
224 |
|
205 | |||
225 | CONSTANT padtech : INTEGER := inferred; |
|
206 | CONSTANT padtech : INTEGER := inferred; | |
226 | SIGNAL not_ramsn_0 : STD_LOGIC; |
|
207 | SIGNAL not_ramsn_0 : STD_LOGIC; | |
227 |
|
208 | |||
228 | ----------------------------------------------------------------------------- |
|
209 | ----------------------------------------------------------------------------- | |
229 | SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
210 | SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
230 | SIGNAL read_buffer : STD_LOGIC; |
|
211 | SIGNAL read_buffer : STD_LOGIC; | |
231 | ----------------------------------------------------------------------------- |
|
212 | ----------------------------------------------------------------------------- | |
232 | SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; |
|
213 | SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; | |
233 | SIGNAL state_read_buffer_on_going : STD_LOGIC; |
|
214 | SIGNAL state_read_buffer_on_going : STD_LOGIC; | |
234 | CONSTANT hindex : INTEGER := 1; |
|
215 | CONSTANT hindex : INTEGER := 1; | |
235 | SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
216 | SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
236 | SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
217 | SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
237 | SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
218 | SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
238 | SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
219 | SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
239 |
|
220 | |||
240 | SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
221 | SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
241 | SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
222 | SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
242 | SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
223 | SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
243 | SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
224 | SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
244 |
|
225 | |||
245 | SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
226 | SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
246 | SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
227 | SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
247 | SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
228 | SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
248 |
|
229 | |||
249 | SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
230 | SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
250 | SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
231 | SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
251 | SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
232 | SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
252 |
|
233 | |||
253 | SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
234 | SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
254 | SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
235 | SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
255 | SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
236 | SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
256 |
|
237 | |||
257 | SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
238 | SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
258 | SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
239 | SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
259 | SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
240 | SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
260 |
|
241 | |||
261 | SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
242 | SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
262 | SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
243 | SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
263 | SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
244 | SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
264 |
|
245 | |||
265 | SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
246 | SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
266 | SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
247 | SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
267 | SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
248 | SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
268 | ----------------------------------------------------------------------------- |
|
249 | ----------------------------------------------------------------------------- | |
269 |
|
250 | |||
270 | SIGNAL current_data : INTEGER; |
|
251 | SIGNAL current_data : INTEGER; | |
271 | SIGNAL LIMIT_DATA : INTEGER := 64; |
|
252 | SIGNAL LIMIT_DATA : INTEGER := 64; | |
272 |
|
253 | |||
273 | SIGNAL read_buffer_temp : STD_LOGIC; |
|
254 | SIGNAL read_buffer_temp : STD_LOGIC; | |
274 | SIGNAL read_buffer_temp_2 : STD_LOGIC; |
|
255 | SIGNAL read_buffer_temp_2 : STD_LOGIC; | |
275 |
|
256 | |||
276 |
|
257 | |||
277 | BEGIN |
|
258 | BEGIN | |
278 |
|
259 | |||
279 | ----------------------------------------------------------------------------- |
|
260 | ----------------------------------------------------------------------------- | |
280 |
|
261 | |||
281 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
|
262 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz | |
282 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz |
|
263 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz | |
283 |
|
264 | |||
284 | ----------------------------------------------------------------------------- |
|
265 | ----------------------------------------------------------------------------- | |
285 |
|
266 | |||
286 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
|
267 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE | |
287 | TestModule_RHF1401_1 : TestModule_RHF1401 |
|
268 | TestModule_RHF1401_1 : TestModule_RHF1401 | |
288 | GENERIC MAP ( |
|
269 | GENERIC MAP ( | |
289 | freq => 24*(I+1), |
|
270 | freq => 24*(I+1), | |
290 | amplitude => 8000/(I+1), |
|
271 | amplitude => 8000/(I+1), | |
291 | impulsion => 0) |
|
272 | impulsion => 0) | |
292 | PORT MAP ( |
|
273 | PORT MAP ( | |
293 | ADC_smpclk => ADC_smpclk, |
|
274 | ADC_smpclk => ADC_smpclk, | |
294 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
|
275 | ADC_OEB_bar => ADC_OEB_bar_CH(I), | |
295 | ADC_data => ADC_data); |
|
276 | ADC_data => ADC_data); | |
296 | END GENERATE MODULE_RHF1401; |
|
277 | END GENERATE MODULE_RHF1401; | |
297 |
|
278 | |||
298 | ----------------------------------------------------------------------------- |
|
279 | ----------------------------------------------------------------------------- | |
299 |
|
280 | |||
300 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
|
281 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 | |
301 | GENERIC MAP ( |
|
282 | GENERIC MAP ( | |
302 | ChanelCount => 8, |
|
283 | ChanelCount => 8, | |
303 | ncycle_cnv_high => 79, |
|
284 | ncycle_cnv_high => 79, | |
304 | ncycle_cnv => 500) |
|
285 | ncycle_cnv => 500) | |
305 | PORT MAP ( |
|
286 | PORT MAP ( | |
306 | cnv_clk => clk49_152MHz, |
|
287 | cnv_clk => clk49_152MHz, | |
307 | cnv_rstn => rstn, |
|
288 | cnv_rstn => rstn, | |
308 | cnv => ADC_smpclk, |
|
289 | cnv => ADC_smpclk, | |
309 | clk => clk25MHz, |
|
290 | clk => clk25MHz, | |
310 | rstn => rstn, |
|
291 | rstn => rstn, | |
311 | ADC_data => ADC_data, |
|
292 | ADC_data => ADC_data, | |
312 | ADC_nOE => ADC_OEB_bar_CH, |
|
293 | ADC_nOE => ADC_OEB_bar_CH, | |
313 | sample => sample, |
|
294 | sample => sample, | |
314 | sample_val => sample_val); |
|
295 | sample_val => sample_val); | |
315 |
|
296 | |||
316 | ----------------------------------------------------------------------------- |
|
297 | ----------------------------------------------------------------------------- | |
317 |
|
298 | |||
318 | lpp_lfr_1 : lpp_lfr |
|
299 | lpp_lfr_1 : lpp_lfr | |
319 | GENERIC MAP ( |
|
300 | GENERIC MAP ( | |
320 | Mem_use => use_CEL, -- use_RAM |
|
301 | Mem_use => use_CEL, -- use_RAM | |
321 | nb_data_by_buffer_size => 32, |
|
302 | nb_data_by_buffer_size => 32, | |
322 | nb_word_by_buffer_size => 30, |
|
303 | nb_word_by_buffer_size => 30, | |
323 | nb_snapshot_param_size => 32, |
|
304 | nb_snapshot_param_size => 32, | |
324 | delta_vector_size => 32, |
|
305 | delta_vector_size => 32, | |
325 | delta_vector_size_f0_2 => 32, |
|
306 | delta_vector_size_f0_2 => 32, | |
326 | pindex => INDEX_LFR, |
|
307 | pindex => INDEX_LFR, | |
327 | paddr => ADDR_LFR, |
|
308 | paddr => ADDR_LFR, | |
328 | pmask => 16#fff#, |
|
309 | pmask => 16#fff#, | |
329 | pirq_ms => 6, |
|
310 | pirq_ms => 6, | |
330 | pirq_wfp => 14, |
|
311 | pirq_wfp => 14, | |
331 | hindex => 0, |
|
312 | hindex => 0, | |
332 | top_lfr_version => X"000001") |
|
313 | top_lfr_version => X"000001") | |
333 | PORT MAP ( |
|
314 | PORT MAP ( | |
334 | clk => clk25MHz, |
|
315 | clk => clk25MHz, | |
335 | rstn => rstn, |
|
316 | rstn => rstn, | |
336 | sample_B => sample(2 DOWNTO 0), |
|
317 | sample_B => sample(2 DOWNTO 0), | |
337 | sample_E => sample(7 DOWNTO 3), |
|
318 | sample_E => sample(7 DOWNTO 3), | |
338 | sample_val => sample_val, |
|
319 | sample_val => sample_val, | |
339 | apbi => apbi, |
|
320 | apbi => apbi, | |
340 | apbo => apbo(15), |
|
321 | apbo => apbo(15), | |
341 | ahbi => ahbmi, |
|
322 | ahbi => ahbmi, | |
342 | ahbo => ahbmo(0), |
|
323 | ahbo => ahbmo(0), | |
343 | coarse_time => coarse_time, |
|
324 | coarse_time => coarse_time, | |
344 | fine_time => fine_time, |
|
325 | fine_time => fine_time, | |
345 | data_shaping_BW => bias_fail_bw); |
|
326 | data_shaping_BW => bias_fail_bw); | |
346 |
|
327 | |||
347 | ----------------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------------- | |
348 | --- AHB CONTROLLER ------------------------------------------------- |
|
329 | --- AHB CONTROLLER ------------------------------------------------- | |
349 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
330 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
350 | GENERIC MAP (defmast => 0, split => 0, |
|
331 | GENERIC MAP (defmast => 0, split => 0, | |
351 | rrobin => 1, ioaddr => 16#FFF#, |
|
332 | rrobin => 1, ioaddr => 16#FFF#, | |
352 | ioen => 0, nahbm => 2, nahbs => 1) |
|
333 | ioen => 0, nahbm => 2, nahbs => 1) | |
353 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
334 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); | |
354 |
|
335 | |||
355 |
|
336 | |||
356 |
|
337 | |||
357 | --- AHB RAM ---------------------------------------------------------- |
|
338 | --- AHB RAM ---------------------------------------------------------- | |
358 | --ahbram0 : ahbram |
|
339 | --ahbram0 : ahbram | |
359 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) |
|
340 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) | |
360 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); |
|
341 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); | |
361 | --ahbram1 : ahbram |
|
342 | --ahbram1 : ahbram | |
362 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) |
|
343 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) | |
363 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); |
|
344 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); | |
364 | --ahbram2 : ahbram |
|
345 | --ahbram2 : ahbram | |
365 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) |
|
346 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) | |
366 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); |
|
347 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); | |
367 | --ahbram3 : ahbram |
|
348 | --ahbram3 : ahbram | |
368 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) |
|
349 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) | |
369 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); |
|
350 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); | |
370 |
|
351 | |||
371 | ----------------------------------------------------------------------------- |
|
352 | ----------------------------------------------------------------------------- | |
372 | ---------------------------------------------------------------------- |
|
353 | ---------------------------------------------------------------------- | |
373 | --- Memory controllers --------------------------------------------- |
|
354 | --- Memory controllers --------------------------------------------- | |
374 | ---------------------------------------------------------------------- |
|
355 | ---------------------------------------------------------------------- | |
375 | memctrlr : mctrl GENERIC MAP ( |
|
356 | memctrlr : mctrl GENERIC MAP ( | |
376 | hindex => 0, |
|
357 | hindex => 0, | |
377 | pindex => 0, |
|
358 | pindex => 0, | |
378 | paddr => 0, |
|
359 | paddr => 0, | |
379 | srbanks => 1 |
|
360 | srbanks => 1 | |
380 | ) |
|
361 | ) | |
381 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
362 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
382 |
|
363 | |||
383 | memi.brdyn <= '1'; |
|
364 | memi.brdyn <= '1'; | |
384 | memi.bexcn <= '1'; |
|
365 | memi.bexcn <= '1'; | |
385 | memi.writen <= '1'; |
|
366 | memi.writen <= '1'; | |
386 | memi.wrn <= "1111"; |
|
367 | memi.wrn <= "1111"; | |
387 | memi.bwidth <= "10"; |
|
368 | memi.bwidth <= "10"; | |
388 |
|
369 | |||
389 | bdr : FOR i IN 0 TO 3 GENERATE |
|
370 | bdr : FOR i IN 0 TO 3 GENERATE | |
390 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
371 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
391 | PORT MAP ( |
|
372 | PORT MAP ( | |
392 | data(31-i*8 DOWNTO 24-i*8), |
|
373 | data(31-i*8 DOWNTO 24-i*8), | |
393 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
374 | memo.data(31-i*8 DOWNTO 24-i*8), | |
394 | memo.bdrive(i), |
|
375 | memo.bdrive(i), | |
395 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
376 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
396 | END GENERATE; |
|
377 | END GENERATE; | |
397 |
|
378 | |||
398 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
379 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
399 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
380 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
400 |
|
381 | |||
401 | not_ramsn_0 <= NOT(memo.ramsn(0)); |
|
382 | not_ramsn_0 <= NOT(memo.ramsn(0)); | |
402 |
|
383 | |||
403 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); |
|
384 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); | |
404 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
385 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
405 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
386 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
406 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
387 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
407 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
388 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
408 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
389 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
409 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
390 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
410 |
|
391 | |||
411 | async_1Mx16_0: CY7C1061DV33 |
|
392 | async_1Mx16_0: CY7C1061DV33 | |
412 | GENERIC MAP ( |
|
393 | GENERIC MAP ( | |
413 | ADDR_BITS => 20, |
|
394 | ADDR_BITS => 20, | |
414 | DATA_BITS => 16, |
|
395 | DATA_BITS => 16, | |
415 | depth => 1048576, |
|
396 | depth => 1048576, | |
416 | MEM_ARRAY_DEBUG => 32, |
|
397 | MEM_ARRAY_DEBUG => 32, | |
417 | TimingInfo => TRUE, |
|
398 | TimingInfo => TRUE, | |
418 | TimingChecks => '1') |
|
399 | TimingChecks => '1') | |
419 | PORT MAP ( |
|
400 | PORT MAP ( | |
420 | CE1_b => '0', |
|
401 | CE1_b => '0', | |
421 | CE2 => nSRAM_CE, |
|
402 | CE2 => nSRAM_CE, | |
422 | WE_b => nSRAM_WE, |
|
403 | WE_b => nSRAM_WE, | |
423 | OE_b => nSRAM_OE, |
|
404 | OE_b => nSRAM_OE, | |
424 | BHE_b => nSRAM_BE1, |
|
405 | BHE_b => nSRAM_BE1, | |
425 | BLE_b => nSRAM_BE0, |
|
406 | BLE_b => nSRAM_BE0, | |
426 | A => address, |
|
407 | A => address, | |
427 | DQ => data(15 DOWNTO 0)); |
|
408 | DQ => data(15 DOWNTO 0)); | |
428 |
|
409 | |||
429 | async_1Mx16_1: CY7C1061DV33 |
|
410 | async_1Mx16_1: CY7C1061DV33 | |
430 | GENERIC MAP ( |
|
411 | GENERIC MAP ( | |
431 | ADDR_BITS => 20, |
|
412 | ADDR_BITS => 20, | |
432 | DATA_BITS => 16, |
|
413 | DATA_BITS => 16, | |
433 | depth => 1048576, |
|
414 | depth => 1048576, | |
434 | MEM_ARRAY_DEBUG => 32, |
|
415 | MEM_ARRAY_DEBUG => 32, | |
435 | TimingInfo => TRUE, |
|
416 | TimingInfo => TRUE, | |
436 | TimingChecks => '1') |
|
417 | TimingChecks => '1') | |
437 | PORT MAP ( |
|
418 | PORT MAP ( | |
438 | CE1_b => '0', |
|
419 | CE1_b => '0', | |
439 | CE2 => nSRAM_CE, |
|
420 | CE2 => nSRAM_CE, | |
440 | WE_b => nSRAM_WE, |
|
421 | WE_b => nSRAM_WE, | |
441 | OE_b => nSRAM_OE, |
|
422 | OE_b => nSRAM_OE, | |
442 | BHE_b => nSRAM_BE3, |
|
423 | BHE_b => nSRAM_BE3, | |
443 | BLE_b => nSRAM_BE2, |
|
424 | BLE_b => nSRAM_BE2, | |
444 | A => address, |
|
425 | A => address, | |
445 | DQ => data(31 DOWNTO 16)); |
|
426 | DQ => data(31 DOWNTO 16)); | |
446 |
|
427 | |||
447 |
|
428 | |||
448 | ----------------------------------------------------------------------------- |
|
429 | ----------------------------------------------------------------------------- | |
449 |
|
430 | |||
450 | WaveGen_Proc : PROCESS |
|
431 | WaveGen_Proc : PROCESS | |
451 | BEGIN |
|
432 | BEGIN | |
452 |
|
433 | |||
453 | -- insert signal assignments here |
|
434 | -- insert signal assignments here | |
454 | WAIT UNTIL clk25MHz = '1'; |
|
435 | WAIT UNTIL clk25MHz = '1'; | |
455 | rstn <= '0'; |
|
436 | rstn <= '0'; | |
456 | apbi.psel(15) <= '0'; |
|
437 | apbi.psel(15) <= '0'; | |
457 | apbi.pwrite <= '0'; |
|
438 | apbi.pwrite <= '0'; | |
458 | apbi.penable <= '0'; |
|
439 | apbi.penable <= '0'; | |
459 | apbi.paddr <= (OTHERS => '0'); |
|
440 | apbi.paddr <= (OTHERS => '0'); | |
460 | apbi.pwdata <= (OTHERS => '0'); |
|
441 | apbi.pwdata <= (OTHERS => '0'); | |
461 | fine_time <= (OTHERS => '0'); |
|
442 | fine_time <= (OTHERS => '0'); | |
462 | coarse_time <= (OTHERS => '0'); |
|
443 | coarse_time <= (OTHERS => '0'); | |
463 | WAIT UNTIL clk25MHz = '1'; |
|
444 | WAIT UNTIL clk25MHz = '1'; | |
464 | -- ahbmi.HGRANT(2) <= '1'; |
|
445 | -- ahbmi.HGRANT(2) <= '1'; | |
465 | -- ahbmi.HREADY <= '1'; |
|
446 | -- ahbmi.HREADY <= '1'; | |
466 | -- ahbmi.HRESP <= HRESP_OKAY; |
|
447 | -- ahbmi.HRESP <= HRESP_OKAY; | |
467 |
|
448 | |||
468 | WAIT UNTIL clk25MHz = '1'; |
|
449 | WAIT UNTIL clk25MHz = '1'; | |
469 | WAIT UNTIL clk25MHz = '1'; |
|
450 | WAIT UNTIL clk25MHz = '1'; | |
470 | rstn <= '1'; |
|
451 | rstn <= '1'; | |
471 | WAIT UNTIL clk25MHz = '1'; |
|
452 | WAIT UNTIL clk25MHz = '1'; | |
472 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000"); |
|
453 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000"); | |
473 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000"); |
|
454 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000"); | |
474 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000"); |
|
455 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000"); | |
475 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000"); |
|
456 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000"); | |
476 |
|
457 | |||
477 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000"); |
|
458 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000"); | |
478 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); |
|
459 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); | |
479 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); |
|
460 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); | |
480 | WAIT UNTIL clk25MHz = '1'; |
|
461 | WAIT UNTIL clk25MHz = '1'; | |
481 | --------------------------------------------------------------------------- |
|
462 | --------------------------------------------------------------------------- | |
482 | -- CONFIGURATION STEP |
|
463 | -- CONFIGURATION STEP | |
483 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); |
|
464 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); | |
484 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); |
|
465 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); | |
485 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); |
|
466 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); | |
486 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); |
|
467 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); | |
487 |
|
468 | |||
488 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020" |
|
469 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020" | |
489 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019" |
|
470 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019" | |
490 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" |
|
471 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" | |
491 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019" |
|
472 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019" | |
492 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" |
|
473 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" | |
493 |
|
474 | |||
494 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" |
|
475 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" | |
495 | -- |
|
476 | -- | |
496 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); |
|
477 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); | |
497 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); |
|
478 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); | |
498 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); |
|
479 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); | |
499 |
|
480 | |||
500 |
|
481 | |||
501 | WAIT UNTIL clk25MHz = '1'; |
|
482 | WAIT UNTIL clk25MHz = '1'; | |
502 | WAIT UNTIL clk25MHz = '1'; |
|
483 | WAIT UNTIL clk25MHz = '1'; | |
503 |
|
484 | |||
504 |
|
485 | |||
505 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); |
|
486 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); | |
506 | WAIT UNTIL clk25MHz = '1'; |
|
487 | WAIT UNTIL clk25MHz = '1'; | |
507 | WAIT UNTIL clk25MHz = '1'; |
|
488 | WAIT UNTIL clk25MHz = '1'; | |
508 | WAIT UNTIL clk25MHz = '1'; |
|
489 | WAIT UNTIL clk25MHz = '1'; | |
509 | WAIT UNTIL clk25MHz = '1'; |
|
490 | WAIT UNTIL clk25MHz = '1'; | |
510 | WAIT UNTIL clk25MHz = '1'; |
|
491 | WAIT UNTIL clk25MHz = '1'; | |
511 | WAIT UNTIL clk25MHz = '1'; |
|
492 | WAIT UNTIL clk25MHz = '1'; | |
512 | WAIT FOR 1 us; |
|
493 | WAIT FOR 1 us; | |
513 | coarse_time <= X"00000001"; |
|
494 | coarse_time <= X"00000001"; | |
514 | --------------------------------------------------------------------------- |
|
495 | --------------------------------------------------------------------------- | |
515 | -- RUN STEP |
|
496 | -- RUN STEP | |
516 | WAIT FOR 200 ms; |
|
497 | WAIT FOR 200 ms; | |
517 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
498 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
518 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); |
|
499 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); | |
519 | WAIT FOR 10 us; |
|
500 | WAIT FOR 10 us; | |
520 | WAIT UNTIL clk25MHz = '1'; |
|
501 | WAIT UNTIL clk25MHz = '1'; | |
521 | WAIT UNTIL clk25MHz = '1'; |
|
502 | WAIT UNTIL clk25MHz = '1'; | |
522 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); |
|
503 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); | |
523 | WAIT UNTIL clk25MHz = '1'; |
|
504 | WAIT UNTIL clk25MHz = '1'; | |
524 | coarse_time <= X"00000010"; |
|
505 | coarse_time <= X"00000010"; | |
525 | WAIT FOR 100 ms; |
|
506 | WAIT FOR 100 ms; | |
526 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
507 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
527 | WAIT FOR 10 us; |
|
508 | WAIT FOR 10 us; | |
528 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); |
|
509 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); | |
529 | WAIT FOR 200 ms; |
|
510 | WAIT FOR 200 ms; | |
530 | REPORT "*** END simulation ***" SEVERITY failure; |
|
511 | REPORT "*** END simulation ***" SEVERITY failure; | |
531 |
|
512 | |||
532 |
|
513 | |||
533 | WAIT; |
|
514 | WAIT; | |
534 |
|
515 | |||
535 | END PROCESS WaveGen_Proc; |
|
516 | END PROCESS WaveGen_Proc; | |
536 | ----------------------------------------------------------------------------- |
|
517 | ----------------------------------------------------------------------------- | |
537 |
|
518 | |||
538 | ----------------------------------------------------------------------------- |
|
519 | ----------------------------------------------------------------------------- | |
539 | -- IRQ |
|
520 | -- IRQ | |
540 | ----------------------------------------------------------------------------- |
|
521 | ----------------------------------------------------------------------------- | |
541 | PROCESS (clk25MHz, rstn) |
|
522 | PROCESS (clk25MHz, rstn) | |
542 | BEGIN -- PROCESS |
|
523 | BEGIN -- PROCESS | |
543 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
524 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
544 |
|
525 | |||
545 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
526 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge | |
546 |
|
527 | |||
547 | END IF; |
|
528 | END IF; | |
548 | END PROCESS; |
|
529 | END PROCESS; | |
549 | ----------------------------------------------------------------------------- |
|
530 | ----------------------------------------------------------------------------- | |
550 |
|
531 | |||
551 | END; |
|
532 | END; |
1 | NO CONTENT: file renamed from lib/lpp/lpp_sim/CY7C1061DV33/vhdlsyn.txt to lib/lpp/lpp_sim/CY7C1061DV33/vhdlsim.txt |
|
NO CONTENT: file renamed from lib/lpp/lpp_sim/CY7C1061DV33/vhdlsyn.txt to lib/lpp/lpp_sim/CY7C1061DV33/vhdlsim.txt |
@@ -1,544 +1,544 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | USE ieee.numeric_std.ALL; |
|
25 | USE ieee.numeric_std.ALL; | |
26 | LIBRARY grlib; |
|
26 | LIBRARY grlib; | |
27 | USE grlib.amba.ALL; |
|
27 | USE grlib.amba.ALL; | |
28 | USE grlib.stdlib.ALL; |
|
28 | USE grlib.stdlib.ALL; | |
29 | USE grlib.devices.ALL; |
|
29 | USE grlib.devices.ALL; | |
30 | LIBRARY lpp; |
|
30 | LIBRARY lpp; | |
31 | USE lpp.lpp_amba.ALL; |
|
31 | USE lpp.lpp_amba.ALL; | |
32 | USE lpp.apb_devices_list.ALL; |
|
32 | USE lpp.apb_devices_list.ALL; | |
33 | USE lpp.lpp_memory.ALL; |
|
33 | USE lpp.lpp_memory.ALL; | |
34 | LIBRARY techmap; |
|
34 | LIBRARY techmap; | |
35 | USE techmap.gencomp.ALL; |
|
35 | USE techmap.gencomp.ALL; | |
36 |
|
36 | |||
37 | ENTITY lpp_lfr_apbreg IS |
|
37 | ENTITY lpp_lfr_apbreg IS | |
38 | GENERIC ( |
|
38 | GENERIC ( | |
39 | nb_data_by_buffer_size : INTEGER := 11; |
|
39 | nb_data_by_buffer_size : INTEGER := 11; | |
40 | nb_word_by_buffer_size : INTEGER := 11; |
|
40 | nb_word_by_buffer_size : INTEGER := 11; | |
41 | nb_snapshot_param_size : INTEGER := 11; |
|
41 | nb_snapshot_param_size : INTEGER := 11; | |
42 | delta_vector_size : INTEGER := 20; |
|
42 | delta_vector_size : INTEGER := 20; | |
43 | delta_vector_size_f0_2 : INTEGER := 3; |
|
43 | delta_vector_size_f0_2 : INTEGER := 3; | |
44 |
|
44 | |||
45 | pindex : INTEGER := 4; |
|
45 | pindex : INTEGER := 4; | |
46 | paddr : INTEGER := 4; |
|
46 | paddr : INTEGER := 4; | |
47 | pmask : INTEGER := 16#fff#; |
|
47 | pmask : INTEGER := 16#fff#; | |
48 | pirq_ms : INTEGER := 0; |
|
48 | pirq_ms : INTEGER := 0; | |
49 | pirq_wfp : INTEGER := 1; |
|
49 | pirq_wfp : INTEGER := 1; | |
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
51 | PORT ( |
|
51 | PORT ( | |
52 | -- AMBA AHB system signals |
|
52 | -- AMBA AHB system signals | |
53 | HCLK : IN STD_ULOGIC; |
|
53 | HCLK : IN STD_ULOGIC; | |
54 | HRESETn : IN STD_ULOGIC; |
|
54 | HRESETn : IN STD_ULOGIC; | |
55 |
|
55 | |||
56 | -- AMBA APB Slave Interface |
|
56 | -- AMBA APB Slave Interface | |
57 | apbi : IN apb_slv_in_type; |
|
57 | apbi : IN apb_slv_in_type; | |
58 | apbo : OUT apb_slv_out_type; |
|
58 | apbo : OUT apb_slv_out_type; | |
59 |
|
59 | |||
60 | --------------------------------------------------------------------------- |
|
60 | --------------------------------------------------------------------------- | |
61 | -- Spectral Matrix Reg |
|
61 | -- Spectral Matrix Reg | |
62 | run_ms : OUT STD_LOGIC; |
|
62 | run_ms : OUT STD_LOGIC; | |
63 | -- IN |
|
63 | -- IN | |
64 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
65 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
66 | ready_matrix_f1 : IN STD_LOGIC; |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
67 | ready_matrix_f2 : IN STD_LOGIC; |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
68 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
68 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
69 | error_bad_component_error : IN STD_LOGIC; |
|
69 | error_bad_component_error : IN STD_LOGIC; | |
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
71 |
|
71 | |||
72 | -- OUT |
|
72 | -- OUT | |
73 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
73 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
75 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
75 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
76 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
76 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
78 | status_error_bad_component_error : OUT STD_LOGIC; |
|
78 | status_error_bad_component_error : OUT STD_LOGIC; | |
79 |
|
79 | |||
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
81 | config_active_interruption_onError : OUT STD_LOGIC; |
|
81 | config_active_interruption_onError : OUT STD_LOGIC; | |
82 |
|
82 | |||
83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
87 |
|
87 | |||
88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
92 |
|
92 | |||
93 | --------------------------------------------------------------------------- |
|
93 | --------------------------------------------------------------------------- | |
94 | --------------------------------------------------------------------------- |
|
94 | --------------------------------------------------------------------------- | |
95 | -- WaveForm picker Reg |
|
95 | -- WaveForm picker Reg | |
96 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
96 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
97 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
97 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
98 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
98 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
99 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
99 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
100 |
|
100 | |||
101 | -- OUT |
|
101 | -- OUT | |
102 | data_shaping_BW : OUT STD_LOGIC; |
|
102 | data_shaping_BW : OUT STD_LOGIC; | |
103 | data_shaping_SP0 : OUT STD_LOGIC; |
|
103 | data_shaping_SP0 : OUT STD_LOGIC; | |
104 | data_shaping_SP1 : OUT STD_LOGIC; |
|
104 | data_shaping_SP1 : OUT STD_LOGIC; | |
105 | data_shaping_R0 : OUT STD_LOGIC; |
|
105 | data_shaping_R0 : OUT STD_LOGIC; | |
106 | data_shaping_R1 : OUT STD_LOGIC; |
|
106 | data_shaping_R1 : OUT STD_LOGIC; | |
107 |
|
107 | |||
108 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
108 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
109 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
109 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
110 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
110 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
111 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
111 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
112 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
112 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
113 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
113 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
114 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
114 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
115 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
115 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
116 |
|
116 | |||
117 | enable_f0 : OUT STD_LOGIC; |
|
117 | enable_f0 : OUT STD_LOGIC; | |
118 | enable_f1 : OUT STD_LOGIC; |
|
118 | enable_f1 : OUT STD_LOGIC; | |
119 | enable_f2 : OUT STD_LOGIC; |
|
119 | enable_f2 : OUT STD_LOGIC; | |
120 | enable_f3 : OUT STD_LOGIC; |
|
120 | enable_f3 : OUT STD_LOGIC; | |
121 |
|
121 | |||
122 | burst_f0 : OUT STD_LOGIC; |
|
122 | burst_f0 : OUT STD_LOGIC; | |
123 | burst_f1 : OUT STD_LOGIC; |
|
123 | burst_f1 : OUT STD_LOGIC; | |
124 | burst_f2 : OUT STD_LOGIC; |
|
124 | burst_f2 : OUT STD_LOGIC; | |
125 |
|
125 | |||
126 | run : OUT STD_LOGIC; |
|
126 | run : OUT STD_LOGIC; | |
127 |
|
127 | |||
128 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
128 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
129 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
130 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
131 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
131 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
132 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
132 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
133 | --------------------------------------------------------------------------- |
|
133 | --------------------------------------------------------------------------- | |
134 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
134 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
135 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
135 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
136 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
136 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
137 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
137 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
138 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
138 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
139 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
139 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
140 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
141 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
141 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
142 |
|
142 | |||
143 | --------------------------------------------------------------------------- |
|
143 | --------------------------------------------------------------------------- | |
144 | ); |
|
144 | ); | |
145 |
|
145 | |||
146 | END lpp_lfr_apbreg; |
|
146 | END lpp_lfr_apbreg; | |
147 |
|
147 | |||
148 | ARCHITECTURE beh OF lpp_lfr_apbreg IS |
|
148 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
149 |
|
149 | |||
150 | CONSTANT REVISION : INTEGER := 1; |
|
150 | CONSTANT REVISION : INTEGER := 1; | |
151 |
|
151 | |||
152 | CONSTANT pconfig : apb_config_type := ( |
|
152 | CONSTANT pconfig : apb_config_type := ( | |
153 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), |
|
153 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
154 | 1 => apb_iobar(paddr, pmask)); |
|
154 | 1 => apb_iobar(paddr, pmask)); | |
155 |
|
155 | |||
156 | TYPE lpp_SpectralMatrix_regs IS RECORD |
|
156 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
157 | config_active_interruption_onNewMatrix : STD_LOGIC; |
|
157 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
158 | config_active_interruption_onError : STD_LOGIC; |
|
158 | config_active_interruption_onError : STD_LOGIC; | |
159 | config_ms_run : STD_LOGIC; |
|
159 | config_ms_run : STD_LOGIC; | |
160 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
160 | status_ready_matrix_f0_0 : STD_LOGIC; | |
161 | status_ready_matrix_f0_1 : STD_LOGIC; |
|
161 | status_ready_matrix_f0_1 : STD_LOGIC; | |
162 | status_ready_matrix_f1 : STD_LOGIC; |
|
162 | status_ready_matrix_f1 : STD_LOGIC; | |
163 | status_ready_matrix_f2 : STD_LOGIC; |
|
163 | status_ready_matrix_f2 : STD_LOGIC; | |
164 | status_error_anticipating_empty_fifo : STD_LOGIC; |
|
164 | status_error_anticipating_empty_fifo : STD_LOGIC; | |
165 | status_error_bad_component_error : STD_LOGIC; |
|
165 | status_error_bad_component_error : STD_LOGIC; | |
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
170 |
|
170 | |||
171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 |
|
175 | |||
176 |
|
|
176 | -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
177 | fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
177 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
178 | fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
178 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
179 | fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
179 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
180 | END RECORD; |
|
180 | END RECORD; | |
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
182 |
|
182 | |||
183 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
183 | TYPE lpp_WaveformPicker_regs IS RECORD | |
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 | data_shaping_BW : STD_LOGIC; |
|
187 | data_shaping_BW : STD_LOGIC; | |
188 | data_shaping_SP0 : STD_LOGIC; |
|
188 | data_shaping_SP0 : STD_LOGIC; | |
189 | data_shaping_SP1 : STD_LOGIC; |
|
189 | data_shaping_SP1 : STD_LOGIC; | |
190 | data_shaping_R0 : STD_LOGIC; |
|
190 | data_shaping_R0 : STD_LOGIC; | |
191 | data_shaping_R1 : STD_LOGIC; |
|
191 | data_shaping_R1 : STD_LOGIC; | |
192 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
192 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
193 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
193 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
194 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
194 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
195 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
195 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
196 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
196 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
197 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
197 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
198 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
198 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
199 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
199 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
200 | enable_f0 : STD_LOGIC; |
|
200 | enable_f0 : STD_LOGIC; | |
201 | enable_f1 : STD_LOGIC; |
|
201 | enable_f1 : STD_LOGIC; | |
202 | enable_f2 : STD_LOGIC; |
|
202 | enable_f2 : STD_LOGIC; | |
203 | enable_f3 : STD_LOGIC; |
|
203 | enable_f3 : STD_LOGIC; | |
204 | burst_f0 : STD_LOGIC; |
|
204 | burst_f0 : STD_LOGIC; | |
205 | burst_f1 : STD_LOGIC; |
|
205 | burst_f1 : STD_LOGIC; | |
206 | burst_f2 : STD_LOGIC; |
|
206 | burst_f2 : STD_LOGIC; | |
207 | run : STD_LOGIC; |
|
207 | run : STD_LOGIC; | |
208 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
208 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
209 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
209 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
210 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
210 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
211 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
211 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
212 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
212 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
213 | END RECORD; |
|
213 | END RECORD; | |
214 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
214 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
215 |
|
215 | |||
216 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
216 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
217 |
|
217 | |||
218 | ----------------------------------------------------------------------------- |
|
218 | ----------------------------------------------------------------------------- | |
219 | -- IRQ |
|
219 | -- IRQ | |
220 | ----------------------------------------------------------------------------- |
|
220 | ----------------------------------------------------------------------------- | |
221 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; |
|
221 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
222 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
222 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
223 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
223 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
224 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
224 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
225 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
225 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
226 | SIGNAL ored_irq_wfp : STD_LOGIC; |
|
226 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
227 |
|
227 | |||
228 | BEGIN -- beh |
|
228 | BEGIN -- beh | |
229 |
|
229 | |||
230 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; |
|
230 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; |
|
231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
232 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
|
232 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
233 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
|
233 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; |
|
234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; |
|
235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
236 |
|
236 | |||
237 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
237 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
238 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
238 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
239 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; |
|
239 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; |
|
240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
241 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; |
|
241 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
242 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; |
|
242 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
243 |
|
243 | |||
244 |
|
244 | |||
245 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; |
|
245 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
246 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; |
|
246 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
247 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; |
|
247 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
248 | data_shaping_R0 <= reg_wp.data_shaping_R0; |
|
248 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
249 | data_shaping_R1 <= reg_wp.data_shaping_R1; |
|
249 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
250 |
|
250 | |||
251 | delta_snapshot <= reg_wp.delta_snapshot; |
|
251 | delta_snapshot <= reg_wp.delta_snapshot; | |
252 | delta_f0 <= reg_wp.delta_f0; |
|
252 | delta_f0 <= reg_wp.delta_f0; | |
253 | delta_f0_2 <= reg_wp.delta_f0_2; |
|
253 | delta_f0_2 <= reg_wp.delta_f0_2; | |
254 | delta_f1 <= reg_wp.delta_f1; |
|
254 | delta_f1 <= reg_wp.delta_f1; | |
255 | delta_f2 <= reg_wp.delta_f2; |
|
255 | delta_f2 <= reg_wp.delta_f2; | |
256 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
256 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
257 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; |
|
257 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
258 | nb_snapshot_param <= reg_wp.nb_snapshot_param; |
|
258 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
259 |
|
259 | |||
260 | enable_f0 <= reg_wp.enable_f0; |
|
260 | enable_f0 <= reg_wp.enable_f0; | |
261 | enable_f1 <= reg_wp.enable_f1; |
|
261 | enable_f1 <= reg_wp.enable_f1; | |
262 | enable_f2 <= reg_wp.enable_f2; |
|
262 | enable_f2 <= reg_wp.enable_f2; | |
263 | enable_f3 <= reg_wp.enable_f3; |
|
263 | enable_f3 <= reg_wp.enable_f3; | |
264 |
|
264 | |||
265 | burst_f0 <= reg_wp.burst_f0; |
|
265 | burst_f0 <= reg_wp.burst_f0; | |
266 | burst_f1 <= reg_wp.burst_f1; |
|
266 | burst_f1 <= reg_wp.burst_f1; | |
267 | burst_f2 <= reg_wp.burst_f2; |
|
267 | burst_f2 <= reg_wp.burst_f2; | |
268 |
|
268 | |||
269 | run <= reg_wp.run; |
|
269 | run <= reg_wp.run; | |
270 |
|
270 | |||
271 | addr_data_f0 <= reg_wp.addr_data_f0; |
|
271 | addr_data_f0 <= reg_wp.addr_data_f0; | |
272 | addr_data_f1 <= reg_wp.addr_data_f1; |
|
272 | addr_data_f1 <= reg_wp.addr_data_f1; | |
273 | addr_data_f2 <= reg_wp.addr_data_f2; |
|
273 | addr_data_f2 <= reg_wp.addr_data_f2; | |
274 | addr_data_f3 <= reg_wp.addr_data_f3; |
|
274 | addr_data_f3 <= reg_wp.addr_data_f3; | |
275 |
|
275 | |||
276 | start_date <= reg_wp.start_date; |
|
276 | start_date <= reg_wp.start_date; | |
277 |
|
277 | |||
278 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
278 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
279 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
279 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
280 | BEGIN -- PROCESS lpp_dma_top |
|
280 | BEGIN -- PROCESS lpp_dma_top | |
281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; |
|
282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
283 | reg_sp.config_active_interruption_onError <= '0'; |
|
283 | reg_sp.config_active_interruption_onError <= '0'; | |
284 | reg_sp.config_ms_run <= '1'; |
|
284 | reg_sp.config_ms_run <= '1'; | |
285 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
285 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; |
|
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
287 | reg_sp.status_ready_matrix_f1 <= '0'; |
|
287 | reg_sp.status_ready_matrix_f1 <= '0'; | |
288 | reg_sp.status_ready_matrix_f2 <= '0'; |
|
288 | reg_sp.status_ready_matrix_f2 <= '0'; | |
289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; |
|
289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
290 | reg_sp.status_error_bad_component_error <= '0'; |
|
290 | reg_sp.status_error_bad_component_error <= '0'; | |
291 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); |
|
291 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); |
|
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); |
|
293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); |
|
294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
295 |
|
295 | |||
296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); |
|
296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); | |
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); |
|
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); |
|
298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); | |
299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); |
|
299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
300 | reg_sp.fine_time_f0_0 <= (OTHERS => '0'); |
|
300 | --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); | |
301 | reg_sp.fine_time_f0_1 <= (OTHERS => '0'); |
|
301 | --reg_sp.fine_time_f0_1 <= (OTHERS => '0'); | |
302 | reg_sp.fine_time_f1 <= (OTHERS => '0'); |
|
302 | --reg_sp.fine_time_f1 <= (OTHERS => '0'); | |
303 | reg_sp.fine_time_f2 <= (OTHERS => '0'); |
|
303 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
304 |
|
304 | |||
305 | prdata <= (OTHERS => '0'); |
|
305 | prdata <= (OTHERS => '0'); | |
306 |
|
306 | |||
307 | apbo.pirq <= (OTHERS => '0'); |
|
307 | apbo.pirq <= (OTHERS => '0'); | |
308 |
|
308 | |||
309 | status_full_ack <= (OTHERS => '0'); |
|
309 | status_full_ack <= (OTHERS => '0'); | |
310 |
|
310 | |||
311 | reg_wp.data_shaping_BW <= '0'; |
|
311 | reg_wp.data_shaping_BW <= '0'; | |
312 | reg_wp.data_shaping_SP0 <= '0'; |
|
312 | reg_wp.data_shaping_SP0 <= '0'; | |
313 | reg_wp.data_shaping_SP1 <= '0'; |
|
313 | reg_wp.data_shaping_SP1 <= '0'; | |
314 | reg_wp.data_shaping_R0 <= '0'; |
|
314 | reg_wp.data_shaping_R0 <= '0'; | |
315 | reg_wp.data_shaping_R1 <= '0'; |
|
315 | reg_wp.data_shaping_R1 <= '0'; | |
316 | reg_wp.enable_f0 <= '0'; |
|
316 | reg_wp.enable_f0 <= '0'; | |
317 | reg_wp.enable_f1 <= '0'; |
|
317 | reg_wp.enable_f1 <= '0'; | |
318 | reg_wp.enable_f2 <= '0'; |
|
318 | reg_wp.enable_f2 <= '0'; | |
319 | reg_wp.enable_f3 <= '0'; |
|
319 | reg_wp.enable_f3 <= '0'; | |
320 | reg_wp.burst_f0 <= '0'; |
|
320 | reg_wp.burst_f0 <= '0'; | |
321 | reg_wp.burst_f1 <= '0'; |
|
321 | reg_wp.burst_f1 <= '0'; | |
322 | reg_wp.burst_f2 <= '0'; |
|
322 | reg_wp.burst_f2 <= '0'; | |
323 | reg_wp.run <= '0'; |
|
323 | reg_wp.run <= '0'; | |
324 | reg_wp.addr_data_f0 <= (OTHERS => '0'); |
|
324 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
325 | reg_wp.addr_data_f1 <= (OTHERS => '0'); |
|
325 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
326 | reg_wp.addr_data_f2 <= (OTHERS => '0'); |
|
326 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
327 | reg_wp.addr_data_f3 <= (OTHERS => '0'); |
|
327 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
328 | reg_wp.status_full <= (OTHERS => '0'); |
|
328 | reg_wp.status_full <= (OTHERS => '0'); | |
329 | reg_wp.status_full_err <= (OTHERS => '0'); |
|
329 | reg_wp.status_full_err <= (OTHERS => '0'); | |
330 | reg_wp.status_new_err <= (OTHERS => '0'); |
|
330 | reg_wp.status_new_err <= (OTHERS => '0'); | |
331 | reg_wp.delta_snapshot <= (OTHERS => '0'); |
|
331 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
332 | reg_wp.delta_f0 <= (OTHERS => '0'); |
|
332 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
333 | reg_wp.delta_f0_2 <= (OTHERS => '0'); |
|
333 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
334 | reg_wp.delta_f1 <= (OTHERS => '0'); |
|
334 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
335 | reg_wp.delta_f2 <= (OTHERS => '0'); |
|
335 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
336 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
336 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
337 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); |
|
337 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
338 | reg_wp.start_date <= (OTHERS => '0'); |
|
338 | reg_wp.start_date <= (OTHERS => '0'); | |
339 |
|
339 | |||
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
341 |
|
341 | |||
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); |
|
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); |
|
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); |
|
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); |
|
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
346 |
|
346 | |||
347 | reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); |
|
347 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
348 | reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); |
|
348 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
349 | reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); |
|
349 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
350 | reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); |
|
350 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
351 |
|
351 | |||
352 | status_full_ack <= (OTHERS => '0'); |
|
352 | status_full_ack <= (OTHERS => '0'); | |
353 |
|
353 | |||
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
|
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; |
|
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
356 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; |
|
356 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
357 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; |
|
357 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
358 |
|
358 | |||
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
|
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
360 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
|
360 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
361 | all_status: FOR I IN 3 DOWNTO 0 LOOP |
|
361 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
362 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; |
|
362 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
363 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; |
|
363 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
364 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; |
|
364 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
365 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; |
|
365 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
366 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; |
|
366 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
367 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; |
|
367 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
368 | END LOOP all_status; |
|
368 | END LOOP all_status; | |
369 |
|
369 | |||
370 | paddr := "000000"; |
|
370 | paddr := "000000"; | |
371 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
371 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
372 | prdata <= (OTHERS => '0'); |
|
372 | prdata <= (OTHERS => '0'); | |
373 | IF apbi.psel(pindex) = '1' THEN |
|
373 | IF apbi.psel(pindex) = '1' THEN | |
374 | -- APB DMA READ -- |
|
374 | -- APB DMA READ -- | |
375 | CASE paddr(7 DOWNTO 2) IS |
|
375 | CASE paddr(7 DOWNTO 2) IS | |
376 | -- |
|
376 | -- | |
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
378 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
378 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
379 | prdata(2) <= reg_sp.config_ms_run; |
|
379 | prdata(2) <= reg_sp.config_ms_run; | |
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; |
|
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; |
|
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
383 | prdata(3) <= reg_sp.status_ready_matrix_f2; |
|
383 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; |
|
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
385 | prdata(5) <= reg_sp.status_error_bad_component_error; |
|
385 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
386 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; |
|
386 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; |
|
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; |
|
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; |
|
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
390 |
|
390 | |||
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; |
|
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; |
|
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; |
|
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; |
|
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; | |
395 |
WHEN "001010" => prdata(15 downto 0) <= |
|
395 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; | |
396 |
WHEN "001011" => prdata(15 downto 0) <= |
|
396 | WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
397 |
WHEN "001100" => prdata(15 downto 0) <= |
|
397 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; | |
398 |
WHEN "001101" => prdata(15 downto 0) <= |
|
398 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; | |
399 |
|
399 | |||
400 | WHEN "001111" => prdata <= debug_reg; |
|
400 | WHEN "001111" => prdata <= debug_reg; | |
401 | --------------------------------------------------------------------- |
|
401 | --------------------------------------------------------------------- | |
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; |
|
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; | |
403 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
403 | prdata(1) <= reg_wp.data_shaping_SP0; | |
404 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
404 | prdata(2) <= reg_wp.data_shaping_SP1; | |
405 | prdata(3) <= reg_wp.data_shaping_R0; |
|
405 | prdata(3) <= reg_wp.data_shaping_R0; | |
406 | prdata(4) <= reg_wp.data_shaping_R1; |
|
406 | prdata(4) <= reg_wp.data_shaping_R1; | |
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; |
|
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
408 | prdata(1) <= reg_wp.enable_f1; |
|
408 | prdata(1) <= reg_wp.enable_f1; | |
409 | prdata(2) <= reg_wp.enable_f2; |
|
409 | prdata(2) <= reg_wp.enable_f2; | |
410 | prdata(3) <= reg_wp.enable_f3; |
|
410 | prdata(3) <= reg_wp.enable_f3; | |
411 | prdata(4) <= reg_wp.burst_f0; |
|
411 | prdata(4) <= reg_wp.burst_f0; | |
412 | prdata(5) <= reg_wp.burst_f1; |
|
412 | prdata(5) <= reg_wp.burst_f1; | |
413 | prdata(6) <= reg_wp.burst_f2; |
|
413 | prdata(6) <= reg_wp.burst_f2; | |
414 | prdata(7) <= reg_wp.run; |
|
414 | prdata(7) <= reg_wp.run; | |
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; |
|
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; |
|
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; | |
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; |
|
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; |
|
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; | |
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; |
|
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
|
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; |
|
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; |
|
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; |
|
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; |
|
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; |
|
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; |
|
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
|
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; |
|
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; |
|
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
431 | ---------------------------------------------------- |
|
431 | ---------------------------------------------------- | |
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); |
|
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); |
|
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
434 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); |
|
434 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
435 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); |
|
435 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); | |
436 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); |
|
436 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
437 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); |
|
437 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); | |
438 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); |
|
438 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
439 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); |
|
439 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); | |
440 | ---------------------------------------------------- |
|
440 | ---------------------------------------------------- | |
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
442 | WHEN OTHERS => NULL; |
|
442 | WHEN OTHERS => NULL; | |
443 |
|
443 | |||
444 | END CASE; |
|
444 | END CASE; | |
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
446 | -- APB DMA WRITE -- |
|
446 | -- APB DMA WRITE -- | |
447 | CASE paddr(7 DOWNTO 2) IS |
|
447 | CASE paddr(7 DOWNTO 2) IS | |
448 | -- |
|
448 | -- | |
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
451 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
451 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
|
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); |
|
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); |
|
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
455 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); |
|
455 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); |
|
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
457 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); |
|
457 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |
458 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; |
|
458 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; |
|
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; |
|
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; |
|
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
462 | -- |
|
462 | -- | |
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); |
|
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
|
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); |
|
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
469 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
469 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
470 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
470 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
471 | reg_wp.enable_f3 <= apbi.pwdata(3); |
|
471 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
472 | reg_wp.burst_f0 <= apbi.pwdata(4); |
|
472 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
473 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
473 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
474 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
474 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
475 | reg_wp.run <= apbi.pwdata(7); |
|
475 | reg_wp.run <= apbi.pwdata(7); | |
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; |
|
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; |
|
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; |
|
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; |
|
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); |
|
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); |
|
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); |
|
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); |
|
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); |
|
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); |
|
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
496 | -- |
|
496 | -- | |
497 | WHEN OTHERS => NULL; |
|
497 | WHEN OTHERS => NULL; | |
498 | END CASE; |
|
498 | END CASE; | |
499 | END IF; |
|
499 | END IF; | |
500 | END IF; |
|
500 | END IF; | |
501 |
|
501 | |||
502 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR |
|
502 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
503 | ready_matrix_f0_1 OR |
|
503 | ready_matrix_f0_1 OR | |
504 | ready_matrix_f1 OR |
|
504 | ready_matrix_f1 OR | |
505 | ready_matrix_f2) |
|
505 | ready_matrix_f2) | |
506 | ) |
|
506 | ) | |
507 | OR |
|
507 | OR | |
508 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR |
|
508 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |
509 | error_bad_component_error) |
|
509 | error_bad_component_error) | |
510 | )); |
|
510 | )); | |
511 |
|
511 | |||
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; |
|
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
513 |
|
513 | |||
514 | END IF; |
|
514 | END IF; | |
515 | END PROCESS lpp_lfr_apbreg; |
|
515 | END PROCESS lpp_lfr_apbreg; | |
516 |
|
516 | |||
517 | apbo.pindex <= pindex; |
|
517 | apbo.pindex <= pindex; | |
518 | apbo.pconfig <= pconfig; |
|
518 | apbo.pconfig <= pconfig; | |
519 | apbo.prdata <= prdata; |
|
519 | apbo.prdata <= prdata; | |
520 |
|
520 | |||
521 | ----------------------------------------------------------------------------- |
|
521 | ----------------------------------------------------------------------------- | |
522 | -- IRQ |
|
522 | -- IRQ | |
523 | ----------------------------------------------------------------------------- |
|
523 | ----------------------------------------------------------------------------- | |
524 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; |
|
524 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |
525 |
|
525 | |||
526 | PROCESS (HCLK, HRESETn) |
|
526 | PROCESS (HCLK, HRESETn) | |
527 | BEGIN -- PROCESS |
|
527 | BEGIN -- PROCESS | |
528 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
528 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
529 | irq_wfp_reg <= (OTHERS => '0'); |
|
529 | irq_wfp_reg <= (OTHERS => '0'); | |
530 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge |
|
530 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
531 | irq_wfp_reg <= irq_wfp_reg_s; |
|
531 | irq_wfp_reg <= irq_wfp_reg_s; | |
532 | END IF; |
|
532 | END IF; | |
533 | END PROCESS; |
|
533 | END PROCESS; | |
534 |
|
534 | |||
535 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE |
|
535 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
536 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); |
|
536 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
537 | END GENERATE all_irq_wfp; |
|
537 | END GENERATE all_irq_wfp; | |
538 |
|
538 | |||
539 | irq_wfp_ZERO <= (OTHERS => '0'); |
|
539 | irq_wfp_ZERO <= (OTHERS => '0'); | |
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; |
|
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
541 |
|
541 | |||
542 | run_ms <= reg_sp.config_ms_run; |
|
542 | run_ms <= reg_sp.config_ms_run; | |
543 |
|
543 | |||
544 | END beh; |
|
544 | END beh; |
@@ -1,414 +1,374 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY lpp; |
|
4 | LIBRARY lpp; | |
5 | USE lpp.lpp_amba.ALL; |
|
5 | USE lpp.lpp_amba.ALL; | |
6 | USE lpp.lpp_memory.ALL; |
|
6 | USE lpp.lpp_memory.ALL; | |
7 | --USE lpp.lpp_uart.ALL; |
|
7 | --USE lpp.lpp_uart.ALL; | |
8 | USE lpp.lpp_matrix.ALL; |
|
8 | USE lpp.lpp_matrix.ALL; | |
9 | --USE lpp.lpp_delay.ALL; |
|
9 | --USE lpp.lpp_delay.ALL; | |
10 | USE lpp.lpp_fft.ALL; |
|
10 | USE lpp.lpp_fft.ALL; | |
11 | USE lpp.fft_components.ALL; |
|
11 | USE lpp.fft_components.ALL; | |
12 | USE lpp.lpp_ad_conv.ALL; |
|
12 | USE lpp.lpp_ad_conv.ALL; | |
13 | USE lpp.iir_filter.ALL; |
|
13 | USE lpp.iir_filter.ALL; | |
14 | USE lpp.general_purpose.ALL; |
|
14 | USE lpp.general_purpose.ALL; | |
15 | USE lpp.Filtercfg.ALL; |
|
15 | USE lpp.Filtercfg.ALL; | |
16 | USE lpp.lpp_demux.ALL; |
|
16 | USE lpp.lpp_demux.ALL; | |
17 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
17 | USE lpp.lpp_top_lfr_pkg.ALL; | |
18 | USE lpp.lpp_dma_pkg.ALL; |
|
18 | USE lpp.lpp_dma_pkg.ALL; | |
19 | USE lpp.lpp_Header.ALL; |
|
19 | USE lpp.lpp_Header.ALL; | |
20 | USE lpp.lpp_lfr_pkg.ALL; |
|
20 | USE lpp.lpp_lfr_pkg.ALL; | |
21 |
|
21 | |||
22 | LIBRARY grlib; |
|
22 | LIBRARY grlib; | |
23 | USE grlib.amba.ALL; |
|
23 | USE grlib.amba.ALL; | |
24 | USE grlib.stdlib.ALL; |
|
24 | USE grlib.stdlib.ALL; | |
25 | USE grlib.devices.ALL; |
|
25 | USE grlib.devices.ALL; | |
26 | USE GRLIB.DMA2AHB_Package.ALL; |
|
26 | USE GRLIB.DMA2AHB_Package.ALL; | |
27 |
|
27 | |||
28 |
|
28 | |||
29 | ENTITY lpp_lfr_ms IS |
|
29 | ENTITY lpp_lfr_ms IS | |
30 | GENERIC ( |
|
30 | GENERIC ( | |
31 | Mem_use : INTEGER |
|
31 | Mem_use : INTEGER | |
32 | ); |
|
32 | ); | |
33 | PORT ( |
|
33 | PORT ( | |
34 | clk : IN STD_LOGIC; |
|
34 | clk : IN STD_LOGIC; | |
35 | rstn : IN STD_LOGIC; |
|
35 | rstn : IN STD_LOGIC; | |
36 |
|
36 | |||
37 | --------------------------------------------------------------------------- |
|
37 | --------------------------------------------------------------------------- | |
38 | -- DATA INPUT |
|
38 | -- DATA INPUT | |
39 | --------------------------------------------------------------------------- |
|
39 | --------------------------------------------------------------------------- | |
40 | -- TIME |
|
40 | -- TIME | |
41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
43 | -- |
|
43 | -- | |
44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
46 | -- |
|
46 | -- | |
47 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
48 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
48 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
49 | -- |
|
49 | -- | |
50 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
50 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
51 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
51 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
52 |
|
52 | |||
53 | --------------------------------------------------------------------------- |
|
53 | --------------------------------------------------------------------------- | |
54 | -- DMA |
|
54 | -- DMA | |
55 | --------------------------------------------------------------------------- |
|
55 | --------------------------------------------------------------------------- | |
56 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
56 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
57 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
57 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
58 | dma_valid : OUT STD_LOGIC; |
|
58 | dma_valid : OUT STD_LOGIC; | |
59 | dma_valid_burst : OUT STD_LOGIC; |
|
59 | dma_valid_burst : OUT STD_LOGIC; | |
60 | dma_ren : IN STD_LOGIC; |
|
60 | dma_ren : IN STD_LOGIC; | |
61 | dma_done : IN STD_LOGIC; |
|
61 | dma_done : IN STD_LOGIC; | |
62 |
|
62 | |||
63 | -- Reg out |
|
63 | -- Reg out | |
64 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
64 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
65 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
65 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
66 | ready_matrix_f1 : OUT STD_LOGIC; |
|
66 | ready_matrix_f1 : OUT STD_LOGIC; | |
67 | ready_matrix_f2 : OUT STD_LOGIC; |
|
67 | ready_matrix_f2 : OUT STD_LOGIC; | |
68 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
68 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
69 | error_bad_component_error : OUT STD_LOGIC; |
|
69 | error_bad_component_error : OUT STD_LOGIC; | |
70 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
70 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
71 |
|
71 | |||
72 | -- Reg In |
|
72 | -- Reg In | |
73 | status_ready_matrix_f0_0 :IN STD_LOGIC; |
|
73 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
74 | status_ready_matrix_f0_1 :IN STD_LOGIC; |
|
74 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
75 | status_ready_matrix_f1 :IN STD_LOGIC; |
|
75 | status_ready_matrix_f1 :IN STD_LOGIC; | |
76 | status_ready_matrix_f2 :IN STD_LOGIC; |
|
76 | status_ready_matrix_f2 :IN STD_LOGIC; | |
77 | status_error_anticipating_empty_fifo :IN STD_LOGIC; |
|
77 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
78 | status_error_bad_component_error :IN STD_LOGIC; |
|
78 | status_error_bad_component_error :IN STD_LOGIC; | |
79 |
|
79 | |||
80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
81 | config_active_interruption_onError : IN STD_LOGIC; |
|
81 | config_active_interruption_onError : IN STD_LOGIC; | |
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 |
|
86 | |||
87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
91 |
|
91 | |||
92 | ); |
|
92 | ); | |
93 | END; |
|
93 | END; | |
94 |
|
94 | |||
95 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
95 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
96 | ----------------------------------------------------------------------------- |
|
96 | ----------------------------------------------------------------------------- | |
97 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
97 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
98 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
98 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
99 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
99 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
100 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
100 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
101 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
101 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
102 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
102 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
103 |
|
103 | |||
104 | ----------------------------------------------------------------------------- |
|
104 | ----------------------------------------------------------------------------- | |
105 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); |
|
105 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); | |
106 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
106 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
107 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
107 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
108 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
108 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
109 |
|
109 | |||
110 | ----------------------------------------------------------------------------- |
|
110 | ----------------------------------------------------------------------------- | |
111 | SIGNAL FFT_Load : STD_LOGIC; |
|
111 | SIGNAL FFT_Load : STD_LOGIC; | |
112 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
112 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
113 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
113 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
114 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
114 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
115 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
115 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
116 |
|
116 | |||
117 | ----------------------------------------------------------------------------- |
|
117 | ----------------------------------------------------------------------------- | |
118 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
118 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
119 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
119 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
120 |
|
120 | |||
121 | ----------------------------------------------------------------------------- |
|
121 | ----------------------------------------------------------------------------- | |
122 | SIGNAL SM_FlagError : STD_LOGIC; |
|
122 | SIGNAL SM_FlagError : STD_LOGIC; | |
123 | -- SIGNAL SM_Pong : STD_LOGIC; |
|
123 | -- SIGNAL SM_Pong : STD_LOGIC; | |
124 | SIGNAL SM_Wen : STD_LOGIC; |
|
124 | SIGNAL SM_Wen : STD_LOGIC; | |
125 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
125 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
126 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
126 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
127 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
127 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
128 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
128 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
129 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
129 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
130 |
|
130 | |||
131 | ----------------------------------------------------------------------------- |
|
131 | ----------------------------------------------------------------------------- | |
132 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
132 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
133 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
133 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
134 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
134 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
135 |
|
135 | |||
136 | ----------------------------------------------------------------------------- |
|
136 | ----------------------------------------------------------------------------- | |
137 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
137 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
138 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
138 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
139 | SIGNAL Head_Empty : STD_LOGIC; |
|
139 | SIGNAL Head_Empty : STD_LOGIC; | |
140 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
141 | SIGNAL Head_Valid : STD_LOGIC; |
|
141 | SIGNAL Head_Valid : STD_LOGIC; | |
142 | SIGNAL Head_Val : STD_LOGIC; |
|
142 | SIGNAL Head_Val : STD_LOGIC; | |
143 |
|
143 | |||
144 | ----------------------------------------------------------------------------- |
|
144 | ----------------------------------------------------------------------------- | |
145 | SIGNAL DMA_Read : STD_LOGIC; |
|
145 | SIGNAL DMA_Read : STD_LOGIC; | |
146 | SIGNAL DMA_ack : STD_LOGIC; |
|
146 | SIGNAL DMA_ack : STD_LOGIC; | |
147 |
|
147 | |||
148 | ----------------------------------------------------------------------------- |
|
148 | ----------------------------------------------------------------------------- | |
149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
150 |
|
150 | |||
151 | BEGIN |
|
151 | BEGIN | |
152 |
|
152 | |||
153 | ----------------------------------------------------------------------------- |
|
153 | ----------------------------------------------------------------------------- | |
154 | Memf0: lppFIFOxN |
|
154 | Memf0: lppFIFOxN | |
155 | GENERIC MAP ( |
|
155 | GENERIC MAP ( | |
156 | tech => 0, Mem_use => Mem_use, Data_sz => 16, |
|
156 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
157 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') |
|
157 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |
158 | PORT MAP ( |
|
158 | PORT MAP ( | |
159 | rstn => rstn, wclk => clk, rclk => clk, |
|
159 | rstn => rstn, wclk => clk, rclk => clk, | |
160 | ReUse => (OTHERS => '0'), |
|
160 | ReUse => (OTHERS => '0'), | |
161 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), |
|
161 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), | |
162 | wdata => sample_f0_wdata, rdata => FifoF0_Data, |
|
162 | wdata => sample_f0_wdata, rdata => FifoF0_Data, | |
163 | full => OPEN, empty => FifoF0_Empty); |
|
163 | full => OPEN, empty => FifoF0_Empty); | |
164 |
|
164 | |||
165 | Memf1: lppFIFOxN |
|
165 | Memf1: lppFIFOxN | |
166 | GENERIC MAP ( |
|
166 | GENERIC MAP ( | |
167 | tech => 0, Mem_use => Mem_use, Data_sz => 16, |
|
167 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
168 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
168 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
169 | PORT MAP ( |
|
169 | PORT MAP ( | |
170 | rstn => rstn, wclk => clk, rclk => clk, |
|
170 | rstn => rstn, wclk => clk, rclk => clk, | |
171 | ReUse => (OTHERS => '0'), |
|
171 | ReUse => (OTHERS => '0'), | |
172 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), |
|
172 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), | |
173 | wdata => sample_f1_wdata, rdata => FifoF1_Data, |
|
173 | wdata => sample_f1_wdata, rdata => FifoF1_Data, | |
174 | full => OPEN, empty => FifoF1_Empty); |
|
174 | full => OPEN, empty => FifoF1_Empty); | |
175 |
|
175 | |||
176 |
|
176 | |||
177 | Memf2: lppFIFOxN |
|
177 | Memf2: lppFIFOxN | |
178 | GENERIC MAP ( |
|
178 | GENERIC MAP ( | |
179 | tech => 0, Mem_use => Mem_use, Data_sz => 16, |
|
179 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
180 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
180 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
181 | PORT MAP ( |
|
181 | PORT MAP ( | |
182 | rstn => rstn, wclk => clk, rclk => clk, |
|
182 | rstn => rstn, wclk => clk, rclk => clk, | |
183 | ReUse => (OTHERS => '0'), |
|
183 | ReUse => (OTHERS => '0'), | |
184 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), |
|
184 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), | |
185 | wdata => sample_f3_wdata, rdata => FifoF3_Data, |
|
185 | wdata => sample_f3_wdata, rdata => FifoF3_Data, | |
186 | full => OPEN, empty => FifoF3_Empty); |
|
186 | full => OPEN, empty => FifoF3_Empty); | |
187 | ----------------------------------------------------------------------------- |
|
187 | ----------------------------------------------------------------------------- | |
188 |
|
188 | |||
189 |
|
189 | |||
190 | ----------------------------------------------------------------------------- |
|
190 | ----------------------------------------------------------------------------- | |
191 | DMUX0 : DEMUX |
|
191 | DMUX0 : DEMUX | |
192 | GENERIC MAP ( |
|
192 | GENERIC MAP ( | |
193 | Data_sz => 16) |
|
193 | Data_sz => 16) | |
194 | PORT MAP ( |
|
194 | PORT MAP ( | |
195 | clk => clk, |
|
195 | clk => clk, | |
196 | rstn => rstn, |
|
196 | rstn => rstn, | |
197 | Read => FFT_Read, |
|
197 | Read => FFT_Read, | |
198 | Load => FFT_Load, |
|
198 | Load => FFT_Load, | |
199 | EmptyF0 => FifoF0_Empty, |
|
199 | EmptyF0 => FifoF0_Empty, | |
200 | EmptyF1 => FifoF1_Empty, |
|
200 | EmptyF1 => FifoF1_Empty, | |
201 | EmptyF2 => FifoF3_Empty, |
|
201 | EmptyF2 => FifoF3_Empty, | |
202 | DataF0 => FifoF0_Data, |
|
202 | DataF0 => FifoF0_Data, | |
203 | DataF1 => FifoF1_Data, |
|
203 | DataF1 => FifoF1_Data, | |
204 | DataF2 => FifoF3_Data, |
|
204 | DataF2 => FifoF3_Data, | |
205 | WorkFreq => DMUX_WorkFreq, |
|
205 | WorkFreq => DMUX_WorkFreq, | |
206 | Read_DEMUX => DMUX_Read, |
|
206 | Read_DEMUX => DMUX_Read, | |
207 | Empty => DMUX_Empty, |
|
207 | Empty => DMUX_Empty, | |
208 | Data => DMUX_Data); |
|
208 | Data => DMUX_Data); | |
209 | ----------------------------------------------------------------------------- |
|
209 | ----------------------------------------------------------------------------- | |
210 |
|
210 | |||
211 |
|
211 | |||
212 | ----------------------------------------------------------------------------- |
|
212 | ----------------------------------------------------------------------------- | |
213 | FFT0: FFT |
|
213 | FFT0: FFT | |
214 | GENERIC MAP ( |
|
214 | GENERIC MAP ( | |
215 | Data_sz => 16, |
|
215 | Data_sz => 16, | |
216 | NbData => 256) |
|
216 | NbData => 256) | |
217 | PORT MAP ( |
|
217 | PORT MAP ( | |
218 | clkm => clk, |
|
218 | clkm => clk, | |
219 | rstn => rstn, |
|
219 | rstn => rstn, | |
220 | FifoIN_Empty => DMUX_Empty, |
|
220 | FifoIN_Empty => DMUX_Empty, | |
221 | FifoIN_Data => DMUX_Data, |
|
221 | FifoIN_Data => DMUX_Data, | |
222 | FifoOUT_Full => FifoINT_Full, |
|
222 | FifoOUT_Full => FifoINT_Full, | |
223 | Load => FFT_Load, |
|
223 | Load => FFT_Load, | |
224 | Read => FFT_Read, |
|
224 | Read => FFT_Read, | |
225 | Write => FFT_Write, |
|
225 | Write => FFT_Write, | |
226 | ReUse => FFT_ReUse, |
|
226 | ReUse => FFT_ReUse, | |
227 | Data => FFT_Data); |
|
227 | Data => FFT_Data); | |
228 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
229 |
|
229 | |||
230 |
|
230 | |||
231 | ----------------------------------------------------------------------------- |
|
231 | ----------------------------------------------------------------------------- | |
232 | MemInt : lppFIFOxN |
|
232 | MemInt : lppFIFOxN | |
233 | GENERIC MAP ( |
|
233 | GENERIC MAP ( | |
234 | tech => 0, |
|
234 | tech => 0, | |
235 | Mem_use => Mem_use, |
|
235 | Mem_use => Mem_use, | |
236 | Data_sz => 16, |
|
236 | Data_sz => 16, | |
237 | Addr_sz => 8, |
|
237 | Addr_sz => 8, | |
238 | FifoCnt => 5, |
|
238 | FifoCnt => 5, | |
239 | Enable_ReUse => '1') |
|
239 | Enable_ReUse => '1') | |
240 | PORT MAP ( |
|
240 | PORT MAP ( | |
241 | rstn => rstn, |
|
241 | rstn => rstn, | |
242 | wclk => clk, |
|
242 | wclk => clk, | |
243 | rclk => clk, |
|
243 | rclk => clk, | |
244 | ReUse => SM_ReUse, |
|
244 | ReUse => SM_ReUse, | |
245 | wen => FFT_Write, |
|
245 | wen => FFT_Write, | |
246 | ren => SM_Read, |
|
246 | ren => SM_Read, | |
247 | wdata => FFT_Data, |
|
247 | wdata => FFT_Data, | |
248 | rdata => FifoINT_Data, |
|
248 | rdata => FifoINT_Data, | |
249 | full => FifoINT_Full, |
|
249 | full => FifoINT_Full, | |
250 | empty => OPEN); |
|
250 | empty => OPEN); | |
251 | ----------------------------------------------------------------------------- |
|
251 | ----------------------------------------------------------------------------- | |
252 |
|
252 | |||
253 | ----------------------------------------------------------------------------- |
|
253 | ----------------------------------------------------------------------------- | |
254 | SM0 : MatriceSpectrale |
|
254 | SM0 : MatriceSpectrale | |
255 | GENERIC MAP ( |
|
255 | GENERIC MAP ( | |
256 | Input_SZ => 16, |
|
256 | Input_SZ => 16, | |
257 | Result_SZ => 32) |
|
257 | Result_SZ => 32) | |
258 | PORT MAP ( |
|
258 | PORT MAP ( | |
259 | clkm => clk, |
|
259 | clkm => clk, | |
260 | rstn => rstn, |
|
260 | rstn => rstn, | |
261 | FifoIN_Full => FifoINT_Full, |
|
261 | FifoIN_Full => FifoINT_Full, | |
262 | SetReUse => FFT_ReUse, |
|
262 | SetReUse => FFT_ReUse, | |
263 | Valid => Head_Valid, |
|
263 | Valid => Head_Valid, | |
264 | Data_IN => FifoINT_Data, |
|
264 | Data_IN => FifoINT_Data, | |
265 | ACK => DMA_ack, |
|
265 | ACK => DMA_ack, | |
266 | SM_Write => SM_Wen, |
|
266 | SM_Write => SM_Wen, | |
267 | FlagError => SM_FlagError, |
|
267 | FlagError => SM_FlagError, | |
268 | -- Pong => SM_Pong, |
|
268 | -- Pong => SM_Pong, | |
269 | Statu => SM_Param, |
|
269 | Statu => SM_Param, | |
270 | Write => SM_Write, |
|
270 | Write => SM_Write, | |
271 | Read => SM_Read, |
|
271 | Read => SM_Read, | |
272 | ReUse => SM_ReUse, |
|
272 | ReUse => SM_ReUse, | |
273 | Data_OUT => SM_Data); |
|
273 | Data_OUT => SM_Data); | |
274 | ----------------------------------------------------------------------------- |
|
274 | ----------------------------------------------------------------------------- | |
275 |
|
275 | |||
276 | ----------------------------------------------------------------------------- |
|
276 | ----------------------------------------------------------------------------- | |
277 | MemOut : lppFIFOxN |
|
277 | MemOut : lppFIFOxN | |
278 | GENERIC MAP ( |
|
278 | GENERIC MAP ( | |
279 | tech => 0, |
|
279 | tech => 0, | |
280 | Mem_use => Mem_use, |
|
280 | Mem_use => Mem_use, | |
281 | Data_sz => 32, |
|
281 | Data_sz => 32, | |
282 | Addr_sz => 8, |
|
282 | Addr_sz => 8, | |
283 | FifoCnt => 2, |
|
283 | FifoCnt => 2, | |
284 | Enable_ReUse => '0') |
|
284 | Enable_ReUse => '0') | |
285 | PORT MAP ( |
|
285 | PORT MAP ( | |
286 | rstn => rstn, |
|
286 | rstn => rstn, | |
287 | wclk => clk, |
|
287 | wclk => clk, | |
288 | rclk => clk, |
|
288 | rclk => clk, | |
289 | ReUse => (OTHERS => '0'), |
|
289 | ReUse => (OTHERS => '0'), | |
290 | wen => SM_Write, |
|
290 | wen => SM_Write, | |
291 | ren => Head_Read, |
|
291 | ren => Head_Read, | |
292 | wdata => SM_Data, |
|
292 | wdata => SM_Data, | |
293 | rdata => FifoOUT_Data, |
|
293 | rdata => FifoOUT_Data, | |
294 | full => FifoOUT_Full, |
|
294 | full => FifoOUT_Full, | |
295 | empty => FifoOUT_Empty); |
|
295 | empty => FifoOUT_Empty); | |
296 | ----------------------------------------------------------------------------- |
|
296 | ----------------------------------------------------------------------------- | |
297 |
|
297 | |||
298 | ----------------------------------------------------------------------------- |
|
298 | ----------------------------------------------------------------------------- | |
299 | Head0 : HeaderBuilder |
|
299 | Head0 : HeaderBuilder | |
300 | GENERIC MAP ( |
|
300 | GENERIC MAP ( | |
301 | Data_sz => 32) |
|
301 | Data_sz => 32) | |
302 | PORT MAP ( |
|
302 | PORT MAP ( | |
303 | clkm => clk, |
|
303 | clkm => clk, | |
304 | rstn => rstn, |
|
304 | rstn => rstn, | |
305 | -- pong => SM_Pong, |
|
305 | -- pong => SM_Pong, | |
306 | Statu => SM_Param, |
|
306 | Statu => SM_Param, | |
307 | Matrix_Type => DMUX_WorkFreq, |
|
307 | Matrix_Type => DMUX_WorkFreq, | |
308 | Matrix_Write => SM_Wen, |
|
308 | Matrix_Write => SM_Wen, | |
309 | Valid => Head_Valid, |
|
309 | Valid => Head_Valid, | |
|
310 | ||||
310 |
|
|
311 | dataIN => FifoOUT_Data, | |
311 | emptyIN => FifoOUT_Empty, |
|
312 | emptyIN => FifoOUT_Empty, | |
312 |
RenOUT => Head_Read, |
|
313 | RenOUT => Head_Read, | |
|
314 | ||||
313 | dataOUT => Head_Data, |
|
315 | dataOUT => Head_Data, | |
314 | emptyOUT => Head_Empty, |
|
316 | emptyOUT => Head_Empty, | |
315 |
RenIN => DMA_Read, |
|
317 | RenIN => DMA_Read, | |
|
318 | ||||
316 | header => Head_Header, |
|
319 | header => Head_Header, | |
317 | header_val => Head_Val, |
|
320 | header_val => Head_Val, | |
318 | header_ack => DMA_ack ); |
|
321 | header_ack => DMA_ack ); | |
319 | ----------------------------------------------------------------------------- |
|
322 | ----------------------------------------------------------------------------- | |
320 | data_time(31 DOWNTO 0) <= coarse_time; |
|
323 | data_time(31 DOWNTO 0) <= coarse_time; | |
321 | data_time(47 DOWNTO 32) <= fine_time; |
|
324 | data_time(47 DOWNTO 32) <= fine_time; | |
322 |
|
325 | |||
323 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma |
|
326 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
324 | PORT MAP ( |
|
327 | PORT MAP ( | |
325 | HCLK => clk, |
|
328 | HCLK => clk, | |
326 | HRESETn => rstn, |
|
329 | HRESETn => rstn, | |
327 |
|
330 | |||
328 | data_time => data_time, |
|
331 | data_time => data_time, | |
329 |
|
332 | |||
330 | fifo_data => Head_Data, |
|
333 | fifo_data => Head_Data, | |
331 | fifo_empty => Head_Empty, |
|
334 | fifo_empty => Head_Empty, | |
332 | fifo_ren => DMA_Read, |
|
335 | fifo_ren => DMA_Read, | |
333 |
|
336 | |||
334 | header => Head_Header, |
|
337 | header => Head_Header, | |
335 | header_val => Head_Val, |
|
338 | header_val => Head_Val, | |
336 | header_ack => DMA_ack, |
|
339 | header_ack => DMA_ack, | |
337 |
|
340 | |||
338 | dma_addr => dma_addr, |
|
341 | dma_addr => dma_addr, | |
339 | dma_data => dma_data, |
|
342 | dma_data => dma_data, | |
340 | dma_valid => dma_valid, |
|
343 | dma_valid => dma_valid, | |
341 | dma_valid_burst => dma_valid_burst, |
|
344 | dma_valid_burst => dma_valid_burst, | |
342 | dma_ren => dma_ren, |
|
345 | dma_ren => dma_ren, | |
343 | dma_done => dma_done, |
|
346 | dma_done => dma_done, | |
344 |
|
347 | |||
345 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
348 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
346 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
349 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
347 | ready_matrix_f1 => ready_matrix_f1, |
|
350 | ready_matrix_f1 => ready_matrix_f1, | |
348 | ready_matrix_f2 => ready_matrix_f2, |
|
351 | ready_matrix_f2 => ready_matrix_f2, | |
349 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
352 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
350 | error_bad_component_error => error_bad_component_error, |
|
353 | error_bad_component_error => error_bad_component_error, | |
351 | debug_reg => debug_reg, |
|
354 | debug_reg => debug_reg, | |
352 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
355 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
353 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
356 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
354 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
357 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
355 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
358 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
356 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
359 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
357 | status_error_bad_component_error => status_error_bad_component_error, |
|
360 | status_error_bad_component_error => status_error_bad_component_error, | |
358 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
361 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
359 | config_active_interruption_onError => config_active_interruption_onError, |
|
362 | config_active_interruption_onError => config_active_interruption_onError, | |
360 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
363 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
361 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
364 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
362 | addr_matrix_f1 => addr_matrix_f1, |
|
365 | addr_matrix_f1 => addr_matrix_f1, | |
363 | addr_matrix_f2 => addr_matrix_f2, |
|
366 | addr_matrix_f2 => addr_matrix_f2, | |
364 |
|
367 | |||
365 | matrix_time_f0_0 => matrix_time_f0_0, |
|
368 | matrix_time_f0_0 => matrix_time_f0_0, | |
366 | matrix_time_f0_1 => matrix_time_f0_1, |
|
369 | matrix_time_f0_1 => matrix_time_f0_1, | |
367 | matrix_time_f1 => matrix_time_f1, |
|
370 | matrix_time_f1 => matrix_time_f1, | |
368 | matrix_time_f2 => matrix_time_f2 |
|
371 | matrix_time_f2 => matrix_time_f2 | |
369 | ); |
|
372 | ); | |
370 |
|
373 | |||
371 |
|
||||
372 |
|
||||
373 |
|
||||
374 | ----------------------------------------------------------------------------- |
|
|||
375 | --lpp_dma_ip_1: lpp_dma_ip |
|
|||
376 | -- GENERIC MAP ( |
|
|||
377 | -- tech => 0, |
|
|||
378 | -- hindex => hindex) |
|
|||
379 | -- PORT MAP ( |
|
|||
380 | -- HCLK => clk, |
|
|||
381 | -- HRESETn => rstn, |
|
|||
382 | -- AHB_Master_In => AHB_Master_In, |
|
|||
383 | -- AHB_Master_Out => AHB_Master_Out, |
|
|||
384 |
|
||||
385 | -- fifo_data => Head_Data, |
|
|||
386 | -- fifo_empty => Head_Empty, |
|
|||
387 | -- fifo_ren => DMA_Read, |
|
|||
388 |
|
||||
389 | -- header => Head_Header, |
|
|||
390 | -- header_val => Head_Val, |
|
|||
391 | -- header_ack => DMA_ack, |
|
|||
392 |
|
||||
393 | -- ready_matrix_f0_0 => ready_matrix_f0_0, |
|
|||
394 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
|||
395 | -- ready_matrix_f1 => ready_matrix_f1, |
|
|||
396 | -- ready_matrix_f2 => ready_matrix_f2, |
|
|||
397 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
|||
398 | -- error_bad_component_error => error_bad_component_error, |
|
|||
399 | -- debug_reg => debug_reg, |
|
|||
400 | -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
|||
401 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
|||
402 | -- status_ready_matrix_f1 => status_ready_matrix_f1, |
|
|||
403 | -- status_ready_matrix_f2 => status_ready_matrix_f2, |
|
|||
404 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
|||
405 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
|||
406 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
|||
407 | -- config_active_interruption_onError => config_active_interruption_onError, |
|
|||
408 | -- addr_matrix_f0_0 => addr_matrix_f0_0, |
|
|||
409 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
|||
410 | -- addr_matrix_f1 => addr_matrix_f1, |
|
|||
411 | -- addr_matrix_f2 => addr_matrix_f2); |
|
|||
412 | ------------------------------------------------------------------------------- |
|
|||
413 |
|
||||
414 | END Behavioral; |
|
374 | END Behavioral; |
@@ -1,383 +1,383 | |||||
1 |
|
1 | |||
2 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
5 | -- |
|
5 | -- | |
6 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
7 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
8 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
9 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
10 | -- |
|
10 | -- | |
11 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
15 | -- |
|
15 | -- | |
16 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
17 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
20 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
22 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
24 | -- 1.0 - initial version |
|
24 | -- 1.0 - initial version | |
25 | ------------------------------------------------------------------------------- |
|
25 | ------------------------------------------------------------------------------- | |
26 | LIBRARY ieee; |
|
26 | LIBRARY ieee; | |
27 | USE ieee.std_logic_1164.ALL; |
|
27 | USE ieee.std_logic_1164.ALL; | |
28 | USE ieee.numeric_std.ALL; |
|
28 | USE ieee.numeric_std.ALL; | |
29 | LIBRARY grlib; |
|
29 | LIBRARY grlib; | |
30 | USE grlib.amba.ALL; |
|
30 | USE grlib.amba.ALL; | |
31 | USE grlib.stdlib.ALL; |
|
31 | USE grlib.stdlib.ALL; | |
32 | USE grlib.devices.ALL; |
|
32 | USE grlib.devices.ALL; | |
33 | USE GRLIB.DMA2AHB_Package.ALL; |
|
33 | USE GRLIB.DMA2AHB_Package.ALL; | |
34 | LIBRARY lpp; |
|
34 | LIBRARY lpp; | |
35 | USE lpp.lpp_amba.ALL; |
|
35 | USE lpp.lpp_amba.ALL; | |
36 | USE lpp.apb_devices_list.ALL; |
|
36 | USE lpp.apb_devices_list.ALL; | |
37 | USE lpp.lpp_memory.ALL; |
|
37 | USE lpp.lpp_memory.ALL; | |
38 | USE lpp.lpp_dma_pkg.ALL; |
|
38 | USE lpp.lpp_dma_pkg.ALL; | |
39 | LIBRARY techmap; |
|
39 | LIBRARY techmap; | |
40 | USE techmap.gencomp.ALL; |
|
40 | USE techmap.gencomp.ALL; | |
41 |
|
41 | |||
42 |
|
42 | |||
43 | ENTITY lpp_lfr_ms_fsmdma IS |
|
43 | ENTITY lpp_lfr_ms_fsmdma IS | |
44 | PORT ( |
|
44 | PORT ( | |
45 | -- AMBA AHB system signals |
|
45 | -- AMBA AHB system signals | |
46 | HCLK : IN STD_ULOGIC; |
|
46 | HCLK : IN STD_ULOGIC; | |
47 | HRESETn : IN STD_ULOGIC; |
|
47 | HRESETn : IN STD_ULOGIC; | |
48 |
|
48 | |||
49 | --TIME |
|
49 | --TIME | |
50 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
50 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
51 |
|
51 | |||
52 | -- fifo interface |
|
52 | -- fifo interface | |
53 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
53 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
54 | fifo_empty : IN STD_LOGIC; |
|
54 | fifo_empty : IN STD_LOGIC; | |
55 | fifo_ren : OUT STD_LOGIC; |
|
55 | fifo_ren : OUT STD_LOGIC; | |
56 |
|
56 | |||
57 | -- header |
|
57 | -- header | |
58 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
59 | header_val : IN STD_LOGIC; |
|
59 | header_val : IN STD_LOGIC; | |
60 | header_ack : OUT STD_LOGIC; |
|
60 | header_ack : OUT STD_LOGIC; | |
61 |
|
61 | |||
62 | -- DMA |
|
62 | -- DMA | |
63 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
63 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
64 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
65 | dma_valid : OUT STD_LOGIC; |
|
65 | dma_valid : OUT STD_LOGIC; | |
66 | dma_valid_burst : OUT STD_LOGIC; |
|
66 | dma_valid_burst : OUT STD_LOGIC; | |
67 | dma_ren : IN STD_LOGIC; |
|
67 | dma_ren : IN STD_LOGIC; | |
68 | dma_done : IN STD_LOGIC; |
|
68 | dma_done : IN STD_LOGIC; | |
69 |
|
69 | |||
70 | -- Reg out |
|
70 | -- Reg out | |
71 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
71 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
72 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
72 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
73 | ready_matrix_f1 : OUT STD_LOGIC; |
|
73 | ready_matrix_f1 : OUT STD_LOGIC; | |
74 | ready_matrix_f2 : OUT STD_LOGIC; |
|
74 | ready_matrix_f2 : OUT STD_LOGIC; | |
75 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
75 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
76 | error_bad_component_error : OUT STD_LOGIC; |
|
76 | error_bad_component_error : OUT STD_LOGIC; | |
77 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 |
|
78 | |||
79 | -- Reg In |
|
79 | -- Reg In | |
80 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
80 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
81 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
81 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
82 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
82 | status_ready_matrix_f1 : IN STD_LOGIC; | |
83 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
83 | status_ready_matrix_f2 : IN STD_LOGIC; | |
84 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
84 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
85 | status_error_bad_component_error : IN STD_LOGIC; |
|
85 | status_error_bad_component_error : IN STD_LOGIC; | |
86 |
|
86 | |||
87 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
87 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
88 | config_active_interruption_onError : IN STD_LOGIC; |
|
88 | config_active_interruption_onError : IN STD_LOGIC; | |
89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
93 |
|
93 | |||
94 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
94 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
95 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
95 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
96 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
96 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
97 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
97 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
98 |
|
98 | |||
99 | ); |
|
99 | ); | |
100 | END; |
|
100 | END; | |
101 |
|
101 | |||
102 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS |
|
102 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS | |
103 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
104 | -- SIGNAL DMAIn : DMA_In_Type; |
|
104 | -- SIGNAL DMAIn : DMA_In_Type; | |
105 | -- SIGNAL header_dmai : DMA_In_Type; |
|
105 | -- SIGNAL header_dmai : DMA_In_Type; | |
106 | -- SIGNAL component_dmai : DMA_In_Type; |
|
106 | -- SIGNAL component_dmai : DMA_In_Type; | |
107 | -- SIGNAL DMAOut : DMA_OUt_Type; |
|
107 | -- SIGNAL DMAOut : DMA_OUt_Type; | |
108 | ----------------------------------------------------------------------------- |
|
108 | ----------------------------------------------------------------------------- | |
109 |
|
109 | |||
110 | ----------------------------------------------------------------------------- |
|
110 | ----------------------------------------------------------------------------- | |
111 | ----------------------------------------------------------------------------- |
|
111 | ----------------------------------------------------------------------------- | |
112 | TYPE state_DMAWriteBurst IS (IDLE, |
|
112 | TYPE state_DMAWriteBurst IS (IDLE, | |
113 | CHECK_COMPONENT_TYPE, |
|
113 | CHECK_COMPONENT_TYPE, | |
114 | WRITE_COARSE_TIME, |
|
114 | WRITE_COARSE_TIME, | |
115 | WRITE_FINE_TIME, |
|
115 | WRITE_FINE_TIME, | |
116 | TRASH_FIFO, |
|
116 | TRASH_FIFO, | |
117 | SEND_DATA, |
|
117 | SEND_DATA, | |
118 | WAIT_DATA_ACK, |
|
118 | WAIT_DATA_ACK, | |
119 | CHECK_LENGTH |
|
119 | CHECK_LENGTH | |
120 | ); |
|
120 | ); | |
121 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; |
|
121 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; | |
122 |
|
122 | |||
123 | -- SIGNAL nbSend : INTEGER; |
|
123 | -- SIGNAL nbSend : INTEGER; | |
124 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
124 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
125 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
125 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
126 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
126 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
127 | SIGNAL header_check_ok : STD_LOGIC; |
|
127 | SIGNAL header_check_ok : STD_LOGIC; | |
128 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
128 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
129 | SIGNAL send_matrix : STD_LOGIC; |
|
129 | SIGNAL send_matrix : STD_LOGIC; | |
130 | -- SIGNAL request : STD_LOGIC; |
|
130 | -- SIGNAL request : STD_LOGIC; | |
131 | -- SIGNAL remaining_data_request : INTEGER; |
|
131 | -- SIGNAL remaining_data_request : INTEGER; | |
132 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
133 | ----------------------------------------------------------------------------- |
|
133 | ----------------------------------------------------------------------------- | |
134 | ----------------------------------------------------------------------------- |
|
134 | ----------------------------------------------------------------------------- | |
135 | SIGNAL header_select : STD_LOGIC; |
|
135 | SIGNAL header_select : STD_LOGIC; | |
136 |
|
136 | |||
137 | SIGNAL header_send : STD_LOGIC; |
|
137 | SIGNAL header_send : STD_LOGIC; | |
138 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
138 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
139 | SIGNAL header_send_ok : STD_LOGIC; |
|
139 | SIGNAL header_send_ok : STD_LOGIC; | |
140 | SIGNAL header_send_ko : STD_LOGIC; |
|
140 | SIGNAL header_send_ko : STD_LOGIC; | |
141 |
|
141 | |||
142 | SIGNAL component_send : STD_LOGIC; |
|
142 | SIGNAL component_send : STD_LOGIC; | |
143 | SIGNAL component_send_ok : STD_LOGIC; |
|
143 | SIGNAL component_send_ok : STD_LOGIC; | |
144 | SIGNAL component_send_ko : STD_LOGIC; |
|
144 | SIGNAL component_send_ko : STD_LOGIC; | |
145 | ----------------------------------------------------------------------------- |
|
145 | ----------------------------------------------------------------------------- | |
146 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
146 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
147 | SIGNAL component_fifo_ren : STD_LOGIC; |
|
147 | SIGNAL component_fifo_ren : STD_LOGIC; | |
148 |
|
148 | |||
149 | ----------------------------------------------------------------------------- |
|
149 | ----------------------------------------------------------------------------- | |
150 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
150 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
151 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
151 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
152 |
|
152 | |||
153 | BEGIN |
|
153 | BEGIN | |
154 |
|
154 | |||
155 | debug_reg <= debug_reg_s; |
|
155 | debug_reg <= debug_reg_s; | |
156 |
|
156 | |||
157 |
|
157 | |||
158 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE |
|
158 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE | |
159 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
159 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
160 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE |
|
160 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE | |
161 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE |
|
161 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE | |
162 | '0'; |
|
162 | '0'; | |
163 |
|
163 | |||
164 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" |
|
164 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |
165 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE |
|
165 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE | |
166 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
166 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
167 | '0'; |
|
167 | '0'; | |
168 |
|
168 | |||
169 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE |
|
169 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE | |
170 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
170 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
171 | addr_matrix_f1 WHEN matrix_type = "10" ELSE |
|
171 | addr_matrix_f1 WHEN matrix_type = "10" ELSE | |
172 | addr_matrix_f2 WHEN matrix_type = "11" ELSE |
|
172 | addr_matrix_f2 WHEN matrix_type = "11" ELSE | |
173 | (OTHERS => '0'); |
|
173 | (OTHERS => '0'); | |
174 |
|
174 | |||
175 | ----------------------------------------------------------------------------- |
|
175 | ----------------------------------------------------------------------------- | |
176 | -- DMA control |
|
176 | -- DMA control | |
177 | ----------------------------------------------------------------------------- |
|
177 | ----------------------------------------------------------------------------- | |
178 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
178 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
179 | BEGIN -- PROCESS DMAWriteBurst_p |
|
179 | BEGIN -- PROCESS DMAWriteBurst_p | |
180 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
180 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
181 | matrix_type <= (OTHERS => '0'); |
|
181 | matrix_type <= (OTHERS => '0'); | |
182 | component_type <= (OTHERS => '0'); |
|
182 | component_type <= (OTHERS => '0'); | |
183 | state <= IDLE; |
|
183 | state <= IDLE; | |
184 | header_ack <= '0'; |
|
184 | header_ack <= '0'; | |
185 | ready_matrix_f0_0 <= '0'; |
|
185 | ready_matrix_f0_0 <= '0'; | |
186 | ready_matrix_f0_1 <= '0'; |
|
186 | ready_matrix_f0_1 <= '0'; | |
187 | ready_matrix_f1 <= '0'; |
|
187 | ready_matrix_f1 <= '0'; | |
188 | ready_matrix_f2 <= '0'; |
|
188 | ready_matrix_f2 <= '0'; | |
189 | error_anticipating_empty_fifo <= '0'; |
|
189 | error_anticipating_empty_fifo <= '0'; | |
190 | error_bad_component_error <= '0'; |
|
190 | error_bad_component_error <= '0'; | |
191 | component_type_pre <= "0000"; |
|
191 | component_type_pre <= "0000"; | |
192 | fifo_ren_trash <= '1'; |
|
192 | fifo_ren_trash <= '1'; | |
193 | component_send <= '0'; |
|
193 | component_send <= '0'; | |
194 | address <= (OTHERS => '0'); |
|
194 | address <= (OTHERS => '0'); | |
195 | header_select <= '0'; |
|
195 | header_select <= '0'; | |
196 | header_send <= '0'; |
|
196 | header_send <= '0'; | |
197 | header_data <= (OTHERS => '0'); |
|
197 | header_data <= (OTHERS => '0'); | |
198 | fine_time_reg <= (OTHERS => '0'); |
|
198 | fine_time_reg <= (OTHERS => '0'); | |
199 |
|
199 | |||
200 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); |
|
200 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); | |
201 |
|
201 | |||
202 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
202 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
203 |
|
203 | |||
204 | CASE state IS |
|
204 | CASE state IS | |
205 | WHEN IDLE => |
|
205 | WHEN IDLE => | |
206 | debug_reg_s(2 DOWNTO 0) <= "000"; |
|
206 | debug_reg_s(2 DOWNTO 0) <= "000"; | |
207 |
|
207 | |||
208 | matrix_type <= header(1 DOWNTO 0); |
|
208 | matrix_type <= header(1 DOWNTO 0); | |
209 | --component_type <= header(5 DOWNTO 2); |
|
209 | --component_type <= header(5 DOWNTO 2); | |
210 |
|
210 | |||
211 | ready_matrix_f0_0 <= '0'; |
|
211 | ready_matrix_f0_0 <= '0'; | |
212 | ready_matrix_f0_1 <= '0'; |
|
212 | ready_matrix_f0_1 <= '0'; | |
213 | ready_matrix_f1 <= '0'; |
|
213 | ready_matrix_f1 <= '0'; | |
214 | ready_matrix_f2 <= '0'; |
|
214 | ready_matrix_f2 <= '0'; | |
215 | error_bad_component_error <= '0'; |
|
215 | error_bad_component_error <= '0'; | |
216 | header_select <= '1'; |
|
216 | header_select <= '1'; | |
217 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
|
217 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
218 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); |
|
218 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); | |
219 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); |
|
219 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); | |
220 |
|
220 | |||
221 | matrix_type <= header(1 DOWNTO 0); |
|
221 | matrix_type <= header(1 DOWNTO 0); | |
222 | component_type <= header(5 DOWNTO 2); |
|
222 | component_type <= header(5 DOWNTO 2); | |
223 | component_type_pre <= component_type; |
|
223 | component_type_pre <= component_type; | |
224 | state <= CHECK_COMPONENT_TYPE; |
|
224 | state <= CHECK_COMPONENT_TYPE; | |
225 | END IF; |
|
225 | END IF; | |
226 |
|
226 | |||
227 | WHEN CHECK_COMPONENT_TYPE => |
|
227 | WHEN CHECK_COMPONENT_TYPE => | |
228 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
228 | debug_reg_s(2 DOWNTO 0) <= "001"; | |
229 |
|
229 | |||
230 | IF header_check_ok = '1' THEN |
|
230 | IF header_check_ok = '1' THEN | |
231 | header_ack <= '1'; |
|
231 | header_ack <= '1'; | |
232 | header_send <= '0'; |
|
232 | header_send <= '0'; | |
233 | -- |
|
233 | -- | |
234 | IF component_type = "0000" THEN |
|
234 | IF component_type = "0000" THEN | |
235 | address <= address_matrix; |
|
235 | address <= address_matrix; | |
236 | CASE matrix_type IS |
|
236 | CASE matrix_type IS | |
237 | WHEN "00" => matrix_time_f0_0 <= data_time; |
|
237 | WHEN "00" => matrix_time_f0_0 <= data_time; | |
238 | WHEN "01" => matrix_time_f0_1 <= data_time; |
|
238 | WHEN "01" => matrix_time_f0_1 <= data_time; | |
239 | WHEN "10" => matrix_time_f1 <= data_time; |
|
239 | WHEN "10" => matrix_time_f1 <= data_time; | |
240 | WHEN "11" => matrix_time_f2 <= data_time ; |
|
240 | WHEN "11" => matrix_time_f2 <= data_time ; | |
241 | WHEN OTHERS => NULL; |
|
241 | WHEN OTHERS => NULL; | |
242 | END CASE; |
|
242 | END CASE; | |
243 |
|
243 | |||
244 | header_data <= data_time(31 DOWNTO 0); |
|
244 | header_data <= data_time(31 DOWNTO 0); | |
245 | fine_time_reg <= data_time(47 DOWNTO 32); |
|
245 | fine_time_reg <= data_time(47 DOWNTO 32); | |
246 | --state <= WRITE_COARSE_TIME; |
|
246 | --state <= WRITE_COARSE_TIME; | |
247 | --header_send <= '1'; |
|
247 | --header_send <= '1'; | |
248 | state <= SEND_DATA; |
|
248 | state <= SEND_DATA; | |
249 | header_send <= '0'; |
|
249 | header_send <= '0'; | |
250 | component_send <= '1'; |
|
250 | component_send <= '1'; | |
251 | header_select <= '0'; |
|
251 | header_select <= '0'; | |
252 | ELSE |
|
252 | ELSE | |
253 | state <= SEND_DATA; |
|
253 | state <= SEND_DATA; | |
254 | END IF; |
|
254 | END IF; | |
255 | -- |
|
255 | -- | |
256 | ELSE |
|
256 | ELSE | |
257 | error_bad_component_error <= '1'; |
|
257 | error_bad_component_error <= '1'; | |
258 | component_type_pre <= "0000"; |
|
258 | component_type_pre <= "0000"; | |
259 | header_ack <= '1'; |
|
259 | header_ack <= '1'; | |
260 | state <= TRASH_FIFO; |
|
260 | state <= TRASH_FIFO; | |
261 | END IF; |
|
261 | END IF; | |
262 |
|
262 | |||
263 | WHEN WRITE_COARSE_TIME => |
|
263 | --WHEN WRITE_COARSE_TIME => | |
264 | debug_reg_s(2 DOWNTO 0) <= "010"; |
|
264 | -- debug_reg_s(2 DOWNTO 0) <= "010"; | |
265 |
|
265 | |||
266 | header_ack <= '0'; |
|
266 | -- header_ack <= '0'; | |
267 |
|
267 | |||
268 | IF dma_ren = '0' THEN |
|
268 | -- IF dma_ren = '0' THEN | |
269 | header_send <= '0'; |
|
269 | -- header_send <= '0'; | |
270 | ELSE |
|
270 | -- ELSE | |
271 | header_send <= header_send; |
|
271 | -- header_send <= header_send; | |
272 | END IF; |
|
272 | -- END IF; | |
273 |
|
273 | |||
274 |
|
274 | |||
275 | IF header_send_ko = '1' THEN |
|
275 | -- IF header_send_ko = '1' THEN | |
276 | header_send <= '0'; |
|
276 | -- header_send <= '0'; | |
277 | state <= TRASH_FIFO; |
|
277 | -- state <= TRASH_FIFO; | |
278 | error_anticipating_empty_fifo <= '1'; |
|
278 | -- error_anticipating_empty_fifo <= '1'; | |
279 | -- TODO : error sending header |
|
279 | -- -- TODO : error sending header | |
280 | ELSIF header_send_ok = '1' THEN |
|
280 | -- ELSIF header_send_ok = '1' THEN | |
281 | header_send <= '1'; |
|
281 | -- header_send <= '1'; | |
282 | header_select <= '1'; |
|
282 | -- header_select <= '1'; | |
283 | header_data(15 DOWNTO 0) <= fine_time_reg; |
|
283 | -- header_data(15 DOWNTO 0) <= fine_time_reg; | |
284 | header_data(31 DOWNTO 16) <= (OTHERS => '0'); |
|
284 | -- header_data(31 DOWNTO 16) <= (OTHERS => '0'); | |
285 | state <= WRITE_FINE_TIME; |
|
285 | -- state <= WRITE_FINE_TIME; | |
286 | address <= address + 4; |
|
286 | -- address <= address + 4; | |
287 | END IF; |
|
287 | -- END IF; | |
288 |
|
288 | |||
289 |
|
289 | |||
290 | WHEN WRITE_FINE_TIME => |
|
290 | --WHEN WRITE_FINE_TIME => | |
291 | debug_reg_s(2 DOWNTO 0) <= "011"; |
|
291 | -- debug_reg_s(2 DOWNTO 0) <= "011"; | |
292 |
|
292 | |||
293 | header_ack <= '0'; |
|
293 | -- header_ack <= '0'; | |
294 |
|
294 | |||
295 | IF dma_ren = '0' THEN |
|
295 | -- IF dma_ren = '0' THEN | |
296 | header_send <= '0'; |
|
296 | -- header_send <= '0'; | |
297 | ELSE |
|
297 | -- ELSE | |
298 | header_send <= header_send; |
|
298 | -- header_send <= header_send; | |
299 | END IF; |
|
299 | -- END IF; | |
300 |
|
300 | |||
301 | IF header_send_ko = '1' THEN |
|
301 | -- IF header_send_ko = '1' THEN | |
302 | header_send <= '0'; |
|
302 | -- header_send <= '0'; | |
303 | state <= TRASH_FIFO; |
|
303 | -- state <= TRASH_FIFO; | |
304 | error_anticipating_empty_fifo <= '1'; |
|
304 | -- error_anticipating_empty_fifo <= '1'; | |
305 | -- TODO : error sending header |
|
305 | -- -- TODO : error sending header | |
306 | ELSIF header_send_ok = '1' THEN |
|
306 | -- ELSIF header_send_ok = '1' THEN | |
307 | header_send <= '0'; |
|
307 | -- header_send <= '0'; | |
308 | header_select <= '0'; |
|
308 | -- header_select <= '0'; | |
309 | state <= SEND_DATA; |
|
309 | -- state <= SEND_DATA; | |
310 | address <= address + 4; |
|
310 | -- address <= address + 4; | |
311 | END IF; |
|
311 | -- END IF; | |
312 |
|
312 | |||
313 | WHEN TRASH_FIFO => |
|
313 | WHEN TRASH_FIFO => | |
314 | debug_reg_s(2 DOWNTO 0) <= "100"; |
|
314 | debug_reg_s(2 DOWNTO 0) <= "100"; | |
315 |
|
315 | |||
316 | header_ack <= '0'; |
|
316 | header_ack <= '0'; | |
317 | error_bad_component_error <= '0'; |
|
317 | error_bad_component_error <= '0'; | |
318 | error_anticipating_empty_fifo <= '0'; |
|
318 | error_anticipating_empty_fifo <= '0'; | |
319 | IF fifo_empty = '1' THEN |
|
319 | IF fifo_empty = '1' THEN | |
320 | state <= IDLE; |
|
320 | state <= IDLE; | |
321 | fifo_ren_trash <= '1'; |
|
321 | fifo_ren_trash <= '1'; | |
322 | ELSE |
|
322 | ELSE | |
323 | fifo_ren_trash <= '0'; |
|
323 | fifo_ren_trash <= '0'; | |
324 | END IF; |
|
324 | END IF; | |
325 |
|
325 | |||
326 | WHEN SEND_DATA => |
|
326 | WHEN SEND_DATA => | |
327 | header_ack <= '0'; |
|
327 | header_ack <= '0'; | |
328 | debug_reg_s(2 DOWNTO 0) <= "101"; |
|
328 | debug_reg_s(2 DOWNTO 0) <= "101"; | |
329 |
|
329 | |||
330 | IF fifo_empty = '1' THEN |
|
330 | IF fifo_empty = '1' THEN | |
331 | state <= IDLE; |
|
331 | state <= IDLE; | |
332 | IF component_type = "1110" THEN --"1110" -- JC |
|
332 | IF component_type = "1110" THEN --"1110" -- JC | |
333 | CASE matrix_type IS |
|
333 | CASE matrix_type IS | |
334 | WHEN "00" => ready_matrix_f0_0 <= '1'; |
|
334 | WHEN "00" => ready_matrix_f0_0 <= '1'; | |
335 | WHEN "01" => ready_matrix_f0_1 <= '1'; |
|
335 | WHEN "01" => ready_matrix_f0_1 <= '1'; | |
336 | WHEN "10" => ready_matrix_f1 <= '1'; |
|
336 | WHEN "10" => ready_matrix_f1 <= '1'; | |
337 | WHEN "11" => ready_matrix_f2 <= '1'; |
|
337 | WHEN "11" => ready_matrix_f2 <= '1'; | |
338 | WHEN OTHERS => NULL; |
|
338 | WHEN OTHERS => NULL; | |
339 | END CASE; |
|
339 | END CASE; | |
340 |
|
340 | |||
341 | END IF; |
|
341 | END IF; | |
342 | ELSE |
|
342 | ELSE | |
343 | component_send <= '1'; |
|
343 | component_send <= '1'; | |
344 | address <= address; |
|
344 | address <= address; | |
345 | state <= WAIT_DATA_ACK; |
|
345 | state <= WAIT_DATA_ACK; | |
346 | END IF; |
|
346 | END IF; | |
347 |
|
347 | |||
348 | WHEN WAIT_DATA_ACK => |
|
348 | WHEN WAIT_DATA_ACK => | |
349 | debug_reg_s(2 DOWNTO 0) <= "110"; |
|
349 | debug_reg_s(2 DOWNTO 0) <= "110"; | |
350 |
|
350 | |||
351 | component_send <= '0'; |
|
351 | component_send <= '0'; | |
352 | IF component_send_ok = '1' THEN |
|
352 | IF component_send_ok = '1' THEN | |
353 | address <= address + 64; |
|
353 | address <= address + 64; | |
354 | state <= SEND_DATA; |
|
354 | state <= SEND_DATA; | |
355 | ELSIF component_send_ko = '1' THEN |
|
355 | ELSIF component_send_ko = '1' THEN | |
356 | error_anticipating_empty_fifo <= '0'; |
|
356 | error_anticipating_empty_fifo <= '0'; | |
357 | state <= TRASH_FIFO; |
|
357 | state <= TRASH_FIFO; | |
358 | END IF; |
|
358 | END IF; | |
359 |
|
359 | |||
360 | WHEN CHECK_LENGTH => |
|
360 | WHEN CHECK_LENGTH => | |
361 | component_send <= '0'; |
|
361 | component_send <= '0'; | |
362 | debug_reg_s(2 DOWNTO 0) <= "111"; |
|
362 | debug_reg_s(2 DOWNTO 0) <= "111"; | |
363 | state <= IDLE; |
|
363 | state <= IDLE; | |
364 |
|
364 | |||
365 | WHEN OTHERS => NULL; |
|
365 | WHEN OTHERS => NULL; | |
366 | END CASE; |
|
366 | END CASE; | |
367 |
|
367 | |||
368 | END IF; |
|
368 | END IF; | |
369 | END PROCESS DMAWriteFSM_p; |
|
369 | END PROCESS DMAWriteFSM_p; | |
370 |
|
370 | |||
371 | dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; |
|
371 | dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; | |
372 | dma_valid <= header_send WHEN header_select = '1' ELSE '0'; |
|
372 | dma_valid <= header_send WHEN header_select = '1' ELSE '0'; | |
373 | dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; |
|
373 | dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; | |
374 | dma_addr <= address; |
|
374 | dma_addr <= address; | |
375 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren; |
|
375 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren; | |
376 |
|
376 | |||
377 | component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done; |
|
377 | component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done; | |
378 | component_send_ko <= '0'; |
|
378 | component_send_ko <= '0'; | |
379 |
|
379 | |||
380 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; |
|
380 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; | |
381 | header_send_ko <= '0'; |
|
381 | header_send_ko <= '0'; | |
382 |
|
382 | |||
383 | END Behavioral; |
|
383 | END Behavioral; |
@@ -1,287 +1,323 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
|
5 | USE grlib.amba.ALL; | |
6 |
|
6 | |||
7 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
8 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
9 | USE lpp.iir_filter.ALL; |
|
9 | USE lpp.iir_filter.ALL; | |
10 | USE lpp.FILTERcfg.ALL; |
|
10 | USE lpp.FILTERcfg.ALL; | |
11 | USE lpp.lpp_memory.ALL; |
|
11 | USE lpp.lpp_memory.ALL; | |
12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
14 |
|
14 | |||
15 | PACKAGE lpp_lfr_pkg IS |
|
15 | PACKAGE lpp_lfr_pkg IS | |
16 |
|
16 | |||
17 | COMPONENT lpp_lfr_ms |
|
17 | COMPONENT lpp_lfr_ms | |
18 | GENERIC ( |
|
18 | GENERIC ( | |
19 | Mem_use : INTEGER |
|
19 | Mem_use : INTEGER | |
20 | ); |
|
20 | ); | |
21 | PORT ( |
|
21 | PORT ( | |
22 | clk : IN STD_LOGIC; |
|
22 | clk : IN STD_LOGIC; | |
23 | rstn : IN STD_LOGIC; |
|
23 | rstn : IN STD_LOGIC; | |
24 |
|
24 | |||
25 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
25 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
26 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
26 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
27 |
|
27 | |||
28 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
28 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
29 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
29 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
30 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
30 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
31 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
31 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
32 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
32 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
33 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
33 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
34 |
|
34 | |||
35 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
35 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
36 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
36 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
37 | dma_valid : OUT STD_LOGIC; |
|
37 | dma_valid : OUT STD_LOGIC; | |
38 | dma_valid_burst : OUT STD_LOGIC; |
|
38 | dma_valid_burst : OUT STD_LOGIC; | |
39 | dma_ren : IN STD_LOGIC; |
|
39 | dma_ren : IN STD_LOGIC; | |
40 | dma_done : IN STD_LOGIC; |
|
40 | dma_done : IN STD_LOGIC; | |
41 |
|
41 | |||
42 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
42 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
43 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
43 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
44 | ready_matrix_f1 : OUT STD_LOGIC; |
|
44 | ready_matrix_f1 : OUT STD_LOGIC; | |
45 | ready_matrix_f2 : OUT STD_LOGIC; |
|
45 | ready_matrix_f2 : OUT STD_LOGIC; | |
46 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
46 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
47 | error_bad_component_error : OUT STD_LOGIC; |
|
47 | error_bad_component_error : OUT STD_LOGIC; | |
48 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
48 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
49 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
49 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
50 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
50 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
51 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
51 | status_ready_matrix_f1 : IN STD_LOGIC; | |
52 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
52 | status_ready_matrix_f2 : IN STD_LOGIC; | |
53 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
53 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
54 | status_error_bad_component_error : IN STD_LOGIC; |
|
54 | status_error_bad_component_error : IN STD_LOGIC; | |
55 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
55 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
56 | config_active_interruption_onError : IN STD_LOGIC; |
|
56 | config_active_interruption_onError : IN STD_LOGIC; | |
57 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
57 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
58 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
59 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
60 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
60 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
61 |
|
61 | |||
62 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
62 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
63 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
63 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
64 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
64 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
65 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
65 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
66 | END COMPONENT; |
|
66 | END COMPONENT; | |
67 |
|
67 | |||
68 | COMPONENT lpp_lfr_ms_fsmdma |
|
68 | COMPONENT lpp_lfr_ms_fsmdma | |
69 | PORT ( |
|
69 | PORT ( | |
70 | HCLK : IN STD_ULOGIC; |
|
70 | HCLK : IN STD_ULOGIC; | |
71 | HRESETn : IN STD_ULOGIC; |
|
71 | HRESETn : IN STD_ULOGIC; | |
72 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
72 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
73 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
74 | fifo_empty : IN STD_LOGIC; |
|
74 | fifo_empty : IN STD_LOGIC; | |
75 | fifo_ren : OUT STD_LOGIC; |
|
75 | fifo_ren : OUT STD_LOGIC; | |
76 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
76 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
77 | header_val : IN STD_LOGIC; |
|
77 | header_val : IN STD_LOGIC; | |
78 | header_ack : OUT STD_LOGIC; |
|
78 | header_ack : OUT STD_LOGIC; | |
79 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
81 | dma_valid : OUT STD_LOGIC; |
|
81 | dma_valid : OUT STD_LOGIC; | |
82 | dma_valid_burst : OUT STD_LOGIC; |
|
82 | dma_valid_burst : OUT STD_LOGIC; | |
83 | dma_ren : IN STD_LOGIC; |
|
83 | dma_ren : IN STD_LOGIC; | |
84 | dma_done : IN STD_LOGIC; |
|
84 | dma_done : IN STD_LOGIC; | |
85 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
85 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
86 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
86 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
87 | ready_matrix_f1 : OUT STD_LOGIC; |
|
87 | ready_matrix_f1 : OUT STD_LOGIC; | |
88 | ready_matrix_f2 : OUT STD_LOGIC; |
|
88 | ready_matrix_f2 : OUT STD_LOGIC; | |
89 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
89 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
90 | error_bad_component_error : OUT STD_LOGIC; |
|
90 | error_bad_component_error : OUT STD_LOGIC; | |
91 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
92 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
93 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
93 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
94 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
94 | status_ready_matrix_f1 : IN STD_LOGIC; | |
95 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
95 | status_ready_matrix_f2 : IN STD_LOGIC; | |
96 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
96 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
97 | status_error_bad_component_error : IN STD_LOGIC; |
|
97 | status_error_bad_component_error : IN STD_LOGIC; | |
98 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
98 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
99 | config_active_interruption_onError : IN STD_LOGIC; |
|
99 | config_active_interruption_onError : IN STD_LOGIC; | |
100 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
100 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
101 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
102 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
103 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
103 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
104 |
|
104 | |||
105 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
105 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
106 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
106 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
107 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
107 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
108 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
108 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
109 | ); |
|
109 | ); | |
110 | END COMPONENT; |
|
110 | END COMPONENT; | |
111 |
|
111 | |||
112 |
|
112 | |||
113 | COMPONENT lpp_lfr_filter |
|
113 | COMPONENT lpp_lfr_filter | |
114 | GENERIC ( |
|
114 | GENERIC ( | |
115 | Mem_use : INTEGER); |
|
115 | Mem_use : INTEGER); | |
116 | PORT ( |
|
116 | PORT ( | |
117 | sample : IN Samples(7 DOWNTO 0); |
|
117 | sample : IN Samples(7 DOWNTO 0); | |
118 | sample_val : IN STD_LOGIC; |
|
118 | sample_val : IN STD_LOGIC; | |
119 | clk : IN STD_LOGIC; |
|
119 | clk : IN STD_LOGIC; | |
120 | rstn : IN STD_LOGIC; |
|
120 | rstn : IN STD_LOGIC; | |
121 | data_shaping_SP0 : IN STD_LOGIC; |
|
121 | data_shaping_SP0 : IN STD_LOGIC; | |
122 | data_shaping_SP1 : IN STD_LOGIC; |
|
122 | data_shaping_SP1 : IN STD_LOGIC; | |
123 | data_shaping_R0 : IN STD_LOGIC; |
|
123 | data_shaping_R0 : IN STD_LOGIC; | |
124 | data_shaping_R1 : IN STD_LOGIC; |
|
124 | data_shaping_R1 : IN STD_LOGIC; | |
125 | sample_f0_val : OUT STD_LOGIC; |
|
125 | sample_f0_val : OUT STD_LOGIC; | |
126 | sample_f1_val : OUT STD_LOGIC; |
|
126 | sample_f1_val : OUT STD_LOGIC; | |
127 | sample_f2_val : OUT STD_LOGIC; |
|
127 | sample_f2_val : OUT STD_LOGIC; | |
128 | sample_f3_val : OUT STD_LOGIC; |
|
128 | sample_f3_val : OUT STD_LOGIC; | |
129 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
129 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
130 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
130 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
131 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
131 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
132 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
|
132 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); | |
133 | END COMPONENT; |
|
133 | END COMPONENT; | |
134 |
|
134 | |||
135 | COMPONENT lpp_lfr |
|
135 | COMPONENT lpp_lfr | |
136 | GENERIC ( |
|
136 | GENERIC ( | |
137 | Mem_use : INTEGER; |
|
137 | Mem_use : INTEGER; | |
138 | nb_data_by_buffer_size : INTEGER; |
|
138 | nb_data_by_buffer_size : INTEGER; | |
139 | nb_word_by_buffer_size : INTEGER; |
|
139 | nb_word_by_buffer_size : INTEGER; | |
140 | nb_snapshot_param_size : INTEGER; |
|
140 | nb_snapshot_param_size : INTEGER; | |
141 | delta_vector_size : INTEGER; |
|
141 | delta_vector_size : INTEGER; | |
142 | delta_vector_size_f0_2 : INTEGER; |
|
142 | delta_vector_size_f0_2 : INTEGER; | |
143 | pindex : INTEGER; |
|
143 | pindex : INTEGER; | |
144 | paddr : INTEGER; |
|
144 | paddr : INTEGER; | |
145 | pmask : INTEGER; |
|
145 | pmask : INTEGER; | |
146 | pirq_ms : INTEGER; |
|
146 | pirq_ms : INTEGER; | |
147 | pirq_wfp : INTEGER; |
|
147 | pirq_wfp : INTEGER; | |
148 | hindex : INTEGER; |
|
148 | hindex : INTEGER; | |
149 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
149 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
150 | ); |
|
150 | ); | |
151 | PORT ( |
|
151 | PORT ( | |
152 | clk : IN STD_LOGIC; |
|
152 | clk : IN STD_LOGIC; | |
153 | rstn : IN STD_LOGIC; |
|
153 | rstn : IN STD_LOGIC; | |
154 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
154 | sample_B : IN Samples14v(2 DOWNTO 0); | |
155 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
155 | sample_E : IN Samples14v(4 DOWNTO 0); | |
156 | sample_val : IN STD_LOGIC; |
|
156 | sample_val : IN STD_LOGIC; | |
157 | apbi : IN apb_slv_in_type; |
|
157 | apbi : IN apb_slv_in_type; | |
158 | apbo : OUT apb_slv_out_type; |
|
158 | apbo : OUT apb_slv_out_type; | |
159 | ahbi : IN AHB_Mst_In_Type; |
|
159 | ahbi : IN AHB_Mst_In_Type; | |
160 | ahbo : OUT AHB_Mst_Out_Type; |
|
160 | ahbo : OUT AHB_Mst_Out_Type; | |
161 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
161 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
162 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
162 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
163 | data_shaping_BW : OUT STD_LOGIC; |
|
163 | data_shaping_BW : OUT STD_LOGIC; | |
164 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
164 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
165 | ); |
|
165 | ); | |
166 | END COMPONENT; |
|
166 | END COMPONENT; | |
167 |
|
167 | |||
|
168 | ----------------------------------------------------------------------------- | |||
|
169 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) | |||
|
170 | ----------------------------------------------------------------------------- | |||
|
171 | COMPONENT lpp_lfr_WFP_nMS | |||
|
172 | GENERIC ( | |||
|
173 | Mem_use : INTEGER; | |||
|
174 | nb_data_by_buffer_size : INTEGER; | |||
|
175 | nb_word_by_buffer_size : INTEGER; | |||
|
176 | nb_snapshot_param_size : INTEGER; | |||
|
177 | delta_vector_size : INTEGER; | |||
|
178 | delta_vector_size_f0_2 : INTEGER; | |||
|
179 | pindex : INTEGER; | |||
|
180 | paddr : INTEGER; | |||
|
181 | pmask : INTEGER; | |||
|
182 | pirq_ms : INTEGER; | |||
|
183 | pirq_wfp : INTEGER; | |||
|
184 | hindex : INTEGER; | |||
|
185 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |||
|
186 | PORT ( | |||
|
187 | clk : IN STD_LOGIC; | |||
|
188 | rstn : IN STD_LOGIC; | |||
|
189 | sample_B : IN Samples14v(2 DOWNTO 0); | |||
|
190 | sample_E : IN Samples14v(4 DOWNTO 0); | |||
|
191 | sample_val : IN STD_LOGIC; | |||
|
192 | apbi : IN apb_slv_in_type; | |||
|
193 | apbo : OUT apb_slv_out_type; | |||
|
194 | ahbi : IN AHB_Mst_In_Type; | |||
|
195 | ahbo : OUT AHB_Mst_Out_Type; | |||
|
196 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
197 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
198 | data_shaping_BW : OUT STD_LOGIC; | |||
|
199 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
200 | END COMPONENT; | |||
|
201 | ----------------------------------------------------------------------------- | |||
|
202 | ||||
|
203 | ||||
168 |
|
|
204 | COMPONENT lpp_lfr_apbreg | |
169 | GENERIC ( |
|
205 | GENERIC ( | |
170 | nb_data_by_buffer_size : INTEGER; |
|
206 | nb_data_by_buffer_size : INTEGER; | |
171 | nb_word_by_buffer_size : INTEGER; |
|
207 | nb_word_by_buffer_size : INTEGER; | |
172 | nb_snapshot_param_size : INTEGER; |
|
208 | nb_snapshot_param_size : INTEGER; | |
173 | delta_vector_size : INTEGER; |
|
209 | delta_vector_size : INTEGER; | |
174 | delta_vector_size_f0_2 : INTEGER; |
|
210 | delta_vector_size_f0_2 : INTEGER; | |
175 | pindex : INTEGER; |
|
211 | pindex : INTEGER; | |
176 | paddr : INTEGER; |
|
212 | paddr : INTEGER; | |
177 | pmask : INTEGER; |
|
213 | pmask : INTEGER; | |
178 | pirq_ms : INTEGER; |
|
214 | pirq_ms : INTEGER; | |
179 | pirq_wfp : INTEGER; |
|
215 | pirq_wfp : INTEGER; | |
180 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
216 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
181 | PORT ( |
|
217 | PORT ( | |
182 | HCLK : IN STD_ULOGIC; |
|
218 | HCLK : IN STD_ULOGIC; | |
183 | HRESETn : IN STD_ULOGIC; |
|
219 | HRESETn : IN STD_ULOGIC; | |
184 | apbi : IN apb_slv_in_type; |
|
220 | apbi : IN apb_slv_in_type; | |
185 | apbo : OUT apb_slv_out_type; |
|
221 | apbo : OUT apb_slv_out_type; | |
186 | run_ms : OUT STD_LOGIC; |
|
222 | run_ms : OUT STD_LOGIC; | |
187 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
223 | ready_matrix_f0_0 : IN STD_LOGIC; | |
188 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
224 | ready_matrix_f0_1 : IN STD_LOGIC; | |
189 | ready_matrix_f1 : IN STD_LOGIC; |
|
225 | ready_matrix_f1 : IN STD_LOGIC; | |
190 | ready_matrix_f2 : IN STD_LOGIC; |
|
226 | ready_matrix_f2 : IN STD_LOGIC; | |
191 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
227 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
192 | error_bad_component_error : IN STD_LOGIC; |
|
228 | error_bad_component_error : IN STD_LOGIC; | |
193 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
229 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
194 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
230 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
195 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
231 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
196 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
232 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
197 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
233 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
198 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
234 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
199 | status_error_bad_component_error : OUT STD_LOGIC; |
|
235 | status_error_bad_component_error : OUT STD_LOGIC; | |
200 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
236 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
201 | config_active_interruption_onError : OUT STD_LOGIC; |
|
237 | config_active_interruption_onError : OUT STD_LOGIC; | |
202 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
238 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
203 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
239 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
204 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
240 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
205 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
241 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
206 |
|
242 | |||
207 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
243 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
208 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
244 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
209 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
245 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
210 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
246 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
211 |
|
247 | |||
212 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
248 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
213 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
249 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
214 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
250 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
215 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
251 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
216 | data_shaping_BW : OUT STD_LOGIC; |
|
252 | data_shaping_BW : OUT STD_LOGIC; | |
217 | data_shaping_SP0 : OUT STD_LOGIC; |
|
253 | data_shaping_SP0 : OUT STD_LOGIC; | |
218 | data_shaping_SP1 : OUT STD_LOGIC; |
|
254 | data_shaping_SP1 : OUT STD_LOGIC; | |
219 | data_shaping_R0 : OUT STD_LOGIC; |
|
255 | data_shaping_R0 : OUT STD_LOGIC; | |
220 | data_shaping_R1 : OUT STD_LOGIC; |
|
256 | data_shaping_R1 : OUT STD_LOGIC; | |
221 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
257 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
222 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
258 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
223 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
259 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
224 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
260 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
225 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
261 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
226 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
262 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
227 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
263 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
228 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
264 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
229 | enable_f0 : OUT STD_LOGIC; |
|
265 | enable_f0 : OUT STD_LOGIC; | |
230 | enable_f1 : OUT STD_LOGIC; |
|
266 | enable_f1 : OUT STD_LOGIC; | |
231 | enable_f2 : OUT STD_LOGIC; |
|
267 | enable_f2 : OUT STD_LOGIC; | |
232 | enable_f3 : OUT STD_LOGIC; |
|
268 | enable_f3 : OUT STD_LOGIC; | |
233 | burst_f0 : OUT STD_LOGIC; |
|
269 | burst_f0 : OUT STD_LOGIC; | |
234 | burst_f1 : OUT STD_LOGIC; |
|
270 | burst_f1 : OUT STD_LOGIC; | |
235 | burst_f2 : OUT STD_LOGIC; |
|
271 | burst_f2 : OUT STD_LOGIC; | |
236 | run : OUT STD_LOGIC; |
|
272 | run : OUT STD_LOGIC; | |
237 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
273 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
238 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
239 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
240 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
276 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
241 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
277 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
242 | --------------------------------------------------------------------------- |
|
278 | --------------------------------------------------------------------------- | |
243 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
279 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
244 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
280 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
245 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
281 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
246 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
282 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
247 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
283 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
248 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
284 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
249 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
285 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
250 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
286 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
251 | END COMPONENT; |
|
287 | END COMPONENT; | |
252 |
|
288 | |||
253 | COMPONENT lpp_top_ms |
|
289 | COMPONENT lpp_top_ms | |
254 | GENERIC ( |
|
290 | GENERIC ( | |
255 | Mem_use : INTEGER; |
|
291 | Mem_use : INTEGER; | |
256 | nb_burst_available_size : INTEGER; |
|
292 | nb_burst_available_size : INTEGER; | |
257 | nb_snapshot_param_size : INTEGER; |
|
293 | nb_snapshot_param_size : INTEGER; | |
258 | delta_snapshot_size : INTEGER; |
|
294 | delta_snapshot_size : INTEGER; | |
259 | delta_f2_f0_size : INTEGER; |
|
295 | delta_f2_f0_size : INTEGER; | |
260 | delta_f2_f1_size : INTEGER; |
|
296 | delta_f2_f1_size : INTEGER; | |
261 | pindex : INTEGER; |
|
297 | pindex : INTEGER; | |
262 | paddr : INTEGER; |
|
298 | paddr : INTEGER; | |
263 | pmask : INTEGER; |
|
299 | pmask : INTEGER; | |
264 | pirq_ms : INTEGER; |
|
300 | pirq_ms : INTEGER; | |
265 | pirq_wfp : INTEGER; |
|
301 | pirq_wfp : INTEGER; | |
266 | hindex_wfp : INTEGER; |
|
302 | hindex_wfp : INTEGER; | |
267 | hindex_ms : INTEGER); |
|
303 | hindex_ms : INTEGER); | |
268 | PORT ( |
|
304 | PORT ( | |
269 | clk : IN STD_LOGIC; |
|
305 | clk : IN STD_LOGIC; | |
270 | rstn : IN STD_LOGIC; |
|
306 | rstn : IN STD_LOGIC; | |
271 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
307 | sample_B : IN Samples14v(2 DOWNTO 0); | |
272 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
308 | sample_E : IN Samples14v(4 DOWNTO 0); | |
273 | sample_val : IN STD_LOGIC; |
|
309 | sample_val : IN STD_LOGIC; | |
274 | apbi : IN apb_slv_in_type; |
|
310 | apbi : IN apb_slv_in_type; | |
275 | apbo : OUT apb_slv_out_type; |
|
311 | apbo : OUT apb_slv_out_type; | |
276 | ahbi_ms : IN AHB_Mst_In_Type; |
|
312 | ahbi_ms : IN AHB_Mst_In_Type; | |
277 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
313 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
278 | data_shaping_BW : OUT STD_LOGIC; |
|
314 | data_shaping_BW : OUT STD_LOGIC; | |
279 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
315 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
280 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
316 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
281 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
317 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
282 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
318 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
283 |
|
319 | |||
284 | ); |
|
320 | ); | |
285 | END COMPONENT; |
|
321 | END COMPONENT; | |
286 |
|
322 | |||
287 | END lpp_lfr_pkg; |
|
323 | END lpp_lfr_pkg; |
@@ -1,7 +1,8 | |||||
1 | lpp_top_lfr_pkg.vhd |
|
1 | lpp_top_lfr_pkg.vhd | |
2 | lpp_lfr_pkg.vhd |
|
2 | lpp_lfr_pkg.vhd | |
3 | lpp_lfr_filter.vhd |
|
3 | lpp_lfr_filter.vhd | |
4 | lpp_lfr_apbreg.vhd |
|
4 | lpp_lfr_apbreg.vhd | |
5 | lpp_lfr_ms_fsmdma.vhd |
|
5 | lpp_lfr_ms_fsmdma.vhd | |
6 | lpp_lfr_ms.vhd |
|
6 | lpp_lfr_ms.vhd | |
|
7 | lpp_lfr_WFP_nMS.vhd | |||
7 | lpp_lfr.vhd |
|
8 | lpp_lfr.vhd |
1 | NO CONTENT: file was removed |
|
NO CONTENT: file was removed |
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