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temp : les inputs du WFP sont forcer pour permettre le test/debug.
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_waveform_pkg.ALL;
35 35
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 39 ENTITY lpp_waveform IS
40 40
41 41 GENERIC (
42 42 tech : INTEGER := inferred;
43 43 data_size : INTEGER := 96; --16*6
44 44 nb_data_by_buffer_size : INTEGER := 11;
45 45 nb_word_by_buffer_size : INTEGER := 11;
46 46 nb_snapshot_param_size : INTEGER := 11;
47 47 delta_vector_size : INTEGER := 20;
48 48 delta_vector_size_f0_2 : INTEGER := 3);
49 49
50 50 PORT (
51 51 clk : IN STD_LOGIC;
52 52 rstn : IN STD_LOGIC;
53 53
54 54 ---- AMBA AHB Master Interface
55 55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
56 56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
57 57
58 58 --config
59 59 reg_run : IN STD_LOGIC;
60 60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 66
67 67 enable_f0 : IN STD_LOGIC;
68 68 enable_f1 : IN STD_LOGIC;
69 69 enable_f2 : IN STD_LOGIC;
70 70 enable_f3 : IN STD_LOGIC;
71 71
72 72 burst_f0 : IN STD_LOGIC;
73 73 burst_f1 : IN STD_LOGIC;
74 74 burst_f2 : IN STD_LOGIC;
75 75
76 76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
78 78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
79 79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
81 81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 83 ---------------------------------------------------------------------------
84 84 -- INPUT
85 85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87 87
88 88 --f0
89 89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 data_f0_in_valid : IN STD_LOGIC;
91 91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 92 --f1
93 93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 data_f1_in_valid : IN STD_LOGIC;
95 95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 96 --f2
97 97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 data_f2_in_valid : IN STD_LOGIC;
99 99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 100 --f3
101 101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 data_f3_in_valid : IN STD_LOGIC;
103 103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104 104
105 105 ---------------------------------------------------------------------------
106 106 -- OUTPUT
107 107 --f0
108 108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 110 data_f0_data_out_valid : OUT STD_LOGIC;
111 111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 112 data_f0_data_out_ren : IN STD_LOGIC;
113 113 --f1
114 114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 116 data_f1_data_out_valid : OUT STD_LOGIC;
117 117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 118 data_f1_data_out_ren : IN STD_LOGIC;
119 119 --f2
120 120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 122 data_f2_data_out_valid : OUT STD_LOGIC;
123 123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 124 data_f2_data_out_ren : IN STD_LOGIC;
125 125 --f3
126 126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 data_f3_data_out_valid : OUT STD_LOGIC;
129 129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 130 data_f3_data_out_ren : IN STD_LOGIC;
131 131
132 132 --debug
133 133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 134 debug_f0_data_valid : OUT STD_LOGIC;
135 135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 136 debug_f1_data_valid : OUT STD_LOGIC;
137 137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 138 debug_f2_data_valid : OUT STD_LOGIC;
139 139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 140 debug_f3_data_valid : OUT STD_LOGIC
141 141 );
142 142
143 143 END lpp_waveform;
144 144
145 145 ARCHITECTURE beh OF lpp_waveform IS
146 146 SIGNAL start_snapshot_f0 : STD_LOGIC;
147 147 SIGNAL start_snapshot_f1 : STD_LOGIC;
148 148 SIGNAL start_snapshot_f2 : STD_LOGIC;
149 149
150 150 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
151 151 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
152 152 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
153 153 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
154 154
155 155 SIGNAL data_f0_out_valid : STD_LOGIC;
156 156 SIGNAL data_f1_out_valid : STD_LOGIC;
157 157 SIGNAL data_f2_out_valid : STD_LOGIC;
158 158 SIGNAL data_f3_out_valid : STD_LOGIC;
159 159 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
160 160 --
161 161 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 162 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 163 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 164 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 165 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 166 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 167 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 168 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 169 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 170 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 171 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 172 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 173 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 174 --
175 175 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 176 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 177 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 179 --
180 180 SIGNAL run : STD_LOGIC;
181 181 --
182 182 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
183 183 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
184 184 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
185 185 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
186 186 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
187 187 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 188 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 189
190 190 BEGIN -- beh
191 191
192 192 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
193 193 GENERIC MAP (
194 194 delta_vector_size => delta_vector_size,
195 195 delta_vector_size_f0_2 => delta_vector_size_f0_2
196 196 )
197 197 PORT MAP (
198 198 clk => clk,
199 199 rstn => rstn,
200 200 reg_run => reg_run,
201 201 reg_start_date => reg_start_date,
202 202 reg_delta_snapshot => reg_delta_snapshot,
203 203 reg_delta_f0 => reg_delta_f0,
204 204 reg_delta_f0_2 => reg_delta_f0_2,
205 205 reg_delta_f1 => reg_delta_f1,
206 206 reg_delta_f2 => reg_delta_f2,
207 207 coarse_time => coarse_time(30 DOWNTO 0),
208 208 data_f0_valid => data_f0_in_valid,
209 209 data_f2_valid => data_f2_in_valid,
210 210 start_snapshot_f0 => start_snapshot_f0,
211 211 start_snapshot_f1 => start_snapshot_f1,
212 212 start_snapshot_f2 => start_snapshot_f2,
213 213 wfp_on => run);
214 214
215 215 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
216 216 GENERIC MAP (
217 217 data_size => data_size,
218 218 nb_snapshot_param_size => nb_snapshot_param_size)
219 219 PORT MAP (
220 220 clk => clk,
221 221 rstn => rstn,
222 222 run => run,
223 223 enable => enable_f0,
224 224 burst_enable => burst_f0,
225 225 nb_snapshot_param => nb_snapshot_param,
226 226 start_snapshot => start_snapshot_f0,
227 227 data_in => data_f0_in,
228 228 data_in_valid => data_f0_in_valid,
229 229 data_out => data_f0_out,
230 230 data_out_valid => data_f0_out_valid);
231 231
232 232 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
233 233
234 234 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
235 235 GENERIC MAP (
236 236 data_size => data_size,
237 237 nb_snapshot_param_size => nb_snapshot_param_size+1)
238 238 PORT MAP (
239 239 clk => clk,
240 240 rstn => rstn,
241 241 run => run,
242 242 enable => enable_f1,
243 243 burst_enable => burst_f1,
244 244 nb_snapshot_param => nb_snapshot_param_more_one,
245 245 start_snapshot => start_snapshot_f1,
246 246 data_in => data_f1_in,
247 247 data_in_valid => data_f1_in_valid,
248 248 data_out => data_f1_out,
249 249 data_out_valid => data_f1_out_valid);
250 250
251 251 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
252 252 GENERIC MAP (
253 253 data_size => data_size,
254 254 nb_snapshot_param_size => nb_snapshot_param_size+1)
255 255 PORT MAP (
256 256 clk => clk,
257 257 rstn => rstn,
258 258 run => run,
259 259 enable => enable_f2,
260 260 burst_enable => burst_f2,
261 261 nb_snapshot_param => nb_snapshot_param_more_one,
262 262 start_snapshot => start_snapshot_f2,
263 263 data_in => data_f2_in,
264 264 data_in_valid => data_f2_in_valid,
265 265 data_out => data_f2_out,
266 266 data_out_valid => data_f2_out_valid);
267 267
268 268 lpp_waveform_burst_f3 : lpp_waveform_burst
269 269 GENERIC MAP (
270 270 data_size => data_size)
271 271 PORT MAP (
272 272 clk => clk,
273 273 rstn => rstn,
274 274 run => run,
275 275 enable => enable_f3,
276 276 data_in => data_f3_in,
277 277 data_in_valid => data_f3_in_valid,
278 278 data_out => data_f3_out,
279 279 data_out_valid => data_f3_out_valid);
280 280
281 281 -----------------------------------------------------------------------------
282 282 -- DEBUG
283 283 debug_f0_data_valid <= data_f0_out_valid;
284 284 debug_f0_data <= data_f0_out;
285 285 debug_f1_data_valid <= data_f1_out_valid;
286 286 debug_f1_data <= data_f1_out;
287 287 debug_f2_data_valid <= data_f2_out_valid;
288 288 debug_f2_data <= data_f2_out;
289 289 debug_f3_data_valid <= data_f3_out_valid;
290 290 debug_f3_data <= data_f3_out;
291 291 -----------------------------------------------------------------------------
292 292
293 293 PROCESS (clk, rstn)
294 294 BEGIN -- PROCESS
295 295 IF rstn = '0' THEN -- asynchronous reset (active low)
296 296 time_reg1 <= (OTHERS => '0');
297 297 time_reg2 <= (OTHERS => '0');
298 298 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
299 299 time_reg1 <= fine_time & coarse_time;
300 300 time_reg2 <= time_reg1;
301 301 END IF;
302 302 END PROCESS;
303 303
304 304 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
305 305 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
306 306 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
307 307 PORT MAP (
308 308 HCLK => clk,
309 309 HRESETn => rstn,
310 310 run => run,
311 311 valid_in => valid_in(I),
312 312 ack_in => valid_ack(I),
313 313 time_in => time_reg2, -- Todo
314 314 valid_out => valid_out(I),
315 315 time_out => time_out(I), -- Todo
316 316 error => status_new_err(I));
317 317 END GENERATE all_input_valid;
318 318
319 319 all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE
320 320 data_out(0,I) <= data_f0_out(I);
321 321 data_out(1,I) <= data_f1_out(I);
322 322 data_out(2,I) <= data_f2_out(I);
323 323 data_out(3,I) <= data_f3_out(I);
324 324 END GENERATE all_bit_of_data_out;
325 325
326 326 -----------------------------------------------------------------------------
327 327 -- TODO : debug
328 328 -----------------------------------------------------------------------------
329 329 --all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
330 330 -- all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
331 331 -- time_out_2(J,I) <= time_out(J)(I);
332 332 -- END GENERATE all_sample_of_time_out;
333 333 --END GENERATE all_bit_of_time_out;
334
334 335 time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
335 336 time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
336 337 time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
337 338 time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
338 339
339 340 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
340 341 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
341 342 time_out_2(J,I) <= time_out_debug(J)(I);
342 343 END GENERATE all_sample_of_time_out;
343 344 END GENERATE all_bit_of_time_out;
344 345
345 346 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
346 347 GENERIC MAP (tech => tech,
347 348 nb_data_by_buffer_size =>nb_data_by_buffer_size)
348 349 PORT MAP (
349 350 clk => clk,
350 351 rstn => rstn,
351 352 run => run,
352 353 nb_data_by_buffer => nb_data_by_buffer,
353 354 data_in_valid => valid_out,
354 355 data_in_ack => valid_ack,
355 356 data_in => data_out,
356 357 time_in => time_out_2,
357 358
358 359 data_out => wdata,
359 360 data_out_wen => data_wen,
360 361 full_almost => full_almost,
361 362 full => full);
362 363
363 364 lpp_waveform_fifo_1 : lpp_waveform_fifo
364 365 GENERIC MAP (tech => tech)
365 366 PORT MAP (
366 367 clk => clk,
367 368 rstn => rstn,
368 369 run => run,
369 370
370 371 empty => empty,
371 372 empty_almost => empty_almost,
372 373
373 374 data_ren => data_ren,
374 375 rdata => rdata,
375 376
376 377
377 378 full_almost => full_almost,
378 379 full => full,
379 380 data_wen => data_wen,
380 381 wdata => wdata);
381 382
382 383 data_f0_data_out <= rdata;
383 384 data_f1_data_out <= rdata;
384 385 data_f2_data_out <= rdata;
385 386 data_f3_data_out <= rdata;
386
387 --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency
388 -- GENERIC MAP (
389 -- tech => tech)
390 -- PORT MAP (
391 -- clk => clk,
392 -- rstn => rstn,
393 -- run => run,
394
395 -- empty_almost => empty_almost,
396 -- empty => empty,
397 -- data_ren => data_ren,
398
399 -- rdata_0 => data_f0_data_out,
400 -- rdata_1 => data_f1_data_out,
401 -- rdata_2 => data_f2_data_out,
402 -- rdata_3 => data_f3_data_out,
403
404 -- full_almost => full_almost,
405 -- full => full,
406 -- data_wen => data_wen,
407 -- wdata => wdata);
408
409
410
411 387
412 388 data_ren <= data_f3_data_out_ren &
413 389 data_f2_data_out_ren &
414 390 data_f1_data_out_ren &
415 391 data_f0_data_out_ren;
416 392
417 -----------------------------------------------------------------------------
418 -- TODO : set the alterance : time, data, data, .....
419 -----------------------------------------------------------------------------
420 393 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
421 394 GENERIC MAP (
422 395 nb_data_by_buffer_size => nb_word_by_buffer_size)
423 396 PORT MAP (
424 397 clk => clk,
425 398 rstn => rstn,
426 399 run => run,
427 400
428 401 -------------------------------------------------------------------------
429 402 -- CONFIG
430 403 -------------------------------------------------------------------------
431 404 nb_data_by_buffer => nb_word_by_buffer,
432 405
433 406 addr_data_f0 => addr_data_f0,
434 407 addr_data_f1 => addr_data_f1,
435 408 addr_data_f2 => addr_data_f2,
436 409 addr_data_f3 => addr_data_f3,
437 410 -------------------------------------------------------------------------
438 411 -- CTRL
439 412 -------------------------------------------------------------------------
440 413 -- IN
441 414 empty => empty,
442 415 empty_almost => empty_almost,
443 416 data_ren => data_ren,
444 417
445 418 -------------------------------------------------------------------------
446 419 -- STATUS
447 420 -------------------------------------------------------------------------
448 421 status_full => status_full,
449 422 status_full_ack => status_full_ack,
450 423 status_full_err => status_full_err,
451 424
452 425 -------------------------------------------------------------------------
453 426 -- ADDR DATA OUT
454 427 -------------------------------------------------------------------------
455 428 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
456 429 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
457 430 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
458 431 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
459 432
460 433 data_f0_data_out_valid => data_f0_data_out_valid,
461 434 data_f1_data_out_valid => data_f1_data_out_valid,
462 435 data_f2_data_out_valid => data_f2_data_out_valid,
463 436 data_f3_data_out_valid => data_f3_data_out_valid,
464 437
465 438 data_f0_addr_out => data_f0_addr_out,
466 439 data_f1_addr_out => data_f1_addr_out,
467 440 data_f2_addr_out => data_f2_addr_out,
468 441 data_f3_addr_out => data_f3_addr_out
469 442 );
470 443
471 444 END beh;
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