@@ -1,471 +1,444 | |||||
1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
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19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
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21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ------------------------------------------------------------------------------- |
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22 | ------------------------------------------------------------------------------- | |
23 | LIBRARY IEEE; |
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23 | LIBRARY IEEE; | |
24 | USE IEEE.STD_LOGIC_1164.ALL; |
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24 | USE IEEE.STD_LOGIC_1164.ALL; | |
25 | USE ieee.numeric_std.ALL; |
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25 | USE ieee.numeric_std.ALL; | |
26 |
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26 | |||
27 | LIBRARY grlib; |
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27 | LIBRARY grlib; | |
28 | USE grlib.amba.ALL; |
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28 | USE grlib.amba.ALL; | |
29 | USE grlib.stdlib.ALL; |
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29 | USE grlib.stdlib.ALL; | |
30 | USE grlib.devices.ALL; |
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30 | USE grlib.devices.ALL; | |
31 | USE GRLIB.DMA2AHB_Package.ALL; |
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31 | USE GRLIB.DMA2AHB_Package.ALL; | |
32 |
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32 | |||
33 | LIBRARY lpp; |
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33 | LIBRARY lpp; | |
34 | USE lpp.lpp_waveform_pkg.ALL; |
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34 | USE lpp.lpp_waveform_pkg.ALL; | |
35 |
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35 | |||
36 | LIBRARY techmap; |
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36 | LIBRARY techmap; | |
37 | USE techmap.gencomp.ALL; |
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37 | USE techmap.gencomp.ALL; | |
38 |
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38 | |||
39 | ENTITY lpp_waveform IS |
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39 | ENTITY lpp_waveform IS | |
40 |
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40 | |||
41 | GENERIC ( |
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41 | GENERIC ( | |
42 | tech : INTEGER := inferred; |
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42 | tech : INTEGER := inferred; | |
43 | data_size : INTEGER := 96; --16*6 |
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43 | data_size : INTEGER := 96; --16*6 | |
44 | nb_data_by_buffer_size : INTEGER := 11; |
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44 | nb_data_by_buffer_size : INTEGER := 11; | |
45 | nb_word_by_buffer_size : INTEGER := 11; |
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45 | nb_word_by_buffer_size : INTEGER := 11; | |
46 | nb_snapshot_param_size : INTEGER := 11; |
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46 | nb_snapshot_param_size : INTEGER := 11; | |
47 | delta_vector_size : INTEGER := 20; |
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47 | delta_vector_size : INTEGER := 20; | |
48 | delta_vector_size_f0_2 : INTEGER := 3); |
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48 | delta_vector_size_f0_2 : INTEGER := 3); | |
49 |
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49 | |||
50 | PORT ( |
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50 | PORT ( | |
51 | clk : IN STD_LOGIC; |
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51 | clk : IN STD_LOGIC; | |
52 | rstn : IN STD_LOGIC; |
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52 | rstn : IN STD_LOGIC; | |
53 |
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53 | |||
54 | ---- AMBA AHB Master Interface |
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54 | ---- AMBA AHB Master Interface | |
55 | --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO |
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55 | --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO | |
56 | --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO |
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56 | --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO | |
57 |
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57 | |||
58 | --config |
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58 | --config | |
59 | reg_run : IN STD_LOGIC; |
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59 | reg_run : IN STD_LOGIC; | |
60 | reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
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60 | reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
61 | reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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61 | reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
62 | reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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62 | reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
63 | reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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63 | reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
64 | reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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64 | reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
65 | reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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65 | reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
66 |
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66 | |||
67 | enable_f0 : IN STD_LOGIC; |
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67 | enable_f0 : IN STD_LOGIC; | |
68 | enable_f1 : IN STD_LOGIC; |
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68 | enable_f1 : IN STD_LOGIC; | |
69 | enable_f2 : IN STD_LOGIC; |
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69 | enable_f2 : IN STD_LOGIC; | |
70 | enable_f3 : IN STD_LOGIC; |
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70 | enable_f3 : IN STD_LOGIC; | |
71 |
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71 | |||
72 | burst_f0 : IN STD_LOGIC; |
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72 | burst_f0 : IN STD_LOGIC; | |
73 | burst_f1 : IN STD_LOGIC; |
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73 | burst_f1 : IN STD_LOGIC; | |
74 | burst_f2 : IN STD_LOGIC; |
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74 | burst_f2 : IN STD_LOGIC; | |
75 |
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75 | |||
76 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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76 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
77 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
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77 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
78 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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78 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
79 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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79 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
80 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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80 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
81 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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81 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
82 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma |
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82 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |
83 | --------------------------------------------------------------------------- |
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83 | --------------------------------------------------------------------------- | |
84 | -- INPUT |
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84 | -- INPUT | |
85 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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85 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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86 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
87 |
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87 | |||
88 | --f0 |
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88 | --f0 | |
89 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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89 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | data_f0_in_valid : IN STD_LOGIC; |
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90 | data_f0_in_valid : IN STD_LOGIC; | |
91 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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91 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
92 | --f1 |
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92 | --f1 | |
93 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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93 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
94 | data_f1_in_valid : IN STD_LOGIC; |
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94 | data_f1_in_valid : IN STD_LOGIC; | |
95 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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95 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
96 | --f2 |
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96 | --f2 | |
97 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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97 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | data_f2_in_valid : IN STD_LOGIC; |
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98 | data_f2_in_valid : IN STD_LOGIC; | |
99 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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99 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
100 | --f3 |
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100 | --f3 | |
101 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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101 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | data_f3_in_valid : IN STD_LOGIC; |
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102 | data_f3_in_valid : IN STD_LOGIC; | |
103 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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103 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
104 |
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104 | |||
105 | --------------------------------------------------------------------------- |
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105 | --------------------------------------------------------------------------- | |
106 | -- OUTPUT |
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106 | -- OUTPUT | |
107 | --f0 |
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107 | --f0 | |
108 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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108 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
109 | data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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109 | data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
110 | data_f0_data_out_valid : OUT STD_LOGIC; |
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110 | data_f0_data_out_valid : OUT STD_LOGIC; | |
111 | data_f0_data_out_valid_burst : OUT STD_LOGIC; |
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111 | data_f0_data_out_valid_burst : OUT STD_LOGIC; | |
112 | data_f0_data_out_ren : IN STD_LOGIC; |
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112 | data_f0_data_out_ren : IN STD_LOGIC; | |
113 | --f1 |
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113 | --f1 | |
114 | data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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114 | data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
115 | data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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115 | data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
116 | data_f1_data_out_valid : OUT STD_LOGIC; |
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116 | data_f1_data_out_valid : OUT STD_LOGIC; | |
117 | data_f1_data_out_valid_burst : OUT STD_LOGIC; |
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117 | data_f1_data_out_valid_burst : OUT STD_LOGIC; | |
118 | data_f1_data_out_ren : IN STD_LOGIC; |
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118 | data_f1_data_out_ren : IN STD_LOGIC; | |
119 | --f2 |
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119 | --f2 | |
120 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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120 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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121 | data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
122 | data_f2_data_out_valid : OUT STD_LOGIC; |
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122 | data_f2_data_out_valid : OUT STD_LOGIC; | |
123 | data_f2_data_out_valid_burst : OUT STD_LOGIC; |
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123 | data_f2_data_out_valid_burst : OUT STD_LOGIC; | |
124 | data_f2_data_out_ren : IN STD_LOGIC; |
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124 | data_f2_data_out_ren : IN STD_LOGIC; | |
125 | --f3 |
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125 | --f3 | |
126 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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126 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
127 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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127 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
128 | data_f3_data_out_valid : OUT STD_LOGIC; |
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128 | data_f3_data_out_valid : OUT STD_LOGIC; | |
129 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
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129 | data_f3_data_out_valid_burst : OUT STD_LOGIC; | |
130 | data_f3_data_out_ren : IN STD_LOGIC; |
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130 | data_f3_data_out_ren : IN STD_LOGIC; | |
131 |
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131 | |||
132 | --debug |
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132 | --debug | |
133 | debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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133 | debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
134 | debug_f0_data_valid : OUT STD_LOGIC; |
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134 | debug_f0_data_valid : OUT STD_LOGIC; | |
135 | debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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135 | debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
136 | debug_f1_data_valid : OUT STD_LOGIC; |
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136 | debug_f1_data_valid : OUT STD_LOGIC; | |
137 | debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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137 | debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
138 | debug_f2_data_valid : OUT STD_LOGIC; |
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138 | debug_f2_data_valid : OUT STD_LOGIC; | |
139 | debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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139 | debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
140 | debug_f3_data_valid : OUT STD_LOGIC |
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140 | debug_f3_data_valid : OUT STD_LOGIC | |
141 | ); |
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141 | ); | |
142 |
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142 | |||
143 | END lpp_waveform; |
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143 | END lpp_waveform; | |
144 |
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144 | |||
145 | ARCHITECTURE beh OF lpp_waveform IS |
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145 | ARCHITECTURE beh OF lpp_waveform IS | |
146 | SIGNAL start_snapshot_f0 : STD_LOGIC; |
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146 | SIGNAL start_snapshot_f0 : STD_LOGIC; | |
147 | SIGNAL start_snapshot_f1 : STD_LOGIC; |
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147 | SIGNAL start_snapshot_f1 : STD_LOGIC; | |
148 | SIGNAL start_snapshot_f2 : STD_LOGIC; |
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148 | SIGNAL start_snapshot_f2 : STD_LOGIC; | |
149 |
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149 | |||
150 | SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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150 | SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
151 | SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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151 | SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
152 | SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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152 | SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
153 | SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
153 | SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
154 |
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154 | |||
155 | SIGNAL data_f0_out_valid : STD_LOGIC; |
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155 | SIGNAL data_f0_out_valid : STD_LOGIC; | |
156 | SIGNAL data_f1_out_valid : STD_LOGIC; |
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156 | SIGNAL data_f1_out_valid : STD_LOGIC; | |
157 | SIGNAL data_f2_out_valid : STD_LOGIC; |
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157 | SIGNAL data_f2_out_valid : STD_LOGIC; | |
158 | SIGNAL data_f3_out_valid : STD_LOGIC; |
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158 | SIGNAL data_f3_out_valid : STD_LOGIC; | |
159 | SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); |
|
159 | SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); | |
160 | -- |
|
160 | -- | |
161 | SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
161 | SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
162 | SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
162 | SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
163 | SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
163 | SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
164 | SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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164 | SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
165 | SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
165 | SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
166 | SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
166 | SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
167 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
167 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
168 | SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
168 | SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
169 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
169 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
170 | SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
170 | SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
171 | SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
171 | SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
172 | SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
172 | SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
173 | SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
173 | SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
174 | -- |
|
174 | -- | |
175 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
175 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
176 | SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
176 | SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
177 | SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
177 | SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
178 | SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
178 | SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
179 | -- |
|
179 | -- | |
180 | SIGNAL run : STD_LOGIC; |
|
180 | SIGNAL run : STD_LOGIC; | |
181 | -- |
|
181 | -- | |
182 | TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
182 | TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); | |
183 | SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); |
|
183 | SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); | |
184 | SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); |
|
184 | SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); | |
185 | SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); |
|
185 | SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); | |
186 | SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug |
|
186 | SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug | |
187 | SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
187 | SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
188 | SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
188 | SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
189 |
|
189 | |||
190 | BEGIN -- beh |
|
190 | BEGIN -- beh | |
191 |
|
191 | |||
192 | lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler |
|
192 | lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler | |
193 | GENERIC MAP ( |
|
193 | GENERIC MAP ( | |
194 | delta_vector_size => delta_vector_size, |
|
194 | delta_vector_size => delta_vector_size, | |
195 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
195 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
196 | ) |
|
196 | ) | |
197 | PORT MAP ( |
|
197 | PORT MAP ( | |
198 | clk => clk, |
|
198 | clk => clk, | |
199 | rstn => rstn, |
|
199 | rstn => rstn, | |
200 | reg_run => reg_run, |
|
200 | reg_run => reg_run, | |
201 | reg_start_date => reg_start_date, |
|
201 | reg_start_date => reg_start_date, | |
202 | reg_delta_snapshot => reg_delta_snapshot, |
|
202 | reg_delta_snapshot => reg_delta_snapshot, | |
203 | reg_delta_f0 => reg_delta_f0, |
|
203 | reg_delta_f0 => reg_delta_f0, | |
204 | reg_delta_f0_2 => reg_delta_f0_2, |
|
204 | reg_delta_f0_2 => reg_delta_f0_2, | |
205 | reg_delta_f1 => reg_delta_f1, |
|
205 | reg_delta_f1 => reg_delta_f1, | |
206 | reg_delta_f2 => reg_delta_f2, |
|
206 | reg_delta_f2 => reg_delta_f2, | |
207 | coarse_time => coarse_time(30 DOWNTO 0), |
|
207 | coarse_time => coarse_time(30 DOWNTO 0), | |
208 | data_f0_valid => data_f0_in_valid, |
|
208 | data_f0_valid => data_f0_in_valid, | |
209 | data_f2_valid => data_f2_in_valid, |
|
209 | data_f2_valid => data_f2_in_valid, | |
210 | start_snapshot_f0 => start_snapshot_f0, |
|
210 | start_snapshot_f0 => start_snapshot_f0, | |
211 | start_snapshot_f1 => start_snapshot_f1, |
|
211 | start_snapshot_f1 => start_snapshot_f1, | |
212 | start_snapshot_f2 => start_snapshot_f2, |
|
212 | start_snapshot_f2 => start_snapshot_f2, | |
213 | wfp_on => run); |
|
213 | wfp_on => run); | |
214 |
|
214 | |||
215 | lpp_waveform_snapshot_f0 : lpp_waveform_snapshot |
|
215 | lpp_waveform_snapshot_f0 : lpp_waveform_snapshot | |
216 | GENERIC MAP ( |
|
216 | GENERIC MAP ( | |
217 | data_size => data_size, |
|
217 | data_size => data_size, | |
218 | nb_snapshot_param_size => nb_snapshot_param_size) |
|
218 | nb_snapshot_param_size => nb_snapshot_param_size) | |
219 | PORT MAP ( |
|
219 | PORT MAP ( | |
220 | clk => clk, |
|
220 | clk => clk, | |
221 | rstn => rstn, |
|
221 | rstn => rstn, | |
222 | run => run, |
|
222 | run => run, | |
223 | enable => enable_f0, |
|
223 | enable => enable_f0, | |
224 | burst_enable => burst_f0, |
|
224 | burst_enable => burst_f0, | |
225 | nb_snapshot_param => nb_snapshot_param, |
|
225 | nb_snapshot_param => nb_snapshot_param, | |
226 | start_snapshot => start_snapshot_f0, |
|
226 | start_snapshot => start_snapshot_f0, | |
227 | data_in => data_f0_in, |
|
227 | data_in => data_f0_in, | |
228 | data_in_valid => data_f0_in_valid, |
|
228 | data_in_valid => data_f0_in_valid, | |
229 | data_out => data_f0_out, |
|
229 | data_out => data_f0_out, | |
230 | data_out_valid => data_f0_out_valid); |
|
230 | data_out_valid => data_f0_out_valid); | |
231 |
|
231 | |||
232 | nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1; |
|
232 | nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1; | |
233 |
|
233 | |||
234 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot |
|
234 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot | |
235 | GENERIC MAP ( |
|
235 | GENERIC MAP ( | |
236 | data_size => data_size, |
|
236 | data_size => data_size, | |
237 | nb_snapshot_param_size => nb_snapshot_param_size+1) |
|
237 | nb_snapshot_param_size => nb_snapshot_param_size+1) | |
238 | PORT MAP ( |
|
238 | PORT MAP ( | |
239 | clk => clk, |
|
239 | clk => clk, | |
240 | rstn => rstn, |
|
240 | rstn => rstn, | |
241 | run => run, |
|
241 | run => run, | |
242 | enable => enable_f1, |
|
242 | enable => enable_f1, | |
243 | burst_enable => burst_f1, |
|
243 | burst_enable => burst_f1, | |
244 | nb_snapshot_param => nb_snapshot_param_more_one, |
|
244 | nb_snapshot_param => nb_snapshot_param_more_one, | |
245 | start_snapshot => start_snapshot_f1, |
|
245 | start_snapshot => start_snapshot_f1, | |
246 | data_in => data_f1_in, |
|
246 | data_in => data_f1_in, | |
247 | data_in_valid => data_f1_in_valid, |
|
247 | data_in_valid => data_f1_in_valid, | |
248 | data_out => data_f1_out, |
|
248 | data_out => data_f1_out, | |
249 | data_out_valid => data_f1_out_valid); |
|
249 | data_out_valid => data_f1_out_valid); | |
250 |
|
250 | |||
251 | lpp_waveform_snapshot_f2 : lpp_waveform_snapshot |
|
251 | lpp_waveform_snapshot_f2 : lpp_waveform_snapshot | |
252 | GENERIC MAP ( |
|
252 | GENERIC MAP ( | |
253 | data_size => data_size, |
|
253 | data_size => data_size, | |
254 | nb_snapshot_param_size => nb_snapshot_param_size+1) |
|
254 | nb_snapshot_param_size => nb_snapshot_param_size+1) | |
255 | PORT MAP ( |
|
255 | PORT MAP ( | |
256 | clk => clk, |
|
256 | clk => clk, | |
257 | rstn => rstn, |
|
257 | rstn => rstn, | |
258 | run => run, |
|
258 | run => run, | |
259 | enable => enable_f2, |
|
259 | enable => enable_f2, | |
260 | burst_enable => burst_f2, |
|
260 | burst_enable => burst_f2, | |
261 | nb_snapshot_param => nb_snapshot_param_more_one, |
|
261 | nb_snapshot_param => nb_snapshot_param_more_one, | |
262 | start_snapshot => start_snapshot_f2, |
|
262 | start_snapshot => start_snapshot_f2, | |
263 | data_in => data_f2_in, |
|
263 | data_in => data_f2_in, | |
264 | data_in_valid => data_f2_in_valid, |
|
264 | data_in_valid => data_f2_in_valid, | |
265 | data_out => data_f2_out, |
|
265 | data_out => data_f2_out, | |
266 | data_out_valid => data_f2_out_valid); |
|
266 | data_out_valid => data_f2_out_valid); | |
267 |
|
267 | |||
268 | lpp_waveform_burst_f3 : lpp_waveform_burst |
|
268 | lpp_waveform_burst_f3 : lpp_waveform_burst | |
269 | GENERIC MAP ( |
|
269 | GENERIC MAP ( | |
270 | data_size => data_size) |
|
270 | data_size => data_size) | |
271 | PORT MAP ( |
|
271 | PORT MAP ( | |
272 | clk => clk, |
|
272 | clk => clk, | |
273 | rstn => rstn, |
|
273 | rstn => rstn, | |
274 | run => run, |
|
274 | run => run, | |
275 | enable => enable_f3, |
|
275 | enable => enable_f3, | |
276 | data_in => data_f3_in, |
|
276 | data_in => data_f3_in, | |
277 | data_in_valid => data_f3_in_valid, |
|
277 | data_in_valid => data_f3_in_valid, | |
278 | data_out => data_f3_out, |
|
278 | data_out => data_f3_out, | |
279 | data_out_valid => data_f3_out_valid); |
|
279 | data_out_valid => data_f3_out_valid); | |
280 |
|
280 | |||
281 | ----------------------------------------------------------------------------- |
|
281 | ----------------------------------------------------------------------------- | |
282 | -- DEBUG |
|
282 | -- DEBUG | |
283 | debug_f0_data_valid <= data_f0_out_valid; |
|
283 | debug_f0_data_valid <= data_f0_out_valid; | |
284 | debug_f0_data <= data_f0_out; |
|
284 | debug_f0_data <= data_f0_out; | |
285 | debug_f1_data_valid <= data_f1_out_valid; |
|
285 | debug_f1_data_valid <= data_f1_out_valid; | |
286 | debug_f1_data <= data_f1_out; |
|
286 | debug_f1_data <= data_f1_out; | |
287 | debug_f2_data_valid <= data_f2_out_valid; |
|
287 | debug_f2_data_valid <= data_f2_out_valid; | |
288 | debug_f2_data <= data_f2_out; |
|
288 | debug_f2_data <= data_f2_out; | |
289 | debug_f3_data_valid <= data_f3_out_valid; |
|
289 | debug_f3_data_valid <= data_f3_out_valid; | |
290 | debug_f3_data <= data_f3_out; |
|
290 | debug_f3_data <= data_f3_out; | |
291 | ----------------------------------------------------------------------------- |
|
291 | ----------------------------------------------------------------------------- | |
292 |
|
292 | |||
293 | PROCESS (clk, rstn) |
|
293 | PROCESS (clk, rstn) | |
294 | BEGIN -- PROCESS |
|
294 | BEGIN -- PROCESS | |
295 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
295 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
296 | time_reg1 <= (OTHERS => '0'); |
|
296 | time_reg1 <= (OTHERS => '0'); | |
297 | time_reg2 <= (OTHERS => '0'); |
|
297 | time_reg2 <= (OTHERS => '0'); | |
298 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
298 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
299 | time_reg1 <= fine_time & coarse_time; |
|
299 | time_reg1 <= fine_time & coarse_time; | |
300 | time_reg2 <= time_reg1; |
|
300 | time_reg2 <= time_reg1; | |
301 | END IF; |
|
301 | END IF; | |
302 | END PROCESS; |
|
302 | END PROCESS; | |
303 |
|
303 | |||
304 | valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; |
|
304 | valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; | |
305 | all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE |
|
305 | all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE | |
306 | lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid |
|
306 | lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid | |
307 | PORT MAP ( |
|
307 | PORT MAP ( | |
308 | HCLK => clk, |
|
308 | HCLK => clk, | |
309 | HRESETn => rstn, |
|
309 | HRESETn => rstn, | |
310 | run => run, |
|
310 | run => run, | |
311 | valid_in => valid_in(I), |
|
311 | valid_in => valid_in(I), | |
312 | ack_in => valid_ack(I), |
|
312 | ack_in => valid_ack(I), | |
313 | time_in => time_reg2, -- Todo |
|
313 | time_in => time_reg2, -- Todo | |
314 | valid_out => valid_out(I), |
|
314 | valid_out => valid_out(I), | |
315 | time_out => time_out(I), -- Todo |
|
315 | time_out => time_out(I), -- Todo | |
316 | error => status_new_err(I)); |
|
316 | error => status_new_err(I)); | |
317 | END GENERATE all_input_valid; |
|
317 | END GENERATE all_input_valid; | |
318 |
|
318 | |||
319 | all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE |
|
319 | all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE | |
320 | data_out(0,I) <= data_f0_out(I); |
|
320 | data_out(0,I) <= data_f0_out(I); | |
321 | data_out(1,I) <= data_f1_out(I); |
|
321 | data_out(1,I) <= data_f1_out(I); | |
322 | data_out(2,I) <= data_f2_out(I); |
|
322 | data_out(2,I) <= data_f2_out(I); | |
323 | data_out(3,I) <= data_f3_out(I); |
|
323 | data_out(3,I) <= data_f3_out(I); | |
324 | END GENERATE all_bit_of_data_out; |
|
324 | END GENERATE all_bit_of_data_out; | |
325 |
|
325 | |||
326 | ----------------------------------------------------------------------------- |
|
326 | ----------------------------------------------------------------------------- | |
327 | -- TODO : debug |
|
327 | -- TODO : debug | |
328 | ----------------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------------- | |
329 | --all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE |
|
329 | --all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE | |
330 | -- all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE |
|
330 | -- all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE | |
331 | -- time_out_2(J,I) <= time_out(J)(I); |
|
331 | -- time_out_2(J,I) <= time_out(J)(I); | |
332 | -- END GENERATE all_sample_of_time_out; |
|
332 | -- END GENERATE all_sample_of_time_out; | |
333 | --END GENERATE all_bit_of_time_out; |
|
333 | --END GENERATE all_bit_of_time_out; | |
|
334 | ||||
334 |
|
|
335 | time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; | |
335 | time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; |
|
336 | time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; | |
336 | time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; |
|
337 | time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; | |
337 | time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; |
|
338 | time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; | |
338 |
|
339 | |||
339 | all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE |
|
340 | all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE | |
340 | all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE |
|
341 | all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE | |
341 | time_out_2(J,I) <= time_out_debug(J)(I); |
|
342 | time_out_2(J,I) <= time_out_debug(J)(I); | |
342 | END GENERATE all_sample_of_time_out; |
|
343 | END GENERATE all_sample_of_time_out; | |
343 | END GENERATE all_bit_of_time_out; |
|
344 | END GENERATE all_bit_of_time_out; | |
344 |
|
345 | |||
345 | lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter |
|
346 | lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter | |
346 | GENERIC MAP (tech => tech, |
|
347 | GENERIC MAP (tech => tech, | |
347 | nb_data_by_buffer_size =>nb_data_by_buffer_size) |
|
348 | nb_data_by_buffer_size =>nb_data_by_buffer_size) | |
348 | PORT MAP ( |
|
349 | PORT MAP ( | |
349 | clk => clk, |
|
350 | clk => clk, | |
350 | rstn => rstn, |
|
351 | rstn => rstn, | |
351 | run => run, |
|
352 | run => run, | |
352 | nb_data_by_buffer => nb_data_by_buffer, |
|
353 | nb_data_by_buffer => nb_data_by_buffer, | |
353 | data_in_valid => valid_out, |
|
354 | data_in_valid => valid_out, | |
354 | data_in_ack => valid_ack, |
|
355 | data_in_ack => valid_ack, | |
355 | data_in => data_out, |
|
356 | data_in => data_out, | |
356 | time_in => time_out_2, |
|
357 | time_in => time_out_2, | |
357 |
|
358 | |||
358 | data_out => wdata, |
|
359 | data_out => wdata, | |
359 | data_out_wen => data_wen, |
|
360 | data_out_wen => data_wen, | |
360 | full_almost => full_almost, |
|
361 | full_almost => full_almost, | |
361 | full => full); |
|
362 | full => full); | |
362 |
|
363 | |||
363 | lpp_waveform_fifo_1 : lpp_waveform_fifo |
|
364 | lpp_waveform_fifo_1 : lpp_waveform_fifo | |
364 | GENERIC MAP (tech => tech) |
|
365 | GENERIC MAP (tech => tech) | |
365 | PORT MAP ( |
|
366 | PORT MAP ( | |
366 | clk => clk, |
|
367 | clk => clk, | |
367 | rstn => rstn, |
|
368 | rstn => rstn, | |
368 | run => run, |
|
369 | run => run, | |
369 |
|
370 | |||
370 | empty => empty, |
|
371 | empty => empty, | |
371 | empty_almost => empty_almost, |
|
372 | empty_almost => empty_almost, | |
372 |
|
373 | |||
373 | data_ren => data_ren, |
|
374 | data_ren => data_ren, | |
374 | rdata => rdata, |
|
375 | rdata => rdata, | |
375 |
|
376 | |||
376 |
|
377 | |||
377 | full_almost => full_almost, |
|
378 | full_almost => full_almost, | |
378 | full => full, |
|
379 | full => full, | |
379 | data_wen => data_wen, |
|
380 | data_wen => data_wen, | |
380 | wdata => wdata); |
|
381 | wdata => wdata); | |
381 |
|
382 | |||
382 | data_f0_data_out <= rdata; |
|
383 | data_f0_data_out <= rdata; | |
383 | data_f1_data_out <= rdata; |
|
384 | data_f1_data_out <= rdata; | |
384 | data_f2_data_out <= rdata; |
|
385 | data_f2_data_out <= rdata; | |
385 | data_f3_data_out <= rdata; |
|
386 | data_f3_data_out <= rdata; | |
386 |
|
||||
387 | --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency |
|
|||
388 | -- GENERIC MAP ( |
|
|||
389 | -- tech => tech) |
|
|||
390 | -- PORT MAP ( |
|
|||
391 | -- clk => clk, |
|
|||
392 | -- rstn => rstn, |
|
|||
393 | -- run => run, |
|
|||
394 |
|
||||
395 | -- empty_almost => empty_almost, |
|
|||
396 | -- empty => empty, |
|
|||
397 | -- data_ren => data_ren, |
|
|||
398 |
|
||||
399 | -- rdata_0 => data_f0_data_out, |
|
|||
400 | -- rdata_1 => data_f1_data_out, |
|
|||
401 | -- rdata_2 => data_f2_data_out, |
|
|||
402 | -- rdata_3 => data_f3_data_out, |
|
|||
403 |
|
||||
404 | -- full_almost => full_almost, |
|
|||
405 | -- full => full, |
|
|||
406 | -- data_wen => data_wen, |
|
|||
407 | -- wdata => wdata); |
|
|||
408 |
|
||||
409 |
|
||||
410 |
|
||||
411 |
|
387 | |||
412 | data_ren <= data_f3_data_out_ren & |
|
388 | data_ren <= data_f3_data_out_ren & | |
413 | data_f2_data_out_ren & |
|
389 | data_f2_data_out_ren & | |
414 | data_f1_data_out_ren & |
|
390 | data_f1_data_out_ren & | |
415 | data_f0_data_out_ren; |
|
391 | data_f0_data_out_ren; | |
416 |
|
392 | |||
417 | ----------------------------------------------------------------------------- |
|
|||
418 | -- TODO : set the alterance : time, data, data, ..... |
|
|||
419 | ----------------------------------------------------------------------------- |
|
|||
420 |
|
|
393 | lpp_waveform_gen_address_1 : lpp_waveform_genaddress | |
421 | GENERIC MAP ( |
|
394 | GENERIC MAP ( | |
422 | nb_data_by_buffer_size => nb_word_by_buffer_size) |
|
395 | nb_data_by_buffer_size => nb_word_by_buffer_size) | |
423 | PORT MAP ( |
|
396 | PORT MAP ( | |
424 | clk => clk, |
|
397 | clk => clk, | |
425 | rstn => rstn, |
|
398 | rstn => rstn, | |
426 | run => run, |
|
399 | run => run, | |
427 |
|
400 | |||
428 | ------------------------------------------------------------------------- |
|
401 | ------------------------------------------------------------------------- | |
429 | -- CONFIG |
|
402 | -- CONFIG | |
430 | ------------------------------------------------------------------------- |
|
403 | ------------------------------------------------------------------------- | |
431 | nb_data_by_buffer => nb_word_by_buffer, |
|
404 | nb_data_by_buffer => nb_word_by_buffer, | |
432 |
|
405 | |||
433 | addr_data_f0 => addr_data_f0, |
|
406 | addr_data_f0 => addr_data_f0, | |
434 | addr_data_f1 => addr_data_f1, |
|
407 | addr_data_f1 => addr_data_f1, | |
435 | addr_data_f2 => addr_data_f2, |
|
408 | addr_data_f2 => addr_data_f2, | |
436 | addr_data_f3 => addr_data_f3, |
|
409 | addr_data_f3 => addr_data_f3, | |
437 | ------------------------------------------------------------------------- |
|
410 | ------------------------------------------------------------------------- | |
438 | -- CTRL |
|
411 | -- CTRL | |
439 | ------------------------------------------------------------------------- |
|
412 | ------------------------------------------------------------------------- | |
440 | -- IN |
|
413 | -- IN | |
441 | empty => empty, |
|
414 | empty => empty, | |
442 | empty_almost => empty_almost, |
|
415 | empty_almost => empty_almost, | |
443 | data_ren => data_ren, |
|
416 | data_ren => data_ren, | |
444 |
|
417 | |||
445 | ------------------------------------------------------------------------- |
|
418 | ------------------------------------------------------------------------- | |
446 | -- STATUS |
|
419 | -- STATUS | |
447 | ------------------------------------------------------------------------- |
|
420 | ------------------------------------------------------------------------- | |
448 | status_full => status_full, |
|
421 | status_full => status_full, | |
449 | status_full_ack => status_full_ack, |
|
422 | status_full_ack => status_full_ack, | |
450 | status_full_err => status_full_err, |
|
423 | status_full_err => status_full_err, | |
451 |
|
424 | |||
452 | ------------------------------------------------------------------------- |
|
425 | ------------------------------------------------------------------------- | |
453 | -- ADDR DATA OUT |
|
426 | -- ADDR DATA OUT | |
454 | ------------------------------------------------------------------------- |
|
427 | ------------------------------------------------------------------------- | |
455 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, |
|
428 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, | |
456 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, |
|
429 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, | |
457 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, |
|
430 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, | |
458 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, |
|
431 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, | |
459 |
|
432 | |||
460 | data_f0_data_out_valid => data_f0_data_out_valid, |
|
433 | data_f0_data_out_valid => data_f0_data_out_valid, | |
461 | data_f1_data_out_valid => data_f1_data_out_valid, |
|
434 | data_f1_data_out_valid => data_f1_data_out_valid, | |
462 | data_f2_data_out_valid => data_f2_data_out_valid, |
|
435 | data_f2_data_out_valid => data_f2_data_out_valid, | |
463 | data_f3_data_out_valid => data_f3_data_out_valid, |
|
436 | data_f3_data_out_valid => data_f3_data_out_valid, | |
464 |
|
437 | |||
465 | data_f0_addr_out => data_f0_addr_out, |
|
438 | data_f0_addr_out => data_f0_addr_out, | |
466 | data_f1_addr_out => data_f1_addr_out, |
|
439 | data_f1_addr_out => data_f1_addr_out, | |
467 | data_f2_addr_out => data_f2_addr_out, |
|
440 | data_f2_addr_out => data_f2_addr_out, | |
468 | data_f3_addr_out => data_f3_addr_out |
|
441 | data_f3_addr_out => data_f3_addr_out | |
469 | ); |
|
442 | ); | |
470 |
|
443 | |||
471 | END beh; |
|
444 | END beh; |
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