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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.sim.ALL;
32 32 USE gaisler.memctrl.ALL;
33 33 USE gaisler.leon3.ALL;
34 34 USE gaisler.uart.ALL;
35 35 USE gaisler.misc.ALL;
36 36 USE gaisler.spacewire.ALL;
37 37 LIBRARY esa;
38 38 USE esa.memoryctrl.ALL;
39 39 LIBRARY lpp;
40 40 USE lpp.lpp_memory.ALL;
41 41 USE lpp.lpp_ad_conv.ALL;
42 42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 44 USE lpp.iir_filter.ALL;
45 45 USE lpp.general_purpose.ALL;
46 46 USE lpp.lpp_lfr_management.ALL;
47 47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 48 USE lpp.lpp_bootloader_pkg.ALL;
49 49
50 50 --library proasic3l;
51 51 --use proasic3l.all;
52 52
53 53 ENTITY LFR_EQM IS
54 54 GENERIC (
55 55 Mem_use : INTEGER := use_RAM;
56 56 USE_BOOTLOADER : INTEGER := 0;
57 USE_ADCDRIVER : INTEGER := 0;
57 USE_ADCDRIVER : INTEGER := 1;
58 58 tech : INTEGER := apa3e;
59 59 tech_leon : INTEGER := apa3e;
60 60 DEBUG_FORCE_DATA_DMA : INTEGER := 1;
61 61 USE_DEBUG_VECTOR : INTEGER := 1
62 62 );
63 63
64 64 PORT (
65 65 clk50MHz : IN STD_ULOGIC;
66 66 clk49_152MHz : IN STD_ULOGIC;
67 67 reset : IN STD_ULOGIC;
68 68
69 69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70 70
71 71 -- TAG --------------------------------------------------------------------
72 72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 74 -- UART APB ---------------------------------------------------------------
75 75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 77 -- RAM --------------------------------------------------------------------
78 78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80
81 81 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 82 nSRAM_E1 : OUT STD_LOGIC; -- new
83 83 nSRAM_E2 : OUT STD_LOGIC; -- new
84 84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 85 nSRAM_W : OUT STD_LOGIC; -- new
86 86 nSRAM_G : OUT STD_LOGIC; -- new
87 87 nSRAM_BUSY : IN STD_LOGIC; -- new
88 88 -- SPW --------------------------------------------------------------------
89 89 spw1_en : OUT STD_LOGIC; -- new
90 90 spw1_din : IN STD_LOGIC;
91 91 spw1_sin : IN STD_LOGIC;
92 92 spw1_dout : OUT STD_LOGIC;
93 93 spw1_sout : OUT STD_LOGIC;
94 94 spw2_en : OUT STD_LOGIC; -- new
95 95 spw2_din : IN STD_LOGIC;
96 96 spw2_sin : IN STD_LOGIC;
97 97 spw2_dout : OUT STD_LOGIC;
98 98 spw2_sout : OUT STD_LOGIC;
99 99 -- ADC --------------------------------------------------------------------
100 100 bias_fail_sw : OUT STD_LOGIC;
101 101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102 ADC_smpclk : OUT STD_LOGIC;
103 103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 104 -- DAC --------------------------------------------------------------------
105 105 DAC_SDO : OUT STD_LOGIC;
106 106 DAC_SCK : OUT STD_LOGIC;
107 107 DAC_SYNC : OUT STD_LOGIC;
108 108 DAC_CAL_EN : OUT STD_LOGIC;
109 109 -- HK ---------------------------------------------------------------------
110 110 HK_smpclk : OUT STD_LOGIC;
111 111 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
113 113 ---------------------------------------------------------------------------
114 114 -- TAG8 : OUT STD_LOGIC
115 115 );
116 116
117 117 END LFR_EQM;
118 118
119 119
120 120 ARCHITECTURE beh OF LFR_EQM IS
121 121
122 122 SIGNAL clk_25 : STD_LOGIC := '0';
123 123 SIGNAL clk_24 : STD_LOGIC := '0';
124 124 -----------------------------------------------------------------------------
125 125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127 127
128 128 -- CONSTANTS
129 129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133 133
134 134 SIGNAL apbi_ext : apb_slv_in_type;
135 135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140 140
141 141 -- Spacewire signals
142 142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 145 SIGNAL spw_rxtxclk : STD_ULOGIC;
146 146 SIGNAL spw_rxclkn : STD_ULOGIC;
147 147 SIGNAL spw_clk : STD_LOGIC;
148 148 SIGNAL swni : grspw_in_type;
149 149 SIGNAL swno : grspw_out_type;
150 150
151 151 --GPIO
152 152 SIGNAL gpioi : gpio_in_type;
153 153 SIGNAL gpioo : gpio_out_type;
154 154
155 155 -- AD Converter ADS7886
156 156 SIGNAL sample : Samples14v(8 DOWNTO 0);
157 157 SIGNAL sample_s : Samples(8 DOWNTO 0);
158 158 SIGNAL sample_val : STD_LOGIC;
159 159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
160 160
161 161 -----------------------------------------------------------------------------
162 162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 163
164 164 -----------------------------------------------------------------------------
165 165 SIGNAL rstn_25 : STD_LOGIC;
166 166 SIGNAL rstn_24 : STD_LOGIC;
167 167
168 168 SIGNAL LFR_soft_rstn : STD_LOGIC;
169 169 SIGNAL LFR_rstn : STD_LOGIC;
170 170
171 171 SIGNAL ADC_smpclk_s : STD_LOGIC;
172 172
173 173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 174
175 175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
176 176 SIGNAL clk_25_int : STD_LOGIC := '0';
177 177
178 178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
179 179
180 180 SIGNAL rstn_50 : STD_LOGIC;
181 181 SIGNAL clk_lock : STD_LOGIC;
182 182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
184 184
185 185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 186 SIGNAL ahbrxd: STD_LOGIC;
187 187 SIGNAL ahbtxd: STD_LOGIC;
188 188 SIGNAL urxd1 : STD_LOGIC;
189 189 SIGNAL utxd1 : STD_LOGIC;
190 190 BEGIN -- beh
191 191
192 192 -----------------------------------------------------------------------------
193 193 -- CLK_LOCK
194 194 -----------------------------------------------------------------------------
195 195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
196 196
197 197 PROCESS (clk50MHz_int, rstn_50)
198 198 BEGIN -- PROCESS
199 199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
200 200 clk_lock <= '0';
201 201 clk_busy_counter <= (OTHERS => '0');
202 202 nSRAM_BUSY_reg <= '0';
203 203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
204 204 nSRAM_BUSY_reg <= nSRAM_BUSY;
205 205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
206 206 IF clk_busy_counter = "1111" THEN
207 207 clk_lock <= '1';
208 208 ELSE
209 209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
210 210 END IF;
211 211 END IF;
212 212 END IF;
213 213 END PROCESS;
214 214
215 215 -----------------------------------------------------------------------------
216 216 -- CLK
217 217 -----------------------------------------------------------------------------
218 218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
219 219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
220 220
221 221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
222 222 clk50MHz_int <= clk50MHz;
223 223
224 224 PROCESS(clk50MHz_int)
225 225 BEGIN
226 226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
227 227 --clk_25_int <= NOT clk_25_int;
228 228 clk_25 <= NOT clk_25;
229 229 END IF;
230 230 END PROCESS;
231 231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
232 232
233 233 PROCESS(clk49_152MHz)
234 234 BEGIN
235 235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
236 236 clk_24 <= NOT clk_24;
237 237 END IF;
238 238 END PROCESS;
239 239
240 240 -----------------------------------------------------------------------------
241 241 --
242 242 leon3_soc_1 : leon3_soc
243 243 GENERIC MAP (
244 244 fabtech => tech_leon,
245 245 memtech => tech_leon,
246 246 padtech => inferred,
247 247 clktech => inferred,
248 248 disas => 0,
249 249 dbguart => 0,
250 250 pclow => 2,
251 251 clk_freq => 25000,
252 252 IS_RADHARD => 0,
253 253 NB_CPU => 1,
254 254 ENABLE_FPU => 1,
255 255 FPU_NETLIST => 0,
256 256 ENABLE_DSU => 1,
257 257 ENABLE_AHB_UART => 1,
258 258 ENABLE_APB_UART => 1,
259 259 ENABLE_IRQMP => 1,
260 260 ENABLE_GPT => 1,
261 261 NB_AHB_MASTER => NB_AHB_MASTER,
262 262 NB_AHB_SLAVE => NB_AHB_SLAVE,
263 263 NB_APB_SLAVE => NB_APB_SLAVE,
264 264 ADDRESS_SIZE => 19,
265 265 USES_IAP_MEMCTRLR => 1,
266 266 BYPASS_EDAC_MEMCTRLR => '0',
267 267 SRBANKSZ => 8)
268 268 PORT MAP (
269 269 clk => clk_25,
270 270 reset => rstn_25,
271 271 errorn => OPEN,
272 272
273 273 ahbrxd => ahbrxd, -- INPUT
274 274 ahbtxd => ahbtxd, -- OUTPUT
275 275 urxd1 => urxd1, -- INPUT
276 276 utxd1 => utxd1, -- OUTPUT
277 277
278 278 address => address,
279 279 data => data,
280 280 nSRAM_BE0 => OPEN,
281 281 nSRAM_BE1 => OPEN,
282 282 nSRAM_BE2 => OPEN,
283 283 nSRAM_BE3 => OPEN,
284 284 nSRAM_WE => nSRAM_W,
285 285 nSRAM_CE => nSRAM_CE,
286 286 nSRAM_OE => nSRAM_G,
287 287 nSRAM_READY => nSRAM_BUSY,
288 288 SRAM_MBE => nSRAM_MBE,
289 289
290 290 apbi_ext => apbi_ext,
291 291 apbo_ext => apbo_ext,
292 292 ahbi_s_ext => ahbi_s_ext,
293 293 ahbo_s_ext => ahbo_s_ext,
294 294 ahbi_m_ext => ahbi_m_ext,
295 295 ahbo_m_ext => ahbo_m_ext);
296 296
297 297
298 298 nSRAM_E1 <= nSRAM_CE(0);
299 299 nSRAM_E2 <= nSRAM_CE(1);
300 300
301 301 -------------------------------------------------------------------------------
302 302 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
303 303 -------------------------------------------------------------------------------
304 304 apb_lfr_management_1 : apb_lfr_management
305 305 GENERIC MAP (
306 306 tech => tech,
307 307 pindex => 6,
308 308 paddr => 6,
309 309 pmask => 16#fff#,
310 310 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
311 311 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
312 312 PORT MAP (
313 313 clk25MHz => clk_25,
314 314 resetn_25MHz => rstn_25, -- TODO
315 315 --clk24_576MHz => clk_24, -- 49.152MHz/2
316 316 --resetn_24_576MHz => rstn_24, -- TODO
317 317
318 318 grspw_tick => swno.tickout,
319 319 apbi => apbi_ext,
320 320 apbo => apbo_ext(6),
321 321
322 322 HK_sample => sample_s(8),
323 323 HK_val => sample_val,
324 324 HK_sel => HK_SEL,
325 325
326 326 DAC_SDO => DAC_SDO,
327 327 DAC_SCK => DAC_SCK,
328 328 DAC_SYNC => DAC_SYNC,
329 329 DAC_CAL_EN => DAC_CAL_EN,
330 330
331 331 coarse_time => coarse_time,
332 332 fine_time => fine_time,
333 333 LFR_soft_rstn => LFR_soft_rstn
334 334 );
335 335
336 336 -----------------------------------------------------------------------
337 337 --- SpaceWire --------------------------------------------------------
338 338 -----------------------------------------------------------------------
339 339
340 340 ------------------------------------------------------------------------------
341 341 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
342 342 ------------------------------------------------------------------------------
343 343 spw1_en <= '1';
344 344 spw2_en <= '1';
345 345 ------------------------------------------------------------------------------
346 346 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
347 347 ------------------------------------------------------------------------------
348 348
349 349 --spw_clk <= clk50MHz;
350 350 --spw_rxtxclk <= spw_clk;
351 351 --spw_rxclkn <= NOT spw_rxtxclk;
352 352
353 353 -- PADS for SPW1
354 354 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
355 355 PORT MAP (spw1_din, dtmp(0));
356 356 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
357 357 PORT MAP (spw1_sin, stmp(0));
358 358 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
359 359 PORT MAP (spw1_dout, swno.d(0));
360 360 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
361 361 PORT MAP (spw1_sout, swno.s(0));
362 362 -- PADS FOR SPW2
363 363 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
364 364 PORT MAP (spw2_din, dtmp(1));
365 365 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
366 366 PORT MAP (spw2_sin, stmp(1));
367 367 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
368 368 PORT MAP (spw2_dout, swno.d(1));
369 369 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
370 370 PORT MAP (spw2_sout, swno.s(1));
371 371
372 372 -- GRSPW PHY
373 373 --spw1_input: if CFG_SPW_GRSPW = 1 generate
374 374 spw_inputloop : FOR j IN 0 TO 1 GENERATE
375 375 spw_phy0 : grspw_phy
376 376 GENERIC MAP(
377 377 tech => tech_leon,
378 378 rxclkbuftype => 1,
379 379 scantest => 0)
380 380 PORT MAP(
381 381 rxrst => swno.rxrst,
382 382 di => dtmp(j),
383 383 si => stmp(j),
384 384 rxclko => spw_rxclk(j),
385 385 do => swni.d(j),
386 386 ndo => swni.nd(j*5+4 DOWNTO j*5),
387 387 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
388 388 END GENERATE spw_inputloop;
389 389
390 390 -- SPW core
391 391 sw0 : grspwm GENERIC MAP(
392 392 tech => tech_leon,
393 393 hindex => 1,
394 394 pindex => 5,
395 395 paddr => 5,
396 396 pirq => 11,
397 397 sysfreq => 25000, -- CPU_FREQ
398 398 rmap => 1,
399 399 rmapcrc => 1,
400 400 fifosize1 => 16,
401 401 fifosize2 => 16,
402 402 rxclkbuftype => 1,
403 403 rxunaligned => 0,
404 404 rmapbufs => 4,
405 405 ft => 0,
406 406 netlist => 0,
407 407 ports => 2,
408 408 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
409 409 memtech => tech_leon,
410 410 destkey => 2,
411 411 spwcore => 1
412 412 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
413 413 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
414 414 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
415 415 )
416 416 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
417 417 spw_rxclk(1),
418 418 clk50MHz_int,
419 419 clk50MHz_int,
420 420 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
421 421 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
422 422 swni, swno);
423 423
424 424 swni.tickin <= '0';
425 425 swni.rmapen <= '1';
426 426 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
427 427 swni.tickinraw <= '0';
428 428 swni.timein <= (OTHERS => '0');
429 429 swni.dcrstval <= (OTHERS => '0');
430 430 swni.timerrstval <= (OTHERS => '0');
431 431
432 432 -------------------------------------------------------------------------------
433 433 -- LFR ------------------------------------------------------------------------
434 434 -------------------------------------------------------------------------------
435 435 LFR_rstn <= LFR_soft_rstn AND rstn_25;
436 436
437 437 lpp_lfr_1 : lpp_lfr
438 438 GENERIC MAP (
439 439 Mem_use => Mem_use,
440 440 tech => tech,
441 441 nb_data_by_buffer_size => 32,
442 442 --nb_word_by_buffer_size => 30,
443 443 nb_snapshot_param_size => 32,
444 444 delta_vector_size => 32,
445 445 delta_vector_size_f0_2 => 7, -- log2(96)
446 446 pindex => 15,
447 447 paddr => 15,
448 448 pmask => 16#fff#,
449 449 pirq_ms => 6,
450 450 pirq_wfp => 14,
451 451 hindex => 2,
452 452 top_lfr_version => X"020148", -- aa.bb.cc version
453 453 -- AA : BOARD NUMBER
454 454 -- 0 => MINI_LFR
455 455 -- 1 => EM
456 456 -- 2 => EQM (with A3PE3000)
457 457 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
458 458 PORT MAP (
459 459 clk => clk_25,
460 460 rstn => LFR_rstn,
461 461 sample_B => sample_s(2 DOWNTO 0),
462 462 sample_E => sample_s(7 DOWNTO 3),
463 463 sample_val => sample_val,
464 464 apbi => apbi_ext,
465 465 apbo => apbo_ext(15),
466 466 ahbi => ahbi_m_ext,
467 467 ahbo => ahbo_m_ext(2),
468 468 coarse_time => coarse_time,
469 469 fine_time => fine_time,
470 470 data_shaping_BW => bias_fail_sw,
471 471 debug_vector => debug_vector,
472 472 debug_vector_ms => OPEN); --,
473 473 --observation_vector_0 => OPEN,
474 474 --observation_vector_1 => OPEN,
475 475 --observation_reg => observation_reg);
476 476
477 477
478 478 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
479 479 sample_s(I) <= sample(I) & '0' & '0';
480 480 END GENERATE all_sample;
481 481 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
482 482
483 483 -----------------------------------------------------------------------------
484 484 --
485 485 -----------------------------------------------------------------------------
486 486 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
487 487 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
488 488 GENERIC MAP (
489 489 ChanelCount => 9,
490 490 ncycle_cnv_high => 13,
491 491 ncycle_cnv => 25,
492 492 FILTER_ENABLED => 16#FF#)
493 493 PORT MAP (
494 494 cnv_clk => clk_24,
495 495 cnv_rstn => rstn_24,
496 496 cnv => ADC_smpclk_s,
497 497 clk => clk_25,
498 498 rstn => rstn_25,
499 499 ADC_data => ADC_data,
500 500 ADC_nOE => ADC_OEB_bar_CH_s,
501 501 sample => sample,
502 502 sample_val => sample_val);
503 503
504 504 END GENERATE USE_ADCDRIVER_true;
505 505
506 506 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
507 507 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
508 508 GENERIC MAP (
509 509 ChanelCount => 9,
510 510 ncycle_cnv_high => 13,
511 511 ncycle_cnv => 25,
512 512 FILTER_ENABLED => 16#FF#)
513 513 PORT MAP (
514 514 cnv_clk => clk_24,
515 515 cnv_rstn => rstn_24,
516 516 cnv => ADC_smpclk_s,
517 517 clk => clk_25,
518 518 rstn => rstn_25,
519 519 ADC_data => ADC_data,
520 520 ADC_nOE => OPEN,
521 521 sample => OPEN,
522 522 sample_val => sample_val);
523 523
524 524 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
525 525
526 526 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
527 527 ramp_generator_1: ramp_generator
528 528 GENERIC MAP (
529 529 DATA_SIZE => 14,
530 530 VALUE_UNSIGNED_INIT => 2**I,
531 531 VALUE_UNSIGNED_INCR => 0,
532 532 VALUE_UNSIGNED_MASK => 16#3FFF#)
533 533 PORT MAP (
534 534 clk => clk_25,
535 535 rstn => rstn_25,
536 536 new_data => sample_val,
537 537 output_data => sample(I) );
538 538 END GENERATE all_sample;
539 539
540 540
541 541 END GENERATE USE_ADCDRIVER_false;
542 542
543 543
544 544
545 545
546 546 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
547 547
548 548 ADC_smpclk <= ADC_smpclk_s;
549 549 HK_smpclk <= ADC_smpclk_s;
550 550
551 551
552 552 -----------------------------------------------------------------------------
553 553 -- HK
554 554 -----------------------------------------------------------------------------
555 555 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
556 556
557 557 -----------------------------------------------------------------------------
558 558 --
559 559 -----------------------------------------------------------------------------
560 560 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
561 561 lpp_bootloader_1: lpp_bootloader
562 562 GENERIC MAP (
563 563 pindex => 13,
564 564 paddr => 13,
565 565 pmask => 16#fff#,
566 566 hindex => 3,
567 567 haddr => 0,
568 568 hmask => 16#fff#)
569 569 PORT MAP (
570 570 HCLK => clk_25,
571 571 HRESETn => rstn_25,
572 572 apbi => apbi_ext,
573 573 apbo => apbo_ext(13),
574 574 ahbsi => ahbi_s_ext,
575 575 ahbso => ahbo_s_ext(3));
576 576 END GENERATE inst_bootloader;
577 577
578 578 -----------------------------------------------------------------------------
579 579 --
580 580 -----------------------------------------------------------------------------
581 581 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
582 582 PROCESS (clk_25, rstn_25)
583 583 BEGIN -- PROCESS
584 584 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
585 585 TAG <= (OTHERS => '0');
586 586 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
587 587 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
588 588 END IF;
589 589 END PROCESS;
590 590
591 591
592 592 END GENERATE USE_DEBUG_VECTOR_IF;
593 593
594 594 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
595 595 ahbrxd <= TAG(1);
596 596 TAG(3) <= ahbtxd;
597 597 urxd1 <= TAG(2);
598 598 TAG(4) <= utxd1;
599 599 TAG(8) <= nSRAM_BUSY;
600 600 END GENERATE USE_DEBUG_VECTOR_IF2;
601 601
602 602 END beh;
Show file before | Show file after | Hide comments
@@ -1,679 +1,679
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE IEEE.NUMERIC_STD.ALL;
26 26
27 27 LIBRARY techmap;
28 28 USE techmap.gencomp.ALL;
29 29
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_sim_pkg.ALL;
32 32 USE lpp.lpp_lfr_sim_pkg.ALL;
33 33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
34 34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
35 35 USE lpp.iir_filter.ALL;
36 36 USE lpp.FILTERcfg.ALL;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_waveform_pkg.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 40 USE lpp.lpp_top_lfr_pkg.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL;
42 42 USE lpp.general_purpose.ALL;
43 43 --LIBRARY lpp;
44 44 USE lpp.lpp_ad_conv.ALL;
45 45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
46 46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
47 47
48 48 --USE work.debug.ALL;
49 49
50 50 LIBRARY gaisler;
51 51 USE gaisler.libdcom.ALL;
52 52 USE gaisler.sim.ALL;
53 53 USE gaisler.memctrl.ALL;
54 54 USE gaisler.leon3.ALL;
55 55 USE gaisler.uart.ALL;
56 56 USE gaisler.misc.ALL;
57 57 USE gaisler.spacewire.ALL;
58 58
59 59 ENTITY TB IS
60 60
61 61 END TB;
62 62
63 63 ARCHITECTURE beh OF TB IS
64 -- CONSTANT sramfile : STRING := "prom.srec";
65 CONSTANT sramfile : STRING;
64 CONSTANT sramfile : STRING := "prom.srec";
65 -- CONSTANT sramfile : STRING;
66 66
67 67 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
68 68
69 69 COMPONENT LFR_EQM
70 70 GENERIC (
71 71 Mem_use : INTEGER;
72 72 USE_BOOTLOADER : INTEGER;
73 73 USE_ADCDRIVER : INTEGER;
74 74 tech : INTEGER;
75 75 tech_leon : INTEGER;
76 76 DEBUG_FORCE_DATA_DMA : INTEGER;
77 77 USE_DEBUG_VECTOR : INTEGER );
78 78 PORT (
79 79 clk50MHz : IN STD_ULOGIC;
80 80 clk49_152MHz : IN STD_ULOGIC;
81 81 reset : IN STD_ULOGIC;
82 82 --TAG1 : IN STD_ULOGIC;
83 83 --TAG3 : OUT STD_ULOGIC;
84 84 --TAG2 : IN STD_ULOGIC;
85 85 --TAG4 : OUT STD_ULOGIC;
86 86 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
87 87 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
88 88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 nSRAM_MBE : INOUT STD_LOGIC;
90 90 nSRAM_E1 : OUT STD_LOGIC;
91 91 nSRAM_E2 : OUT STD_LOGIC;
92 92 nSRAM_W : OUT STD_LOGIC;
93 93 nSRAM_G : OUT STD_LOGIC;
94 94 nSRAM_BUSY : IN STD_LOGIC;
95 95 spw1_en : OUT STD_LOGIC;
96 96 spw1_din : IN STD_LOGIC;
97 97 spw1_sin : IN STD_LOGIC;
98 98 spw1_dout : OUT STD_LOGIC;
99 99 spw1_sout : OUT STD_LOGIC;
100 100 spw2_en : OUT STD_LOGIC;
101 101 spw2_din : IN STD_LOGIC;
102 102 spw2_sin : IN STD_LOGIC;
103 103 spw2_dout : OUT STD_LOGIC;
104 104 spw2_sout : OUT STD_LOGIC;
105 105 bias_fail_sw : OUT STD_LOGIC;
106 106 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
107 107 ADC_smpclk : OUT STD_LOGIC;
108 108 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
109 109 DAC_SDO : OUT STD_LOGIC;
110 110 DAC_SCK : OUT STD_LOGIC;
111 111 DAC_SYNC : OUT STD_LOGIC;
112 112 DAC_CAL_EN : OUT STD_LOGIC;
113 113 HK_smpclk : OUT STD_LOGIC;
114 114 ADC_OEB_bar_HK : OUT STD_LOGIC;
115 115 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
116 116 END COMPONENT;
117 117
118 118 SIGNAL clk50MHz : STD_ULOGIC := '0';
119 119 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
120 120 SIGNAL reset : STD_ULOGIC;
121 121 SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1);
122 122 --SIGNAL TAG3 : STD_ULOGIC;
123 123 --SIGNAL TAG2 : STD_ULOGIC := '1';
124 124 --SIGNAL TAG4 : STD_ULOGIC;
125 125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
126 126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 SIGNAL nSRAM_MBE : STD_LOGIC;
128 128 SIGNAL nSRAM_E1 : STD_LOGIC;
129 129 SIGNAL nSRAM_E2 : STD_LOGIC;
130 130 SIGNAL nSRAM_W : STD_LOGIC;
131 131 SIGNAL nSRAM_G : STD_LOGIC;
132 132 SIGNAL nSRAM_BUSY : STD_LOGIC;
133 133 SIGNAL spw1_en : STD_LOGIC;
134 134 SIGNAL spw1_din : STD_LOGIC := '1';
135 135 SIGNAL spw1_sin : STD_LOGIC := '1';
136 136 SIGNAL spw1_dout : STD_LOGIC;
137 137 SIGNAL spw1_sout : STD_LOGIC;
138 138 SIGNAL spw2_en : STD_LOGIC;
139 139 SIGNAL spw2_din : STD_LOGIC := '1';
140 140 SIGNAL spw2_sin : STD_LOGIC := '1';
141 141 SIGNAL spw2_dout : STD_LOGIC;
142 142 SIGNAL spw2_sout : STD_LOGIC;
143 143 SIGNAL bias_fail_sw : STD_LOGIC;
144 144 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
145 145 SIGNAL ADC_smpclk : STD_LOGIC;
146 146 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
147 147 SIGNAL DAC_SDO : STD_LOGIC;
148 148 SIGNAL DAC_SCK : STD_LOGIC;
149 149 SIGNAL DAC_SYNC : STD_LOGIC;
150 150 SIGNAL DAC_CAL_EN : STD_LOGIC;
151 151 SIGNAL HK_smpclk : STD_LOGIC;
152 152 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
153 153 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
154 154 -- SIGNAL TAG8 : STD_LOGIC;
155 155
156 156 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
157 157 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
158 158 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
159 159 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
160 160 SIGNAL counter_scrub_period : INTEGER;
161 161
162 162
163 163 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
164 164 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
165 165 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
166 166
167 167 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
168 168 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
169 169 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
170 170 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
171 171 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
172 172 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
173 173
174 174 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
175 175 SIGNAL data_message : STRING(1 TO 15) := "---------------";
176 176 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
177 177 SIGNAL TXD1 : STD_LOGIC;
178 178 SIGNAL RXD1 : STD_LOGIC;
179 179
180 180 -----------------------------------------------------------------------------
181 181 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
182 182 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
183 183 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
184 184 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
185 185 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
186 186 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
187 187 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
188 188 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
189 189 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
190 190 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
191 191 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
192 192 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
193 193 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
194 194 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
195 195
196 196
197 197 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
198 198 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
199 199
200 200 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
201 201 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
202 202
203 203 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 204 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 205 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 206 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
207 207
208 208 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
209 209 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
210 210 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
211 211
212 212
213 213 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
214 214 -----------------------------------------------------------------------------
215 215 CONSTANT srambanks : INTEGER := 2;
216 216 CONSTANT sramwidth : INTEGER := 32;
217 217 CONSTANT sramdepth : INTEGER := 19;
218 218 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
219 219 -----------------------------------------------------------------------------
220 220
221 221 BEGIN -- beh
222 222
223 223 LFR_EQM_1 : LFR_EQM
224 224 GENERIC MAP (
225 225 Mem_use => use_RAM,
226 226 USE_BOOTLOADER => 0,
227 USE_ADCDRIVER => 0,
227 USE_ADCDRIVER => 1,
228 228 tech => apa3e,
229 229 tech_leon => apa3e,
230 230 DEBUG_FORCE_DATA_DMA => 1,
231 231 USE_DEBUG_VECTOR => 0)
232 232 PORT MAP (
233 233 clk50MHz => clk50MHz, --IN --ok
234 234 clk49_152MHz => clk49_152MHz, --in --ok
235 235 reset => reset, --IN --ok
236 236
237 237 TAG => TAG,
238 238 --TAG1 => TAG1, --in
239 239 --TAG3 => TAG3, --out
240 240 --TAG2 => TAG2, --IN --ok
241 241 --TAG4 => TAG4, --out --ok
242 242
243 243 address => address, --out
244 244 data => data, --inout
245 245 nSRAM_MBE => nSRAM_MBE, --inout
246 246 nSRAM_E1 => nSRAM_E1, --out
247 247 nSRAM_E2 => nSRAM_E2, --out
248 248 nSRAM_W => nSRAM_W, --out
249 249 nSRAM_G => nSRAM_G, --out
250 250 nSRAM_BUSY => nSRAM_BUSY, --in
251 251
252 252 spw1_en => spw1_en, --out --ok
253 253 spw1_din => spw1_din, --in --ok
254 254 spw1_sin => spw1_sin, --in --ok
255 255 spw1_dout => spw1_dout, --out --ok
256 256 spw1_sout => spw1_sout, --out --ok
257 257
258 258 spw2_en => spw2_en, --out --ok
259 259 spw2_din => spw2_din, --in --ok
260 260 spw2_sin => spw2_sin, --in --ok
261 261 spw2_dout => spw2_dout, --out --ok
262 262 spw2_sout => spw2_sout, --out --ok
263 263
264 264 bias_fail_sw => bias_fail_sw, --OUT --ok
265 265
266 266 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
267 267 ADC_smpclk => ADC_smpclk, --out --ok
268 268 ADC_data => ADC_data, --IN --ok
269 269
270 270 DAC_SDO => DAC_SDO, --out --ok
271 271 DAC_SCK => DAC_SCK, --out --ok
272 272 DAC_SYNC => DAC_SYNC, --out --ok
273 273 DAC_CAL_EN => DAC_CAL_EN, --out --ok
274 274
275 275 HK_smpclk => HK_smpclk, --out --ok
276 276 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
277 277 HK_SEL => HK_SEL); --out --ok
278 278
279 279
280 280 -----------------------------------------------------------------------------
281 281 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
282 282 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
283 283 -----------------------------------------------------------------------------
284 284
285 285 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
286 286 TestModule_RHF1401_1 : TestModule_RHF1401
287 287 GENERIC MAP (
288 288 freq => 24*(I+1),
289 289 amplitude => 8000/(I+1),
290 290 impulsion => 0)
291 291 PORT MAP (
292 292 ADC_smpclk => ADC_smpclk,
293 293 ADC_OEB_bar => ADC_OEB_bar_CH(I),
294 294 ADC_data => ADC_data);
295 295 END GENERATE MODULE_RHF1401;
296 296
297 297 -----------------------------------------------------------------------------
298 298 PROCESS (clk50MHz, reset)
299 299 BEGIN -- PROCESS
300 300 IF reset = '0' THEN -- asynchronous reset (active low)
301 301 nSRAM_BUSY <= '1';
302 302 counter_scrub_period <= 0;
303 303 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
304 304 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
305 305 counter_scrub_period <= 0;
306 306 ELSE
307 307 counter_scrub_period <= counter_scrub_period + 1;
308 308 END IF;
309 309
310 310 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
311 311 nSRAM_BUSY <= '1';
312 312 ELSE
313 313 nSRAM_BUSY <= '0';
314 314 END IF;
315 315 END IF;
316 316 END PROCESS;
317 317
318 318 -----------------------------------------------------------------------------
319 319 -- TB
320 320 -----------------------------------------------------------------------------
321 321 TAG(1) <= TXD1;
322 322 TAG(2) <= '1';
323 323 RXD1 <= TAG(3);
324 324
325 325 PROCESS
326 326 CONSTANT txp : TIME := 320 ns;
327 327 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
328 328 BEGIN -- PROCESS
329 329 TXD1 <= '1';
330 330 reset <= '0';
331 331 WAIT FOR 500 ns;
332 332 reset <= '1';
333 333 WAIT FOR 100 us;
334 334 message_simu <= "0 - UART init ";
335 335 UART_INIT(TXD1, txp);
336 336
337 337 ---------------------------------------------------------------------------
338 338 -- LAUNCH leon 3 software
339 339 ---------------------------------------------------------------------------
340 340 message_simu <= "2- GO Leon3....";
341 341
342 342 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
343 343 --Force a debug break
344 344 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
345 345 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
346 346 --Clear time tag counter
347 347 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
348 348 --Clear ASR registers
349 349 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
350 350 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
351 351 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
352 352 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
353 353 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
354 354 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
355 355 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
356 356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
357 357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
358 358 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
359 359 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
360 360 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
361 361 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
362 362 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
363 363 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
364 364
365 365 IF USE_ESA_MEMCTRL = 1 THEN
366 366 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
367 367 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
368 368 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
369 369 END IF;
370 370
371 371 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
372 372 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
373 373 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
374 374 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
375 375 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
376 376
377 377 --memSet(DSUBASEADDRESS+0x300000,0,1567);
378 378
379 379 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
380 380 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
381 381 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
382 382 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
383 383 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
384 384 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
385 385 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
386 386
387 387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
388 388 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
389 389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
390 390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
391 391 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
392 392 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
393 393 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
394 394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
395 395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
396 396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
397 397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
398 398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
399 399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
400 400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
401 401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
402 402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
403 403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
404 404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
405 405 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
406 406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
407 407 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
408 408 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
409 409 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
410 410 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
411 411
412 412 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
413 413
414 414 --//Disable interrupts
415 415 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
416 416 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
417 417 -- return false;
418 418 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
419 419 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
420 420 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
421 421
422 422 -- //Set up timer
423 423 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
424 424 --if(APBTIMERBASEADD == (unsigned int)-1)
425 425 -- return false;
426 426 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
427 427 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
428 428 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
429 429
430 430
431 431 ---------------------------------------------------------------------------
432 432 --bool dsu3plugin::setCacheEnable(bool enabled)
433 433 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
434 434 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
435 435 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
436 436 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
437 437 data_read <= data_read_v;
438 438 --if(enabled){
439 439 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
440 440 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
441 441 --}else{
442 442 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
443 443 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
444 444 --}
445 445
446 446
447 447 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
448 448 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
449 449
450 450 ---------------------------------------------------------------------------
451 451 --message_simu <= "1 - UART test ";
452 452 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
453 453 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
454 454 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
455 455 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
456 456 --data_read <= data_read_v;
457 457 --data_message <= "GPIO_data_write";
458 458
459 459 -- UNSET the LFR reset
460 460 message_simu <= "2 - LFR UNRESET";
461 461 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
462 462 --
463 463 message_simu <= "3 - LFR CONFIG ";
464 464 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
465 465 ADDR_BUFFER_MS_F0_0,
466 466 ADDR_BUFFER_MS_F0_1,
467 467 ADDR_BUFFER_MS_F1_0,
468 468 ADDR_BUFFER_MS_F1_1,
469 469 ADDR_BUFFER_MS_F2_0,
470 470 ADDR_BUFFER_MS_F2_1);
471 471
472 472
473 473 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
474 474 LFR_MODE_SBM1,
475 475 X"7FFFFFFF", -- START DATE
476 476
477 477 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
478 478 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
479 479 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
480 480 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
481 481 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
482 482 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
483 483
484 484 ADDR_BASE_LFR,
485 485 ADDR_BUFFER_WFP_F0_0,
486 486 ADDR_BUFFER_WFP_F0_1,
487 487 ADDR_BUFFER_WFP_F1_0,
488 488 ADDR_BUFFER_WFP_F1_1,
489 489 ADDR_BUFFER_WFP_F2_0,
490 490 ADDR_BUFFER_WFP_F2_1,
491 491 ADDR_BUFFER_WFP_F3_0,
492 492 ADDR_BUFFER_WFP_F3_1);
493 493
494 494 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
495 495 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
496 496
497 497
498 498 ---------------------------------------------------------------------------
499 499 -- CONFIG LFR 2
500 500 ---------------------------------------------------------------------------
501 501 --message_simu <= "3 - LFR2 CONFIG";
502 502 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
503 503 -- X"40000000",
504 504 -- X"40001000",
505 505 -- X"40002000",
506 506 -- X"40003000",
507 507 -- X"40004000",
508 508 -- X"40005000");
509 509
510 510
511 511 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
512 512 -- LFR_MODE_SBM1,
513 513 -- X"7FFFFFFF", -- START DATE
514 514
515 515 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
516 516 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
517 517 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
518 518 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
519 519 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
520 520 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
521 521
522 522 -- ADDR_BASE_LFR_2,
523 523 -- X"40006000",
524 524 -- X"40007000",
525 525 -- X"40008000",
526 526 -- X"40009000",
527 527 -- X"4000A000",
528 528 -- X"4000B000",
529 529 -- X"4000C000",
530 530 -- X"4000D000");
531 531
532 532 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
533 533 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
534 534
535 535 ---------------------------------------------------------------------------
536 536 ---------------------------------------------------------------------------
537 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"58", X"FFFFFFFF");
537 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"5" & "10", X"FFFFFFFF");
538 538
539 539
540 540 message_simu <= "4 - GO GO GO !!";
541 541 data_message <= "---------------";
542 542 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
543 543 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
544 544
545 545
546 546 data_read_v := (OTHERS => '1');
547 547 READ_STATUS : LOOP
548 548 data_message <= "---------------";
549 549 WAIT FOR 2 ms;
550 550 data_message <= "READ_STATUS_SM_";
551 551 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
552 552 --data_message <= "--------------r";
553 553 --data_read <= data_read_v;
554 554 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
555 555
556 556 data_message <= "READ_STATUS_WF_";
557 557 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
558 558 --data_message <= "--------------r";
559 559 --data_read <= data_read_v;
560 560 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
561 561 END LOOP READ_STATUS;
562 562
563 563 WAIT;
564 564 END PROCESS;
565 565
566 566
567 567 -----------------------------------------------------------------------------
568 568 PROCESS (nSRAM_W, reset)
569 569 BEGIN -- PROCESS
570 570 IF reset = '0' THEN -- asynchronous reset (active low)
571 571 data_pre_f0 <= X"00020001";
572 572 data_pre_f1 <= X"00020001";
573 573 data_pre_f2 <= X"00020001";
574 574
575 575 addr_pre_f0 <= (OTHERS => '0');
576 576 addr_pre_f1 <= (OTHERS => '0');
577 577 addr_pre_f2 <= (OTHERS => '0');
578 578
579 579 error_wfp <= "000";
580 580 error_wfp_addr <= "000";
581 581
582 582 sample_counter <= (0,0,0);
583 583
584 584 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
585 585 error_wfp <= "000";
586 586 error_wfp_addr <= "000";
587 587 -------------------------------------------------------------------------
588 588 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
589 589 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
590 590
591 591 addr_pre_f0 <= address(13 DOWNTO 0);
592 592 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
593 593 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
594 594 error_wfp_addr(0) <= '1';
595 595 END IF;
596 596 END IF;
597 597
598 598 data_pre_f0 <= data;
599 599 CASE data_pre_f0 IS
600 600 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
601 601 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
602 602 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
603 603 WHEN OTHERS => error_wfp(0) <= '1';
604 604 END CASE;
605 605
606 606
607 607 END IF;
608 608 -------------------------------------------------------------------------
609 609 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
610 610 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
611 611
612 612 addr_pre_f1 <= address(13 DOWNTO 0);
613 613 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
614 614 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
615 615 error_wfp_addr(1) <= '1';
616 616 END IF;
617 617 END IF;
618 618
619 619 data_pre_f1 <= data;
620 620 CASE data_pre_f1 IS
621 621 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
622 622 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
623 623 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
624 624 WHEN OTHERS => error_wfp(1) <= '1';
625 625 END CASE;
626 626
627 627 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
628 628 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
629 629 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
630 630
631 631 END IF;
632 632 -------------------------------------------------------------------------
633 633 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
634 634 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
635 635
636 636 addr_pre_f2 <= address(13 DOWNTO 0);
637 637 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
638 638 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
639 639 error_wfp_addr(2) <= '1';
640 640 END IF;
641 641 END IF;
642 642
643 643 data_pre_f2 <= data;
644 644 CASE data_pre_f2 IS
645 645 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
646 646 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
647 647 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
648 648 WHEN OTHERS => error_wfp(2) <= '1';
649 649 END CASE;
650 650
651 651 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
652 652 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
653 653 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
654 654
655 655 END IF;
656 656 END IF;
657 657 END PROCESS;
658 658 -----------------------------------------------------------------------------
659 659 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
660 660
661 661 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
662 662 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
663 663 sr0 : sram
664 664 GENERIC MAP (
665 665 index => i,
666 666 abits => sramdepth,
667 667 fname => sramfile)
668 668 PORT MAP (
669 669 address,
670 670 data(31-i*8 DOWNTO 24-i*8),
671 671 ramsn(k),
672 672 nSRAM_W,
673 673 nSRAM_G
674 674 );
675 675 END GENERATE;
676 676 END GENERATE;
677 677
678 678 END beh;
679 679
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