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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
31 USE gaisler.sim.ALL;
32 USE gaisler.memctrl.ALL;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
38 USE esa.memoryctrl.ALL;
39 LIBRARY lpp;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 USE lpp.iir_filter.ALL;
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 USE lpp.lpp_bootloader_pkg.ALL;
48 USE lpp.lpp_bootloader_pkg.ALL;
49
49
50 --library proasic3l;
50 --library proasic3l;
51 --use proasic3l.all;
51 --use proasic3l.all;
52
52
53 ENTITY LFR_EQM IS
53 ENTITY LFR_EQM IS
54 GENERIC (
54 GENERIC (
55 Mem_use : INTEGER := use_RAM;
55 Mem_use : INTEGER := use_RAM;
56 USE_BOOTLOADER : INTEGER := 0;
56 USE_BOOTLOADER : INTEGER := 0;
57 USE_ADCDRIVER : INTEGER := 0;
57 USE_ADCDRIVER : INTEGER := 1;
58 tech : INTEGER := apa3e;
58 tech : INTEGER := apa3e;
59 tech_leon : INTEGER := apa3e;
59 tech_leon : INTEGER := apa3e;
60 DEBUG_FORCE_DATA_DMA : INTEGER := 1;
60 DEBUG_FORCE_DATA_DMA : INTEGER := 1;
61 USE_DEBUG_VECTOR : INTEGER := 1
61 USE_DEBUG_VECTOR : INTEGER := 1
62 );
62 );
63
63
64 PORT (
64 PORT (
65 clk50MHz : IN STD_ULOGIC;
65 clk50MHz : IN STD_ULOGIC;
66 clk49_152MHz : IN STD_ULOGIC;
66 clk49_152MHz : IN STD_ULOGIC;
67 reset : IN STD_ULOGIC;
67 reset : IN STD_ULOGIC;
68
68
69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70
70
71 -- TAG --------------------------------------------------------------------
71 -- TAG --------------------------------------------------------------------
72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 -- UART APB ---------------------------------------------------------------
74 -- UART APB ---------------------------------------------------------------
75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 -- RAM --------------------------------------------------------------------
77 -- RAM --------------------------------------------------------------------
78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80
80
81 nSRAM_MBE : INOUT STD_LOGIC; -- new
81 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 nSRAM_E1 : OUT STD_LOGIC; -- new
82 nSRAM_E1 : OUT STD_LOGIC; -- new
83 nSRAM_E2 : OUT STD_LOGIC; -- new
83 nSRAM_E2 : OUT STD_LOGIC; -- new
84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 nSRAM_W : OUT STD_LOGIC; -- new
85 nSRAM_W : OUT STD_LOGIC; -- new
86 nSRAM_G : OUT STD_LOGIC; -- new
86 nSRAM_G : OUT STD_LOGIC; -- new
87 nSRAM_BUSY : IN STD_LOGIC; -- new
87 nSRAM_BUSY : IN STD_LOGIC; -- new
88 -- SPW --------------------------------------------------------------------
88 -- SPW --------------------------------------------------------------------
89 spw1_en : OUT STD_LOGIC; -- new
89 spw1_en : OUT STD_LOGIC; -- new
90 spw1_din : IN STD_LOGIC;
90 spw1_din : IN STD_LOGIC;
91 spw1_sin : IN STD_LOGIC;
91 spw1_sin : IN STD_LOGIC;
92 spw1_dout : OUT STD_LOGIC;
92 spw1_dout : OUT STD_LOGIC;
93 spw1_sout : OUT STD_LOGIC;
93 spw1_sout : OUT STD_LOGIC;
94 spw2_en : OUT STD_LOGIC; -- new
94 spw2_en : OUT STD_LOGIC; -- new
95 spw2_din : IN STD_LOGIC;
95 spw2_din : IN STD_LOGIC;
96 spw2_sin : IN STD_LOGIC;
96 spw2_sin : IN STD_LOGIC;
97 spw2_dout : OUT STD_LOGIC;
97 spw2_dout : OUT STD_LOGIC;
98 spw2_sout : OUT STD_LOGIC;
98 spw2_sout : OUT STD_LOGIC;
99 -- ADC --------------------------------------------------------------------
99 -- ADC --------------------------------------------------------------------
100 bias_fail_sw : OUT STD_LOGIC;
100 bias_fail_sw : OUT STD_LOGIC;
101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 ADC_smpclk : OUT STD_LOGIC;
102 ADC_smpclk : OUT STD_LOGIC;
103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 -- DAC --------------------------------------------------------------------
104 -- DAC --------------------------------------------------------------------
105 DAC_SDO : OUT STD_LOGIC;
105 DAC_SDO : OUT STD_LOGIC;
106 DAC_SCK : OUT STD_LOGIC;
106 DAC_SCK : OUT STD_LOGIC;
107 DAC_SYNC : OUT STD_LOGIC;
107 DAC_SYNC : OUT STD_LOGIC;
108 DAC_CAL_EN : OUT STD_LOGIC;
108 DAC_CAL_EN : OUT STD_LOGIC;
109 -- HK ---------------------------------------------------------------------
109 -- HK ---------------------------------------------------------------------
110 HK_smpclk : OUT STD_LOGIC;
110 HK_smpclk : OUT STD_LOGIC;
111 ADC_OEB_bar_HK : OUT STD_LOGIC;
111 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
113 ---------------------------------------------------------------------------
113 ---------------------------------------------------------------------------
114 -- TAG8 : OUT STD_LOGIC
114 -- TAG8 : OUT STD_LOGIC
115 );
115 );
116
116
117 END LFR_EQM;
117 END LFR_EQM;
118
118
119
119
120 ARCHITECTURE beh OF LFR_EQM IS
120 ARCHITECTURE beh OF LFR_EQM IS
121
121
122 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127
127
128 -- CONSTANTS
128 -- CONSTANTS
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133
133
134 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbi_ext : apb_slv_in_type;
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140
140
141 -- Spacewire signals
141 -- Spacewire signals
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 SIGNAL spw_rxtxclk : STD_ULOGIC;
145 SIGNAL spw_rxtxclk : STD_ULOGIC;
146 SIGNAL spw_rxclkn : STD_ULOGIC;
146 SIGNAL spw_rxclkn : STD_ULOGIC;
147 SIGNAL spw_clk : STD_LOGIC;
147 SIGNAL spw_clk : STD_LOGIC;
148 SIGNAL swni : grspw_in_type;
148 SIGNAL swni : grspw_in_type;
149 SIGNAL swno : grspw_out_type;
149 SIGNAL swno : grspw_out_type;
150
150
151 --GPIO
151 --GPIO
152 SIGNAL gpioi : gpio_in_type;
152 SIGNAL gpioi : gpio_in_type;
153 SIGNAL gpioo : gpio_out_type;
153 SIGNAL gpioo : gpio_out_type;
154
154
155 -- AD Converter ADS7886
155 -- AD Converter ADS7886
156 SIGNAL sample : Samples14v(8 DOWNTO 0);
156 SIGNAL sample : Samples14v(8 DOWNTO 0);
157 SIGNAL sample_s : Samples(8 DOWNTO 0);
157 SIGNAL sample_s : Samples(8 DOWNTO 0);
158 SIGNAL sample_val : STD_LOGIC;
158 SIGNAL sample_val : STD_LOGIC;
159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
160
160
161 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
163
163
164 -----------------------------------------------------------------------------
164 -----------------------------------------------------------------------------
165 SIGNAL rstn_25 : STD_LOGIC;
165 SIGNAL rstn_25 : STD_LOGIC;
166 SIGNAL rstn_24 : STD_LOGIC;
166 SIGNAL rstn_24 : STD_LOGIC;
167
167
168 SIGNAL LFR_soft_rstn : STD_LOGIC;
168 SIGNAL LFR_soft_rstn : STD_LOGIC;
169 SIGNAL LFR_rstn : STD_LOGIC;
169 SIGNAL LFR_rstn : STD_LOGIC;
170
170
171 SIGNAL ADC_smpclk_s : STD_LOGIC;
171 SIGNAL ADC_smpclk_s : STD_LOGIC;
172
172
173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
174
174
175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
176 SIGNAL clk_25_int : STD_LOGIC := '0';
176 SIGNAL clk_25_int : STD_LOGIC := '0';
177
177
178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
179
179
180 SIGNAL rstn_50 : STD_LOGIC;
180 SIGNAL rstn_50 : STD_LOGIC;
181 SIGNAL clk_lock : STD_LOGIC;
181 SIGNAL clk_lock : STD_LOGIC;
182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
184
184
185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 SIGNAL ahbrxd: STD_LOGIC;
186 SIGNAL ahbrxd: STD_LOGIC;
187 SIGNAL ahbtxd: STD_LOGIC;
187 SIGNAL ahbtxd: STD_LOGIC;
188 SIGNAL urxd1 : STD_LOGIC;
188 SIGNAL urxd1 : STD_LOGIC;
189 SIGNAL utxd1 : STD_LOGIC;
189 SIGNAL utxd1 : STD_LOGIC;
190 BEGIN -- beh
190 BEGIN -- beh
191
191
192 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
193 -- CLK_LOCK
193 -- CLK_LOCK
194 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
196
196
197 PROCESS (clk50MHz_int, rstn_50)
197 PROCESS (clk50MHz_int, rstn_50)
198 BEGIN -- PROCESS
198 BEGIN -- PROCESS
199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
200 clk_lock <= '0';
200 clk_lock <= '0';
201 clk_busy_counter <= (OTHERS => '0');
201 clk_busy_counter <= (OTHERS => '0');
202 nSRAM_BUSY_reg <= '0';
202 nSRAM_BUSY_reg <= '0';
203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
204 nSRAM_BUSY_reg <= nSRAM_BUSY;
204 nSRAM_BUSY_reg <= nSRAM_BUSY;
205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
206 IF clk_busy_counter = "1111" THEN
206 IF clk_busy_counter = "1111" THEN
207 clk_lock <= '1';
207 clk_lock <= '1';
208 ELSE
208 ELSE
209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
210 END IF;
210 END IF;
211 END IF;
211 END IF;
212 END IF;
212 END IF;
213 END PROCESS;
213 END PROCESS;
214
214
215 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
216 -- CLK
216 -- CLK
217 -----------------------------------------------------------------------------
217 -----------------------------------------------------------------------------
218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
220
220
221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
222 clk50MHz_int <= clk50MHz;
222 clk50MHz_int <= clk50MHz;
223
223
224 PROCESS(clk50MHz_int)
224 PROCESS(clk50MHz_int)
225 BEGIN
225 BEGIN
226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
227 --clk_25_int <= NOT clk_25_int;
227 --clk_25_int <= NOT clk_25_int;
228 clk_25 <= NOT clk_25;
228 clk_25 <= NOT clk_25;
229 END IF;
229 END IF;
230 END PROCESS;
230 END PROCESS;
231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
232
232
233 PROCESS(clk49_152MHz)
233 PROCESS(clk49_152MHz)
234 BEGIN
234 BEGIN
235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
236 clk_24 <= NOT clk_24;
236 clk_24 <= NOT clk_24;
237 END IF;
237 END IF;
238 END PROCESS;
238 END PROCESS;
239
239
240 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
241 --
241 --
242 leon3_soc_1 : leon3_soc
242 leon3_soc_1 : leon3_soc
243 GENERIC MAP (
243 GENERIC MAP (
244 fabtech => tech_leon,
244 fabtech => tech_leon,
245 memtech => tech_leon,
245 memtech => tech_leon,
246 padtech => inferred,
246 padtech => inferred,
247 clktech => inferred,
247 clktech => inferred,
248 disas => 0,
248 disas => 0,
249 dbguart => 0,
249 dbguart => 0,
250 pclow => 2,
250 pclow => 2,
251 clk_freq => 25000,
251 clk_freq => 25000,
252 IS_RADHARD => 0,
252 IS_RADHARD => 0,
253 NB_CPU => 1,
253 NB_CPU => 1,
254 ENABLE_FPU => 1,
254 ENABLE_FPU => 1,
255 FPU_NETLIST => 0,
255 FPU_NETLIST => 0,
256 ENABLE_DSU => 1,
256 ENABLE_DSU => 1,
257 ENABLE_AHB_UART => 1,
257 ENABLE_AHB_UART => 1,
258 ENABLE_APB_UART => 1,
258 ENABLE_APB_UART => 1,
259 ENABLE_IRQMP => 1,
259 ENABLE_IRQMP => 1,
260 ENABLE_GPT => 1,
260 ENABLE_GPT => 1,
261 NB_AHB_MASTER => NB_AHB_MASTER,
261 NB_AHB_MASTER => NB_AHB_MASTER,
262 NB_AHB_SLAVE => NB_AHB_SLAVE,
262 NB_AHB_SLAVE => NB_AHB_SLAVE,
263 NB_APB_SLAVE => NB_APB_SLAVE,
263 NB_APB_SLAVE => NB_APB_SLAVE,
264 ADDRESS_SIZE => 19,
264 ADDRESS_SIZE => 19,
265 USES_IAP_MEMCTRLR => 1,
265 USES_IAP_MEMCTRLR => 1,
266 BYPASS_EDAC_MEMCTRLR => '0',
266 BYPASS_EDAC_MEMCTRLR => '0',
267 SRBANKSZ => 8)
267 SRBANKSZ => 8)
268 PORT MAP (
268 PORT MAP (
269 clk => clk_25,
269 clk => clk_25,
270 reset => rstn_25,
270 reset => rstn_25,
271 errorn => OPEN,
271 errorn => OPEN,
272
272
273 ahbrxd => ahbrxd, -- INPUT
273 ahbrxd => ahbrxd, -- INPUT
274 ahbtxd => ahbtxd, -- OUTPUT
274 ahbtxd => ahbtxd, -- OUTPUT
275 urxd1 => urxd1, -- INPUT
275 urxd1 => urxd1, -- INPUT
276 utxd1 => utxd1, -- OUTPUT
276 utxd1 => utxd1, -- OUTPUT
277
277
278 address => address,
278 address => address,
279 data => data,
279 data => data,
280 nSRAM_BE0 => OPEN,
280 nSRAM_BE0 => OPEN,
281 nSRAM_BE1 => OPEN,
281 nSRAM_BE1 => OPEN,
282 nSRAM_BE2 => OPEN,
282 nSRAM_BE2 => OPEN,
283 nSRAM_BE3 => OPEN,
283 nSRAM_BE3 => OPEN,
284 nSRAM_WE => nSRAM_W,
284 nSRAM_WE => nSRAM_W,
285 nSRAM_CE => nSRAM_CE,
285 nSRAM_CE => nSRAM_CE,
286 nSRAM_OE => nSRAM_G,
286 nSRAM_OE => nSRAM_G,
287 nSRAM_READY => nSRAM_BUSY,
287 nSRAM_READY => nSRAM_BUSY,
288 SRAM_MBE => nSRAM_MBE,
288 SRAM_MBE => nSRAM_MBE,
289
289
290 apbi_ext => apbi_ext,
290 apbi_ext => apbi_ext,
291 apbo_ext => apbo_ext,
291 apbo_ext => apbo_ext,
292 ahbi_s_ext => ahbi_s_ext,
292 ahbi_s_ext => ahbi_s_ext,
293 ahbo_s_ext => ahbo_s_ext,
293 ahbo_s_ext => ahbo_s_ext,
294 ahbi_m_ext => ahbi_m_ext,
294 ahbi_m_ext => ahbi_m_ext,
295 ahbo_m_ext => ahbo_m_ext);
295 ahbo_m_ext => ahbo_m_ext);
296
296
297
297
298 nSRAM_E1 <= nSRAM_CE(0);
298 nSRAM_E1 <= nSRAM_CE(0);
299 nSRAM_E2 <= nSRAM_CE(1);
299 nSRAM_E2 <= nSRAM_CE(1);
300
300
301 -------------------------------------------------------------------------------
301 -------------------------------------------------------------------------------
302 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
302 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
303 -------------------------------------------------------------------------------
303 -------------------------------------------------------------------------------
304 apb_lfr_management_1 : apb_lfr_management
304 apb_lfr_management_1 : apb_lfr_management
305 GENERIC MAP (
305 GENERIC MAP (
306 tech => tech,
306 tech => tech,
307 pindex => 6,
307 pindex => 6,
308 paddr => 6,
308 paddr => 6,
309 pmask => 16#fff#,
309 pmask => 16#fff#,
310 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
310 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
311 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
311 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
312 PORT MAP (
312 PORT MAP (
313 clk25MHz => clk_25,
313 clk25MHz => clk_25,
314 resetn_25MHz => rstn_25, -- TODO
314 resetn_25MHz => rstn_25, -- TODO
315 --clk24_576MHz => clk_24, -- 49.152MHz/2
315 --clk24_576MHz => clk_24, -- 49.152MHz/2
316 --resetn_24_576MHz => rstn_24, -- TODO
316 --resetn_24_576MHz => rstn_24, -- TODO
317
317
318 grspw_tick => swno.tickout,
318 grspw_tick => swno.tickout,
319 apbi => apbi_ext,
319 apbi => apbi_ext,
320 apbo => apbo_ext(6),
320 apbo => apbo_ext(6),
321
321
322 HK_sample => sample_s(8),
322 HK_sample => sample_s(8),
323 HK_val => sample_val,
323 HK_val => sample_val,
324 HK_sel => HK_SEL,
324 HK_sel => HK_SEL,
325
325
326 DAC_SDO => DAC_SDO,
326 DAC_SDO => DAC_SDO,
327 DAC_SCK => DAC_SCK,
327 DAC_SCK => DAC_SCK,
328 DAC_SYNC => DAC_SYNC,
328 DAC_SYNC => DAC_SYNC,
329 DAC_CAL_EN => DAC_CAL_EN,
329 DAC_CAL_EN => DAC_CAL_EN,
330
330
331 coarse_time => coarse_time,
331 coarse_time => coarse_time,
332 fine_time => fine_time,
332 fine_time => fine_time,
333 LFR_soft_rstn => LFR_soft_rstn
333 LFR_soft_rstn => LFR_soft_rstn
334 );
334 );
335
335
336 -----------------------------------------------------------------------
336 -----------------------------------------------------------------------
337 --- SpaceWire --------------------------------------------------------
337 --- SpaceWire --------------------------------------------------------
338 -----------------------------------------------------------------------
338 -----------------------------------------------------------------------
339
339
340 ------------------------------------------------------------------------------
340 ------------------------------------------------------------------------------
341 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
341 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
342 ------------------------------------------------------------------------------
342 ------------------------------------------------------------------------------
343 spw1_en <= '1';
343 spw1_en <= '1';
344 spw2_en <= '1';
344 spw2_en <= '1';
345 ------------------------------------------------------------------------------
345 ------------------------------------------------------------------------------
346 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
346 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
347 ------------------------------------------------------------------------------
347 ------------------------------------------------------------------------------
348
348
349 --spw_clk <= clk50MHz;
349 --spw_clk <= clk50MHz;
350 --spw_rxtxclk <= spw_clk;
350 --spw_rxtxclk <= spw_clk;
351 --spw_rxclkn <= NOT spw_rxtxclk;
351 --spw_rxclkn <= NOT spw_rxtxclk;
352
352
353 -- PADS for SPW1
353 -- PADS for SPW1
354 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
354 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
355 PORT MAP (spw1_din, dtmp(0));
355 PORT MAP (spw1_din, dtmp(0));
356 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
356 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
357 PORT MAP (spw1_sin, stmp(0));
357 PORT MAP (spw1_sin, stmp(0));
358 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
358 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
359 PORT MAP (spw1_dout, swno.d(0));
359 PORT MAP (spw1_dout, swno.d(0));
360 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
360 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
361 PORT MAP (spw1_sout, swno.s(0));
361 PORT MAP (spw1_sout, swno.s(0));
362 -- PADS FOR SPW2
362 -- PADS FOR SPW2
363 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
363 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
364 PORT MAP (spw2_din, dtmp(1));
364 PORT MAP (spw2_din, dtmp(1));
365 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
365 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
366 PORT MAP (spw2_sin, stmp(1));
366 PORT MAP (spw2_sin, stmp(1));
367 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
367 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
368 PORT MAP (spw2_dout, swno.d(1));
368 PORT MAP (spw2_dout, swno.d(1));
369 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
369 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
370 PORT MAP (spw2_sout, swno.s(1));
370 PORT MAP (spw2_sout, swno.s(1));
371
371
372 -- GRSPW PHY
372 -- GRSPW PHY
373 --spw1_input: if CFG_SPW_GRSPW = 1 generate
373 --spw1_input: if CFG_SPW_GRSPW = 1 generate
374 spw_inputloop : FOR j IN 0 TO 1 GENERATE
374 spw_inputloop : FOR j IN 0 TO 1 GENERATE
375 spw_phy0 : grspw_phy
375 spw_phy0 : grspw_phy
376 GENERIC MAP(
376 GENERIC MAP(
377 tech => tech_leon,
377 tech => tech_leon,
378 rxclkbuftype => 1,
378 rxclkbuftype => 1,
379 scantest => 0)
379 scantest => 0)
380 PORT MAP(
380 PORT MAP(
381 rxrst => swno.rxrst,
381 rxrst => swno.rxrst,
382 di => dtmp(j),
382 di => dtmp(j),
383 si => stmp(j),
383 si => stmp(j),
384 rxclko => spw_rxclk(j),
384 rxclko => spw_rxclk(j),
385 do => swni.d(j),
385 do => swni.d(j),
386 ndo => swni.nd(j*5+4 DOWNTO j*5),
386 ndo => swni.nd(j*5+4 DOWNTO j*5),
387 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
387 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
388 END GENERATE spw_inputloop;
388 END GENERATE spw_inputloop;
389
389
390 -- SPW core
390 -- SPW core
391 sw0 : grspwm GENERIC MAP(
391 sw0 : grspwm GENERIC MAP(
392 tech => tech_leon,
392 tech => tech_leon,
393 hindex => 1,
393 hindex => 1,
394 pindex => 5,
394 pindex => 5,
395 paddr => 5,
395 paddr => 5,
396 pirq => 11,
396 pirq => 11,
397 sysfreq => 25000, -- CPU_FREQ
397 sysfreq => 25000, -- CPU_FREQ
398 rmap => 1,
398 rmap => 1,
399 rmapcrc => 1,
399 rmapcrc => 1,
400 fifosize1 => 16,
400 fifosize1 => 16,
401 fifosize2 => 16,
401 fifosize2 => 16,
402 rxclkbuftype => 1,
402 rxclkbuftype => 1,
403 rxunaligned => 0,
403 rxunaligned => 0,
404 rmapbufs => 4,
404 rmapbufs => 4,
405 ft => 0,
405 ft => 0,
406 netlist => 0,
406 netlist => 0,
407 ports => 2,
407 ports => 2,
408 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
408 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
409 memtech => tech_leon,
409 memtech => tech_leon,
410 destkey => 2,
410 destkey => 2,
411 spwcore => 1
411 spwcore => 1
412 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
412 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
413 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
413 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
414 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
414 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
415 )
415 )
416 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
416 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
417 spw_rxclk(1),
417 spw_rxclk(1),
418 clk50MHz_int,
418 clk50MHz_int,
419 clk50MHz_int,
419 clk50MHz_int,
420 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
420 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
421 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
421 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
422 swni, swno);
422 swni, swno);
423
423
424 swni.tickin <= '0';
424 swni.tickin <= '0';
425 swni.rmapen <= '1';
425 swni.rmapen <= '1';
426 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
426 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
427 swni.tickinraw <= '0';
427 swni.tickinraw <= '0';
428 swni.timein <= (OTHERS => '0');
428 swni.timein <= (OTHERS => '0');
429 swni.dcrstval <= (OTHERS => '0');
429 swni.dcrstval <= (OTHERS => '0');
430 swni.timerrstval <= (OTHERS => '0');
430 swni.timerrstval <= (OTHERS => '0');
431
431
432 -------------------------------------------------------------------------------
432 -------------------------------------------------------------------------------
433 -- LFR ------------------------------------------------------------------------
433 -- LFR ------------------------------------------------------------------------
434 -------------------------------------------------------------------------------
434 -------------------------------------------------------------------------------
435 LFR_rstn <= LFR_soft_rstn AND rstn_25;
435 LFR_rstn <= LFR_soft_rstn AND rstn_25;
436
436
437 lpp_lfr_1 : lpp_lfr
437 lpp_lfr_1 : lpp_lfr
438 GENERIC MAP (
438 GENERIC MAP (
439 Mem_use => Mem_use,
439 Mem_use => Mem_use,
440 tech => tech,
440 tech => tech,
441 nb_data_by_buffer_size => 32,
441 nb_data_by_buffer_size => 32,
442 --nb_word_by_buffer_size => 30,
442 --nb_word_by_buffer_size => 30,
443 nb_snapshot_param_size => 32,
443 nb_snapshot_param_size => 32,
444 delta_vector_size => 32,
444 delta_vector_size => 32,
445 delta_vector_size_f0_2 => 7, -- log2(96)
445 delta_vector_size_f0_2 => 7, -- log2(96)
446 pindex => 15,
446 pindex => 15,
447 paddr => 15,
447 paddr => 15,
448 pmask => 16#fff#,
448 pmask => 16#fff#,
449 pirq_ms => 6,
449 pirq_ms => 6,
450 pirq_wfp => 14,
450 pirq_wfp => 14,
451 hindex => 2,
451 hindex => 2,
452 top_lfr_version => X"020148", -- aa.bb.cc version
452 top_lfr_version => X"020148", -- aa.bb.cc version
453 -- AA : BOARD NUMBER
453 -- AA : BOARD NUMBER
454 -- 0 => MINI_LFR
454 -- 0 => MINI_LFR
455 -- 1 => EM
455 -- 1 => EM
456 -- 2 => EQM (with A3PE3000)
456 -- 2 => EQM (with A3PE3000)
457 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
457 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
458 PORT MAP (
458 PORT MAP (
459 clk => clk_25,
459 clk => clk_25,
460 rstn => LFR_rstn,
460 rstn => LFR_rstn,
461 sample_B => sample_s(2 DOWNTO 0),
461 sample_B => sample_s(2 DOWNTO 0),
462 sample_E => sample_s(7 DOWNTO 3),
462 sample_E => sample_s(7 DOWNTO 3),
463 sample_val => sample_val,
463 sample_val => sample_val,
464 apbi => apbi_ext,
464 apbi => apbi_ext,
465 apbo => apbo_ext(15),
465 apbo => apbo_ext(15),
466 ahbi => ahbi_m_ext,
466 ahbi => ahbi_m_ext,
467 ahbo => ahbo_m_ext(2),
467 ahbo => ahbo_m_ext(2),
468 coarse_time => coarse_time,
468 coarse_time => coarse_time,
469 fine_time => fine_time,
469 fine_time => fine_time,
470 data_shaping_BW => bias_fail_sw,
470 data_shaping_BW => bias_fail_sw,
471 debug_vector => debug_vector,
471 debug_vector => debug_vector,
472 debug_vector_ms => OPEN); --,
472 debug_vector_ms => OPEN); --,
473 --observation_vector_0 => OPEN,
473 --observation_vector_0 => OPEN,
474 --observation_vector_1 => OPEN,
474 --observation_vector_1 => OPEN,
475 --observation_reg => observation_reg);
475 --observation_reg => observation_reg);
476
476
477
477
478 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
478 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
479 sample_s(I) <= sample(I) & '0' & '0';
479 sample_s(I) <= sample(I) & '0' & '0';
480 END GENERATE all_sample;
480 END GENERATE all_sample;
481 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
481 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
482
482
483 -----------------------------------------------------------------------------
483 -----------------------------------------------------------------------------
484 --
484 --
485 -----------------------------------------------------------------------------
485 -----------------------------------------------------------------------------
486 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
486 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
487 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
487 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
488 GENERIC MAP (
488 GENERIC MAP (
489 ChanelCount => 9,
489 ChanelCount => 9,
490 ncycle_cnv_high => 13,
490 ncycle_cnv_high => 13,
491 ncycle_cnv => 25,
491 ncycle_cnv => 25,
492 FILTER_ENABLED => 16#FF#)
492 FILTER_ENABLED => 16#FF#)
493 PORT MAP (
493 PORT MAP (
494 cnv_clk => clk_24,
494 cnv_clk => clk_24,
495 cnv_rstn => rstn_24,
495 cnv_rstn => rstn_24,
496 cnv => ADC_smpclk_s,
496 cnv => ADC_smpclk_s,
497 clk => clk_25,
497 clk => clk_25,
498 rstn => rstn_25,
498 rstn => rstn_25,
499 ADC_data => ADC_data,
499 ADC_data => ADC_data,
500 ADC_nOE => ADC_OEB_bar_CH_s,
500 ADC_nOE => ADC_OEB_bar_CH_s,
501 sample => sample,
501 sample => sample,
502 sample_val => sample_val);
502 sample_val => sample_val);
503
503
504 END GENERATE USE_ADCDRIVER_true;
504 END GENERATE USE_ADCDRIVER_true;
505
505
506 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
506 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
507 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
507 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
508 GENERIC MAP (
508 GENERIC MAP (
509 ChanelCount => 9,
509 ChanelCount => 9,
510 ncycle_cnv_high => 13,
510 ncycle_cnv_high => 13,
511 ncycle_cnv => 25,
511 ncycle_cnv => 25,
512 FILTER_ENABLED => 16#FF#)
512 FILTER_ENABLED => 16#FF#)
513 PORT MAP (
513 PORT MAP (
514 cnv_clk => clk_24,
514 cnv_clk => clk_24,
515 cnv_rstn => rstn_24,
515 cnv_rstn => rstn_24,
516 cnv => ADC_smpclk_s,
516 cnv => ADC_smpclk_s,
517 clk => clk_25,
517 clk => clk_25,
518 rstn => rstn_25,
518 rstn => rstn_25,
519 ADC_data => ADC_data,
519 ADC_data => ADC_data,
520 ADC_nOE => OPEN,
520 ADC_nOE => OPEN,
521 sample => OPEN,
521 sample => OPEN,
522 sample_val => sample_val);
522 sample_val => sample_val);
523
523
524 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
524 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
525
525
526 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
526 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
527 ramp_generator_1: ramp_generator
527 ramp_generator_1: ramp_generator
528 GENERIC MAP (
528 GENERIC MAP (
529 DATA_SIZE => 14,
529 DATA_SIZE => 14,
530 VALUE_UNSIGNED_INIT => 2**I,
530 VALUE_UNSIGNED_INIT => 2**I,
531 VALUE_UNSIGNED_INCR => 0,
531 VALUE_UNSIGNED_INCR => 0,
532 VALUE_UNSIGNED_MASK => 16#3FFF#)
532 VALUE_UNSIGNED_MASK => 16#3FFF#)
533 PORT MAP (
533 PORT MAP (
534 clk => clk_25,
534 clk => clk_25,
535 rstn => rstn_25,
535 rstn => rstn_25,
536 new_data => sample_val,
536 new_data => sample_val,
537 output_data => sample(I) );
537 output_data => sample(I) );
538 END GENERATE all_sample;
538 END GENERATE all_sample;
539
539
540
540
541 END GENERATE USE_ADCDRIVER_false;
541 END GENERATE USE_ADCDRIVER_false;
542
542
543
543
544
544
545
545
546 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
546 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
547
547
548 ADC_smpclk <= ADC_smpclk_s;
548 ADC_smpclk <= ADC_smpclk_s;
549 HK_smpclk <= ADC_smpclk_s;
549 HK_smpclk <= ADC_smpclk_s;
550
550
551
551
552 -----------------------------------------------------------------------------
552 -----------------------------------------------------------------------------
553 -- HK
553 -- HK
554 -----------------------------------------------------------------------------
554 -----------------------------------------------------------------------------
555 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
555 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
556
556
557 -----------------------------------------------------------------------------
557 -----------------------------------------------------------------------------
558 --
558 --
559 -----------------------------------------------------------------------------
559 -----------------------------------------------------------------------------
560 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
560 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
561 lpp_bootloader_1: lpp_bootloader
561 lpp_bootloader_1: lpp_bootloader
562 GENERIC MAP (
562 GENERIC MAP (
563 pindex => 13,
563 pindex => 13,
564 paddr => 13,
564 paddr => 13,
565 pmask => 16#fff#,
565 pmask => 16#fff#,
566 hindex => 3,
566 hindex => 3,
567 haddr => 0,
567 haddr => 0,
568 hmask => 16#fff#)
568 hmask => 16#fff#)
569 PORT MAP (
569 PORT MAP (
570 HCLK => clk_25,
570 HCLK => clk_25,
571 HRESETn => rstn_25,
571 HRESETn => rstn_25,
572 apbi => apbi_ext,
572 apbi => apbi_ext,
573 apbo => apbo_ext(13),
573 apbo => apbo_ext(13),
574 ahbsi => ahbi_s_ext,
574 ahbsi => ahbi_s_ext,
575 ahbso => ahbo_s_ext(3));
575 ahbso => ahbo_s_ext(3));
576 END GENERATE inst_bootloader;
576 END GENERATE inst_bootloader;
577
577
578 -----------------------------------------------------------------------------
578 -----------------------------------------------------------------------------
579 --
579 --
580 -----------------------------------------------------------------------------
580 -----------------------------------------------------------------------------
581 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
581 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
582 PROCESS (clk_25, rstn_25)
582 PROCESS (clk_25, rstn_25)
583 BEGIN -- PROCESS
583 BEGIN -- PROCESS
584 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
584 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
585 TAG <= (OTHERS => '0');
585 TAG <= (OTHERS => '0');
586 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
586 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
587 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
587 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
588 END IF;
588 END IF;
589 END PROCESS;
589 END PROCESS;
590
590
591
591
592 END GENERATE USE_DEBUG_VECTOR_IF;
592 END GENERATE USE_DEBUG_VECTOR_IF;
593
593
594 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
594 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
595 ahbrxd <= TAG(1);
595 ahbrxd <= TAG(1);
596 TAG(3) <= ahbtxd;
596 TAG(3) <= ahbtxd;
597 urxd1 <= TAG(2);
597 urxd1 <= TAG(2);
598 TAG(4) <= utxd1;
598 TAG(4) <= utxd1;
599 TAG(8) <= nSRAM_BUSY;
599 TAG(8) <= nSRAM_BUSY;
600 END GENERATE USE_DEBUG_VECTOR_IF2;
600 END GENERATE USE_DEBUG_VECTOR_IF2;
601
601
602 END beh;
602 END beh;
Show file before | Show file after | Hide comments
@@ -1,679 +1,679
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
26
27 LIBRARY techmap;
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
28 USE techmap.gencomp.ALL;
29
29
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_sim_pkg.ALL;
31 USE lpp.lpp_sim_pkg.ALL;
32 USE lpp.lpp_lfr_sim_pkg.ALL;
32 USE lpp.lpp_lfr_sim_pkg.ALL;
33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
35 USE lpp.iir_filter.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.FILTERcfg.ALL;
36 USE lpp.FILTERcfg.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_waveform_pkg.ALL;
38 USE lpp.lpp_waveform_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_top_lfr_pkg.ALL;
40 USE lpp.lpp_top_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.general_purpose.ALL;
42 USE lpp.general_purpose.ALL;
43 --LIBRARY lpp;
43 --LIBRARY lpp;
44 USE lpp.lpp_ad_conv.ALL;
44 USE lpp.lpp_ad_conv.ALL;
45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
47
47
48 --USE work.debug.ALL;
48 --USE work.debug.ALL;
49
49
50 LIBRARY gaisler;
50 LIBRARY gaisler;
51 USE gaisler.libdcom.ALL;
51 USE gaisler.libdcom.ALL;
52 USE gaisler.sim.ALL;
52 USE gaisler.sim.ALL;
53 USE gaisler.memctrl.ALL;
53 USE gaisler.memctrl.ALL;
54 USE gaisler.leon3.ALL;
54 USE gaisler.leon3.ALL;
55 USE gaisler.uart.ALL;
55 USE gaisler.uart.ALL;
56 USE gaisler.misc.ALL;
56 USE gaisler.misc.ALL;
57 USE gaisler.spacewire.ALL;
57 USE gaisler.spacewire.ALL;
58
58
59 ENTITY TB IS
59 ENTITY TB IS
60
60
61 END TB;
61 END TB;
62
62
63 ARCHITECTURE beh OF TB IS
63 ARCHITECTURE beh OF TB IS
64 -- CONSTANT sramfile : STRING := "prom.srec";
64 CONSTANT sramfile : STRING := "prom.srec";
65 CONSTANT sramfile : STRING;
65 -- CONSTANT sramfile : STRING;
66
66
67 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
67 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
68
68
69 COMPONENT LFR_EQM
69 COMPONENT LFR_EQM
70 GENERIC (
70 GENERIC (
71 Mem_use : INTEGER;
71 Mem_use : INTEGER;
72 USE_BOOTLOADER : INTEGER;
72 USE_BOOTLOADER : INTEGER;
73 USE_ADCDRIVER : INTEGER;
73 USE_ADCDRIVER : INTEGER;
74 tech : INTEGER;
74 tech : INTEGER;
75 tech_leon : INTEGER;
75 tech_leon : INTEGER;
76 DEBUG_FORCE_DATA_DMA : INTEGER;
76 DEBUG_FORCE_DATA_DMA : INTEGER;
77 USE_DEBUG_VECTOR : INTEGER );
77 USE_DEBUG_VECTOR : INTEGER );
78 PORT (
78 PORT (
79 clk50MHz : IN STD_ULOGIC;
79 clk50MHz : IN STD_ULOGIC;
80 clk49_152MHz : IN STD_ULOGIC;
80 clk49_152MHz : IN STD_ULOGIC;
81 reset : IN STD_ULOGIC;
81 reset : IN STD_ULOGIC;
82 --TAG1 : IN STD_ULOGIC;
82 --TAG1 : IN STD_ULOGIC;
83 --TAG3 : OUT STD_ULOGIC;
83 --TAG3 : OUT STD_ULOGIC;
84 --TAG2 : IN STD_ULOGIC;
84 --TAG2 : IN STD_ULOGIC;
85 --TAG4 : OUT STD_ULOGIC;
85 --TAG4 : OUT STD_ULOGIC;
86 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
86 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
87 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
87 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 nSRAM_MBE : INOUT STD_LOGIC;
89 nSRAM_MBE : INOUT STD_LOGIC;
90 nSRAM_E1 : OUT STD_LOGIC;
90 nSRAM_E1 : OUT STD_LOGIC;
91 nSRAM_E2 : OUT STD_LOGIC;
91 nSRAM_E2 : OUT STD_LOGIC;
92 nSRAM_W : OUT STD_LOGIC;
92 nSRAM_W : OUT STD_LOGIC;
93 nSRAM_G : OUT STD_LOGIC;
93 nSRAM_G : OUT STD_LOGIC;
94 nSRAM_BUSY : IN STD_LOGIC;
94 nSRAM_BUSY : IN STD_LOGIC;
95 spw1_en : OUT STD_LOGIC;
95 spw1_en : OUT STD_LOGIC;
96 spw1_din : IN STD_LOGIC;
96 spw1_din : IN STD_LOGIC;
97 spw1_sin : IN STD_LOGIC;
97 spw1_sin : IN STD_LOGIC;
98 spw1_dout : OUT STD_LOGIC;
98 spw1_dout : OUT STD_LOGIC;
99 spw1_sout : OUT STD_LOGIC;
99 spw1_sout : OUT STD_LOGIC;
100 spw2_en : OUT STD_LOGIC;
100 spw2_en : OUT STD_LOGIC;
101 spw2_din : IN STD_LOGIC;
101 spw2_din : IN STD_LOGIC;
102 spw2_sin : IN STD_LOGIC;
102 spw2_sin : IN STD_LOGIC;
103 spw2_dout : OUT STD_LOGIC;
103 spw2_dout : OUT STD_LOGIC;
104 spw2_sout : OUT STD_LOGIC;
104 spw2_sout : OUT STD_LOGIC;
105 bias_fail_sw : OUT STD_LOGIC;
105 bias_fail_sw : OUT STD_LOGIC;
106 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
106 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
107 ADC_smpclk : OUT STD_LOGIC;
107 ADC_smpclk : OUT STD_LOGIC;
108 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
108 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
109 DAC_SDO : OUT STD_LOGIC;
109 DAC_SDO : OUT STD_LOGIC;
110 DAC_SCK : OUT STD_LOGIC;
110 DAC_SCK : OUT STD_LOGIC;
111 DAC_SYNC : OUT STD_LOGIC;
111 DAC_SYNC : OUT STD_LOGIC;
112 DAC_CAL_EN : OUT STD_LOGIC;
112 DAC_CAL_EN : OUT STD_LOGIC;
113 HK_smpclk : OUT STD_LOGIC;
113 HK_smpclk : OUT STD_LOGIC;
114 ADC_OEB_bar_HK : OUT STD_LOGIC;
114 ADC_OEB_bar_HK : OUT STD_LOGIC;
115 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
115 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
116 END COMPONENT;
116 END COMPONENT;
117
117
118 SIGNAL clk50MHz : STD_ULOGIC := '0';
118 SIGNAL clk50MHz : STD_ULOGIC := '0';
119 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
119 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
120 SIGNAL reset : STD_ULOGIC;
120 SIGNAL reset : STD_ULOGIC;
121 SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1);
121 SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1);
122 --SIGNAL TAG3 : STD_ULOGIC;
122 --SIGNAL TAG3 : STD_ULOGIC;
123 --SIGNAL TAG2 : STD_ULOGIC := '1';
123 --SIGNAL TAG2 : STD_ULOGIC := '1';
124 --SIGNAL TAG4 : STD_ULOGIC;
124 --SIGNAL TAG4 : STD_ULOGIC;
125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL nSRAM_MBE : STD_LOGIC;
127 SIGNAL nSRAM_MBE : STD_LOGIC;
128 SIGNAL nSRAM_E1 : STD_LOGIC;
128 SIGNAL nSRAM_E1 : STD_LOGIC;
129 SIGNAL nSRAM_E2 : STD_LOGIC;
129 SIGNAL nSRAM_E2 : STD_LOGIC;
130 SIGNAL nSRAM_W : STD_LOGIC;
130 SIGNAL nSRAM_W : STD_LOGIC;
131 SIGNAL nSRAM_G : STD_LOGIC;
131 SIGNAL nSRAM_G : STD_LOGIC;
132 SIGNAL nSRAM_BUSY : STD_LOGIC;
132 SIGNAL nSRAM_BUSY : STD_LOGIC;
133 SIGNAL spw1_en : STD_LOGIC;
133 SIGNAL spw1_en : STD_LOGIC;
134 SIGNAL spw1_din : STD_LOGIC := '1';
134 SIGNAL spw1_din : STD_LOGIC := '1';
135 SIGNAL spw1_sin : STD_LOGIC := '1';
135 SIGNAL spw1_sin : STD_LOGIC := '1';
136 SIGNAL spw1_dout : STD_LOGIC;
136 SIGNAL spw1_dout : STD_LOGIC;
137 SIGNAL spw1_sout : STD_LOGIC;
137 SIGNAL spw1_sout : STD_LOGIC;
138 SIGNAL spw2_en : STD_LOGIC;
138 SIGNAL spw2_en : STD_LOGIC;
139 SIGNAL spw2_din : STD_LOGIC := '1';
139 SIGNAL spw2_din : STD_LOGIC := '1';
140 SIGNAL spw2_sin : STD_LOGIC := '1';
140 SIGNAL spw2_sin : STD_LOGIC := '1';
141 SIGNAL spw2_dout : STD_LOGIC;
141 SIGNAL spw2_dout : STD_LOGIC;
142 SIGNAL spw2_sout : STD_LOGIC;
142 SIGNAL spw2_sout : STD_LOGIC;
143 SIGNAL bias_fail_sw : STD_LOGIC;
143 SIGNAL bias_fail_sw : STD_LOGIC;
144 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
144 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
145 SIGNAL ADC_smpclk : STD_LOGIC;
145 SIGNAL ADC_smpclk : STD_LOGIC;
146 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
146 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
147 SIGNAL DAC_SDO : STD_LOGIC;
147 SIGNAL DAC_SDO : STD_LOGIC;
148 SIGNAL DAC_SCK : STD_LOGIC;
148 SIGNAL DAC_SCK : STD_LOGIC;
149 SIGNAL DAC_SYNC : STD_LOGIC;
149 SIGNAL DAC_SYNC : STD_LOGIC;
150 SIGNAL DAC_CAL_EN : STD_LOGIC;
150 SIGNAL DAC_CAL_EN : STD_LOGIC;
151 SIGNAL HK_smpclk : STD_LOGIC;
151 SIGNAL HK_smpclk : STD_LOGIC;
152 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
152 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
153 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
153 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
154 -- SIGNAL TAG8 : STD_LOGIC;
154 -- SIGNAL TAG8 : STD_LOGIC;
155
155
156 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
156 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
157 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
157 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
158 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
158 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
159 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
159 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
160 SIGNAL counter_scrub_period : INTEGER;
160 SIGNAL counter_scrub_period : INTEGER;
161
161
162
162
163 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
163 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
164 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
164 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
165 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
165 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
166
166
167 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
167 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
168 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
168 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
169 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
169 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
170 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
170 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
171 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
171 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
172 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
172 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
173
173
174 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
174 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
175 SIGNAL data_message : STRING(1 TO 15) := "---------------";
175 SIGNAL data_message : STRING(1 TO 15) := "---------------";
176 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
176 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
177 SIGNAL TXD1 : STD_LOGIC;
177 SIGNAL TXD1 : STD_LOGIC;
178 SIGNAL RXD1 : STD_LOGIC;
178 SIGNAL RXD1 : STD_LOGIC;
179
179
180 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
181 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
181 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
182 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
182 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
183 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
183 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
184 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
184 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
185 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
185 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
186 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
186 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
187 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
187 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
188 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
188 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
189 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
189 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
190 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
190 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
191 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
191 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
192 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
192 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
193 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
193 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
194 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
194 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
195
195
196
196
197 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
197 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
198 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
198 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
199
199
200 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
200 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
201 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
201 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
202
202
203 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
206 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
207
207
208 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
208 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
209 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
209 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
210 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
210 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
211
211
212
212
213 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
213 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
214 -----------------------------------------------------------------------------
214 -----------------------------------------------------------------------------
215 CONSTANT srambanks : INTEGER := 2;
215 CONSTANT srambanks : INTEGER := 2;
216 CONSTANT sramwidth : INTEGER := 32;
216 CONSTANT sramwidth : INTEGER := 32;
217 CONSTANT sramdepth : INTEGER := 19;
217 CONSTANT sramdepth : INTEGER := 19;
218 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
218 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
219 -----------------------------------------------------------------------------
219 -----------------------------------------------------------------------------
220
220
221 BEGIN -- beh
221 BEGIN -- beh
222
222
223 LFR_EQM_1 : LFR_EQM
223 LFR_EQM_1 : LFR_EQM
224 GENERIC MAP (
224 GENERIC MAP (
225 Mem_use => use_RAM,
225 Mem_use => use_RAM,
226 USE_BOOTLOADER => 0,
226 USE_BOOTLOADER => 0,
227 USE_ADCDRIVER => 0,
227 USE_ADCDRIVER => 1,
228 tech => apa3e,
228 tech => apa3e,
229 tech_leon => apa3e,
229 tech_leon => apa3e,
230 DEBUG_FORCE_DATA_DMA => 1,
230 DEBUG_FORCE_DATA_DMA => 1,
231 USE_DEBUG_VECTOR => 0)
231 USE_DEBUG_VECTOR => 0)
232 PORT MAP (
232 PORT MAP (
233 clk50MHz => clk50MHz, --IN --ok
233 clk50MHz => clk50MHz, --IN --ok
234 clk49_152MHz => clk49_152MHz, --in --ok
234 clk49_152MHz => clk49_152MHz, --in --ok
235 reset => reset, --IN --ok
235 reset => reset, --IN --ok
236
236
237 TAG => TAG,
237 TAG => TAG,
238 --TAG1 => TAG1, --in
238 --TAG1 => TAG1, --in
239 --TAG3 => TAG3, --out
239 --TAG3 => TAG3, --out
240 --TAG2 => TAG2, --IN --ok
240 --TAG2 => TAG2, --IN --ok
241 --TAG4 => TAG4, --out --ok
241 --TAG4 => TAG4, --out --ok
242
242
243 address => address, --out
243 address => address, --out
244 data => data, --inout
244 data => data, --inout
245 nSRAM_MBE => nSRAM_MBE, --inout
245 nSRAM_MBE => nSRAM_MBE, --inout
246 nSRAM_E1 => nSRAM_E1, --out
246 nSRAM_E1 => nSRAM_E1, --out
247 nSRAM_E2 => nSRAM_E2, --out
247 nSRAM_E2 => nSRAM_E2, --out
248 nSRAM_W => nSRAM_W, --out
248 nSRAM_W => nSRAM_W, --out
249 nSRAM_G => nSRAM_G, --out
249 nSRAM_G => nSRAM_G, --out
250 nSRAM_BUSY => nSRAM_BUSY, --in
250 nSRAM_BUSY => nSRAM_BUSY, --in
251
251
252 spw1_en => spw1_en, --out --ok
252 spw1_en => spw1_en, --out --ok
253 spw1_din => spw1_din, --in --ok
253 spw1_din => spw1_din, --in --ok
254 spw1_sin => spw1_sin, --in --ok
254 spw1_sin => spw1_sin, --in --ok
255 spw1_dout => spw1_dout, --out --ok
255 spw1_dout => spw1_dout, --out --ok
256 spw1_sout => spw1_sout, --out --ok
256 spw1_sout => spw1_sout, --out --ok
257
257
258 spw2_en => spw2_en, --out --ok
258 spw2_en => spw2_en, --out --ok
259 spw2_din => spw2_din, --in --ok
259 spw2_din => spw2_din, --in --ok
260 spw2_sin => spw2_sin, --in --ok
260 spw2_sin => spw2_sin, --in --ok
261 spw2_dout => spw2_dout, --out --ok
261 spw2_dout => spw2_dout, --out --ok
262 spw2_sout => spw2_sout, --out --ok
262 spw2_sout => spw2_sout, --out --ok
263
263
264 bias_fail_sw => bias_fail_sw, --OUT --ok
264 bias_fail_sw => bias_fail_sw, --OUT --ok
265
265
266 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
266 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
267 ADC_smpclk => ADC_smpclk, --out --ok
267 ADC_smpclk => ADC_smpclk, --out --ok
268 ADC_data => ADC_data, --IN --ok
268 ADC_data => ADC_data, --IN --ok
269
269
270 DAC_SDO => DAC_SDO, --out --ok
270 DAC_SDO => DAC_SDO, --out --ok
271 DAC_SCK => DAC_SCK, --out --ok
271 DAC_SCK => DAC_SCK, --out --ok
272 DAC_SYNC => DAC_SYNC, --out --ok
272 DAC_SYNC => DAC_SYNC, --out --ok
273 DAC_CAL_EN => DAC_CAL_EN, --out --ok
273 DAC_CAL_EN => DAC_CAL_EN, --out --ok
274
274
275 HK_smpclk => HK_smpclk, --out --ok
275 HK_smpclk => HK_smpclk, --out --ok
276 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
276 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
277 HK_SEL => HK_SEL); --out --ok
277 HK_SEL => HK_SEL); --out --ok
278
278
279
279
280 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
281 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
281 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
282 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
282 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
283 -----------------------------------------------------------------------------
283 -----------------------------------------------------------------------------
284
284
285 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
285 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
286 TestModule_RHF1401_1 : TestModule_RHF1401
286 TestModule_RHF1401_1 : TestModule_RHF1401
287 GENERIC MAP (
287 GENERIC MAP (
288 freq => 24*(I+1),
288 freq => 24*(I+1),
289 amplitude => 8000/(I+1),
289 amplitude => 8000/(I+1),
290 impulsion => 0)
290 impulsion => 0)
291 PORT MAP (
291 PORT MAP (
292 ADC_smpclk => ADC_smpclk,
292 ADC_smpclk => ADC_smpclk,
293 ADC_OEB_bar => ADC_OEB_bar_CH(I),
293 ADC_OEB_bar => ADC_OEB_bar_CH(I),
294 ADC_data => ADC_data);
294 ADC_data => ADC_data);
295 END GENERATE MODULE_RHF1401;
295 END GENERATE MODULE_RHF1401;
296
296
297 -----------------------------------------------------------------------------
297 -----------------------------------------------------------------------------
298 PROCESS (clk50MHz, reset)
298 PROCESS (clk50MHz, reset)
299 BEGIN -- PROCESS
299 BEGIN -- PROCESS
300 IF reset = '0' THEN -- asynchronous reset (active low)
300 IF reset = '0' THEN -- asynchronous reset (active low)
301 nSRAM_BUSY <= '1';
301 nSRAM_BUSY <= '1';
302 counter_scrub_period <= 0;
302 counter_scrub_period <= 0;
303 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
303 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
304 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
304 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
305 counter_scrub_period <= 0;
305 counter_scrub_period <= 0;
306 ELSE
306 ELSE
307 counter_scrub_period <= counter_scrub_period + 1;
307 counter_scrub_period <= counter_scrub_period + 1;
308 END IF;
308 END IF;
309
309
310 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
310 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
311 nSRAM_BUSY <= '1';
311 nSRAM_BUSY <= '1';
312 ELSE
312 ELSE
313 nSRAM_BUSY <= '0';
313 nSRAM_BUSY <= '0';
314 END IF;
314 END IF;
315 END IF;
315 END IF;
316 END PROCESS;
316 END PROCESS;
317
317
318 -----------------------------------------------------------------------------
318 -----------------------------------------------------------------------------
319 -- TB
319 -- TB
320 -----------------------------------------------------------------------------
320 -----------------------------------------------------------------------------
321 TAG(1) <= TXD1;
321 TAG(1) <= TXD1;
322 TAG(2) <= '1';
322 TAG(2) <= '1';
323 RXD1 <= TAG(3);
323 RXD1 <= TAG(3);
324
324
325 PROCESS
325 PROCESS
326 CONSTANT txp : TIME := 320 ns;
326 CONSTANT txp : TIME := 320 ns;
327 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
327 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
328 BEGIN -- PROCESS
328 BEGIN -- PROCESS
329 TXD1 <= '1';
329 TXD1 <= '1';
330 reset <= '0';
330 reset <= '0';
331 WAIT FOR 500 ns;
331 WAIT FOR 500 ns;
332 reset <= '1';
332 reset <= '1';
333 WAIT FOR 100 us;
333 WAIT FOR 100 us;
334 message_simu <= "0 - UART init ";
334 message_simu <= "0 - UART init ";
335 UART_INIT(TXD1, txp);
335 UART_INIT(TXD1, txp);
336
336
337 ---------------------------------------------------------------------------
337 ---------------------------------------------------------------------------
338 -- LAUNCH leon 3 software
338 -- LAUNCH leon 3 software
339 ---------------------------------------------------------------------------
339 ---------------------------------------------------------------------------
340 message_simu <= "2- GO Leon3....";
340 message_simu <= "2- GO Leon3....";
341
341
342 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
342 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
343 --Force a debug break
343 --Force a debug break
344 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
344 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
345 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
345 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
346 --Clear time tag counter
346 --Clear time tag counter
347 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
347 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
348 --Clear ASR registers
348 --Clear ASR registers
349 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
349 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
350 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
350 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
351 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
351 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
352 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
352 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
353 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
353 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
354 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
354 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
355 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
355 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
358 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
358 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
359 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
359 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
360 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
360 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
361 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
361 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
362 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
362 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
363 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
363 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
364
364
365 IF USE_ESA_MEMCTRL = 1 THEN
365 IF USE_ESA_MEMCTRL = 1 THEN
366 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
366 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
367 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
367 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
368 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
368 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
369 END IF;
369 END IF;
370
370
371 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
371 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
372 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
372 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
373 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
373 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
374 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
374 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
375 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
375 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
376
376
377 --memSet(DSUBASEADDRESS+0x300000,0,1567);
377 --memSet(DSUBASEADDRESS+0x300000,0,1567);
378
378
379 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
379 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
380 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
380 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
381 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
381 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
382 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
382 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
383 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
383 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
384 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
384 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
385 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
385 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
386
386
387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
388 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
388 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
391 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
391 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
392 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
392 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
393 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
393 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
405 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
405 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
407 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
407 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
408 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
408 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
409 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
409 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
410 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
410 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
411
411
412 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
412 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
413
413
414 --//Disable interrupts
414 --//Disable interrupts
415 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
415 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
416 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
416 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
417 -- return false;
417 -- return false;
418 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
418 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
419 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
419 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
420 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
420 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
421
421
422 -- //Set up timer
422 -- //Set up timer
423 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
423 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
424 --if(APBTIMERBASEADD == (unsigned int)-1)
424 --if(APBTIMERBASEADD == (unsigned int)-1)
425 -- return false;
425 -- return false;
426 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
426 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
427 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
427 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
428 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
428 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
429
429
430
430
431 ---------------------------------------------------------------------------
431 ---------------------------------------------------------------------------
432 --bool dsu3plugin::setCacheEnable(bool enabled)
432 --bool dsu3plugin::setCacheEnable(bool enabled)
433 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
433 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
434 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
434 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
435 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
435 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
436 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
436 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
437 data_read <= data_read_v;
437 data_read <= data_read_v;
438 --if(enabled){
438 --if(enabled){
439 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
439 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
440 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
440 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
441 --}else{
441 --}else{
442 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
442 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
443 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
443 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
444 --}
444 --}
445
445
446
446
447 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
447 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
448 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
448 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
449
449
450 ---------------------------------------------------------------------------
450 ---------------------------------------------------------------------------
451 --message_simu <= "1 - UART test ";
451 --message_simu <= "1 - UART test ";
452 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
452 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
453 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
453 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
454 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
454 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
455 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
455 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
456 --data_read <= data_read_v;
456 --data_read <= data_read_v;
457 --data_message <= "GPIO_data_write";
457 --data_message <= "GPIO_data_write";
458
458
459 -- UNSET the LFR reset
459 -- UNSET the LFR reset
460 message_simu <= "2 - LFR UNRESET";
460 message_simu <= "2 - LFR UNRESET";
461 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
461 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
462 --
462 --
463 message_simu <= "3 - LFR CONFIG ";
463 message_simu <= "3 - LFR CONFIG ";
464 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
464 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
465 ADDR_BUFFER_MS_F0_0,
465 ADDR_BUFFER_MS_F0_0,
466 ADDR_BUFFER_MS_F0_1,
466 ADDR_BUFFER_MS_F0_1,
467 ADDR_BUFFER_MS_F1_0,
467 ADDR_BUFFER_MS_F1_0,
468 ADDR_BUFFER_MS_F1_1,
468 ADDR_BUFFER_MS_F1_1,
469 ADDR_BUFFER_MS_F2_0,
469 ADDR_BUFFER_MS_F2_0,
470 ADDR_BUFFER_MS_F2_1);
470 ADDR_BUFFER_MS_F2_1);
471
471
472
472
473 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
473 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
474 LFR_MODE_SBM1,
474 LFR_MODE_SBM1,
475 X"7FFFFFFF", -- START DATE
475 X"7FFFFFFF", -- START DATE
476
476
477 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
477 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
478 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
478 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
479 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
479 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
480 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
480 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
481 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
481 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
482 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
482 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
483
483
484 ADDR_BASE_LFR,
484 ADDR_BASE_LFR,
485 ADDR_BUFFER_WFP_F0_0,
485 ADDR_BUFFER_WFP_F0_0,
486 ADDR_BUFFER_WFP_F0_1,
486 ADDR_BUFFER_WFP_F0_1,
487 ADDR_BUFFER_WFP_F1_0,
487 ADDR_BUFFER_WFP_F1_0,
488 ADDR_BUFFER_WFP_F1_1,
488 ADDR_BUFFER_WFP_F1_1,
489 ADDR_BUFFER_WFP_F2_0,
489 ADDR_BUFFER_WFP_F2_0,
490 ADDR_BUFFER_WFP_F2_1,
490 ADDR_BUFFER_WFP_F2_1,
491 ADDR_BUFFER_WFP_F3_0,
491 ADDR_BUFFER_WFP_F3_0,
492 ADDR_BUFFER_WFP_F3_1);
492 ADDR_BUFFER_WFP_F3_1);
493
493
494 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
494 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
495 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
495 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
496
496
497
497
498 ---------------------------------------------------------------------------
498 ---------------------------------------------------------------------------
499 -- CONFIG LFR 2
499 -- CONFIG LFR 2
500 ---------------------------------------------------------------------------
500 ---------------------------------------------------------------------------
501 --message_simu <= "3 - LFR2 CONFIG";
501 --message_simu <= "3 - LFR2 CONFIG";
502 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
502 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
503 -- X"40000000",
503 -- X"40000000",
504 -- X"40001000",
504 -- X"40001000",
505 -- X"40002000",
505 -- X"40002000",
506 -- X"40003000",
506 -- X"40003000",
507 -- X"40004000",
507 -- X"40004000",
508 -- X"40005000");
508 -- X"40005000");
509
509
510
510
511 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
511 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
512 -- LFR_MODE_SBM1,
512 -- LFR_MODE_SBM1,
513 -- X"7FFFFFFF", -- START DATE
513 -- X"7FFFFFFF", -- START DATE
514
514
515 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
515 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
516 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
516 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
517 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
517 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
518 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
518 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
519 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
519 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
520 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
520 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
521
521
522 -- ADDR_BASE_LFR_2,
522 -- ADDR_BASE_LFR_2,
523 -- X"40006000",
523 -- X"40006000",
524 -- X"40007000",
524 -- X"40007000",
525 -- X"40008000",
525 -- X"40008000",
526 -- X"40009000",
526 -- X"40009000",
527 -- X"4000A000",
527 -- X"4000A000",
528 -- X"4000B000",
528 -- X"4000B000",
529 -- X"4000C000",
529 -- X"4000C000",
530 -- X"4000D000");
530 -- X"4000D000");
531
531
532 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
532 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
533 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
533 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
534
534
535 ---------------------------------------------------------------------------
535 ---------------------------------------------------------------------------
536 ---------------------------------------------------------------------------
536 ---------------------------------------------------------------------------
537 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"58", X"FFFFFFFF");
537 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"5" & "10", X"FFFFFFFF");
538
538
539
539
540 message_simu <= "4 - GO GO GO !!";
540 message_simu <= "4 - GO GO GO !!";
541 data_message <= "---------------";
541 data_message <= "---------------";
542 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
542 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
543 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
543 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
544
544
545
545
546 data_read_v := (OTHERS => '1');
546 data_read_v := (OTHERS => '1');
547 READ_STATUS : LOOP
547 READ_STATUS : LOOP
548 data_message <= "---------------";
548 data_message <= "---------------";
549 WAIT FOR 2 ms;
549 WAIT FOR 2 ms;
550 data_message <= "READ_STATUS_SM_";
550 data_message <= "READ_STATUS_SM_";
551 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
551 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
552 --data_message <= "--------------r";
552 --data_message <= "--------------r";
553 --data_read <= data_read_v;
553 --data_read <= data_read_v;
554 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
554 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
555
555
556 data_message <= "READ_STATUS_WF_";
556 data_message <= "READ_STATUS_WF_";
557 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
557 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
558 --data_message <= "--------------r";
558 --data_message <= "--------------r";
559 --data_read <= data_read_v;
559 --data_read <= data_read_v;
560 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
560 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
561 END LOOP READ_STATUS;
561 END LOOP READ_STATUS;
562
562
563 WAIT;
563 WAIT;
564 END PROCESS;
564 END PROCESS;
565
565
566
566
567 -----------------------------------------------------------------------------
567 -----------------------------------------------------------------------------
568 PROCESS (nSRAM_W, reset)
568 PROCESS (nSRAM_W, reset)
569 BEGIN -- PROCESS
569 BEGIN -- PROCESS
570 IF reset = '0' THEN -- asynchronous reset (active low)
570 IF reset = '0' THEN -- asynchronous reset (active low)
571 data_pre_f0 <= X"00020001";
571 data_pre_f0 <= X"00020001";
572 data_pre_f1 <= X"00020001";
572 data_pre_f1 <= X"00020001";
573 data_pre_f2 <= X"00020001";
573 data_pre_f2 <= X"00020001";
574
574
575 addr_pre_f0 <= (OTHERS => '0');
575 addr_pre_f0 <= (OTHERS => '0');
576 addr_pre_f1 <= (OTHERS => '0');
576 addr_pre_f1 <= (OTHERS => '0');
577 addr_pre_f2 <= (OTHERS => '0');
577 addr_pre_f2 <= (OTHERS => '0');
578
578
579 error_wfp <= "000";
579 error_wfp <= "000";
580 error_wfp_addr <= "000";
580 error_wfp_addr <= "000";
581
581
582 sample_counter <= (0,0,0);
582 sample_counter <= (0,0,0);
583
583
584 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
584 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
585 error_wfp <= "000";
585 error_wfp <= "000";
586 error_wfp_addr <= "000";
586 error_wfp_addr <= "000";
587 -------------------------------------------------------------------------
587 -------------------------------------------------------------------------
588 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
588 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
589 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
589 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
590
590
591 addr_pre_f0 <= address(13 DOWNTO 0);
591 addr_pre_f0 <= address(13 DOWNTO 0);
592 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
592 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
593 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
593 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
594 error_wfp_addr(0) <= '1';
594 error_wfp_addr(0) <= '1';
595 END IF;
595 END IF;
596 END IF;
596 END IF;
597
597
598 data_pre_f0 <= data;
598 data_pre_f0 <= data;
599 CASE data_pre_f0 IS
599 CASE data_pre_f0 IS
600 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
600 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
601 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
601 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
602 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
602 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
603 WHEN OTHERS => error_wfp(0) <= '1';
603 WHEN OTHERS => error_wfp(0) <= '1';
604 END CASE;
604 END CASE;
605
605
606
606
607 END IF;
607 END IF;
608 -------------------------------------------------------------------------
608 -------------------------------------------------------------------------
609 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
609 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
610 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
610 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
611
611
612 addr_pre_f1 <= address(13 DOWNTO 0);
612 addr_pre_f1 <= address(13 DOWNTO 0);
613 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
613 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
614 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
614 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
615 error_wfp_addr(1) <= '1';
615 error_wfp_addr(1) <= '1';
616 END IF;
616 END IF;
617 END IF;
617 END IF;
618
618
619 data_pre_f1 <= data;
619 data_pre_f1 <= data;
620 CASE data_pre_f1 IS
620 CASE data_pre_f1 IS
621 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
621 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
622 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
622 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
623 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
623 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
624 WHEN OTHERS => error_wfp(1) <= '1';
624 WHEN OTHERS => error_wfp(1) <= '1';
625 END CASE;
625 END CASE;
626
626
627 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
627 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
628 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
628 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
629 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
629 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
630
630
631 END IF;
631 END IF;
632 -------------------------------------------------------------------------
632 -------------------------------------------------------------------------
633 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
633 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
634 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
634 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
635
635
636 addr_pre_f2 <= address(13 DOWNTO 0);
636 addr_pre_f2 <= address(13 DOWNTO 0);
637 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
637 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
638 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
638 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
639 error_wfp_addr(2) <= '1';
639 error_wfp_addr(2) <= '1';
640 END IF;
640 END IF;
641 END IF;
641 END IF;
642
642
643 data_pre_f2 <= data;
643 data_pre_f2 <= data;
644 CASE data_pre_f2 IS
644 CASE data_pre_f2 IS
645 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
645 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
646 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
646 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
647 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
647 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
648 WHEN OTHERS => error_wfp(2) <= '1';
648 WHEN OTHERS => error_wfp(2) <= '1';
649 END CASE;
649 END CASE;
650
650
651 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
651 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
652 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
652 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
653 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
653 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
654
654
655 END IF;
655 END IF;
656 END IF;
656 END IF;
657 END PROCESS;
657 END PROCESS;
658 -----------------------------------------------------------------------------
658 -----------------------------------------------------------------------------
659 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
659 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
660
660
661 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
661 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
662 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
662 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
663 sr0 : sram
663 sr0 : sram
664 GENERIC MAP (
664 GENERIC MAP (
665 index => i,
665 index => i,
666 abits => sramdepth,
666 abits => sramdepth,
667 fname => sramfile)
667 fname => sramfile)
668 PORT MAP (
668 PORT MAP (
669 address,
669 address,
670 data(31-i*8 DOWNTO 24-i*8),
670 data(31-i*8 DOWNTO 24-i*8),
671 ramsn(k),
671 ramsn(k),
672 nSRAM_W,
672 nSRAM_W,
673 nSRAM_G
673 nSRAM_G
674 );
674 );
675 END GENERATE;
675 END GENERATE;
676 END GENERATE;
676 END GENERATE;
677
677
678 END beh;
678 END beh;
679
679
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