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LFR-em 1.1.35
pellion -
r467:10ba15a05d8c (LFR-EM) WFP_MS-1-1-35 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 85 ---------------------------------------------------------------------------
86 86 TAG8 : OUT STD_LOGIC;
87 87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 88 );
89 89
90 90 END LFR_em;
91 91
92 92
93 93 ARCHITECTURE beh OF LFR_em IS
94 94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 95 SIGNAL clk_25 : STD_LOGIC := '0';
96 96 SIGNAL clk_24 : STD_LOGIC := '0';
97 97 -----------------------------------------------------------------------------
98 98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 100
101 101 -- CONSTANTS
102 102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106 106
107 107 SIGNAL apbi_ext : apb_slv_in_type;
108 108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113 113
114 114 -- Spacewire signals
115 115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 120 SIGNAL spw_clk : STD_LOGIC;
121 121 SIGNAL swni : grspw_in_type;
122 122 SIGNAL swno : grspw_out_type;
123 123
124 124 --GPIO
125 125 SIGNAL gpioi : gpio_in_type;
126 126 SIGNAL gpioo : gpio_out_type;
127 127
128 128 -- AD Converter ADS7886
129 129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 130 SIGNAL sample_s : Samples(7 DOWNTO 0);
131 131 SIGNAL sample_val : STD_LOGIC;
132 132 SIGNAL ADC_nCS_sig : STD_LOGIC;
133 133 SIGNAL ADC_CLK_sig : STD_LOGIC;
134 134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
135 135
136 136 -----------------------------------------------------------------------------
137 137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 138
139 139 -----------------------------------------------------------------------------
140 140 SIGNAL rstn : STD_LOGIC;
141 141
142 142 SIGNAL LFR_soft_rstn : STD_LOGIC;
143 143 SIGNAL LFR_rstn : STD_LOGIC;
144 144
145 145 SIGNAL ADC_smpclk_s : STD_LOGIC;
146 146
147 147 BEGIN -- beh
148 148
149 149 -----------------------------------------------------------------------------
150 150 -- CLK
151 151 -----------------------------------------------------------------------------
152 152 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
153 153
154 154 PROCESS(clk100MHz)
155 155 BEGIN
156 156 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
157 157 clk_50_s <= NOT clk_50_s;
158 158 END IF;
159 159 END PROCESS;
160 160
161 161 PROCESS(clk_50_s)
162 162 BEGIN
163 163 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
164 164 clk_25 <= NOT clk_25;
165 165 END IF;
166 166 END PROCESS;
167 167
168 168 PROCESS(clk49_152MHz)
169 169 BEGIN
170 170 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
171 171 clk_24 <= NOT clk_24;
172 172 END IF;
173 173 END PROCESS;
174 174
175 175 -----------------------------------------------------------------------------
176 176
177 177 PROCESS (clk_25, rstn)
178 178 BEGIN -- PROCESS
179 179 IF rstn = '0' THEN -- asynchronous reset (active low)
180 180 led(0) <= '0';
181 181 led(1) <= '0';
182 182 led(2) <= '0';
183 183 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
184 184 led(0) <= '0';
185 185 led(1) <= '1';
186 186 led(2) <= '1';
187 187 END IF;
188 188 END PROCESS;
189 189
190 190 --
191 191 leon3_soc_1 : leon3_soc
192 192 GENERIC MAP (
193 193 fabtech => apa3e,
194 194 memtech => apa3e,
195 195 padtech => inferred,
196 196 clktech => inferred,
197 197 disas => 0,
198 198 dbguart => 0,
199 199 pclow => 2,
200 200 clk_freq => 25000,
201 201 NB_CPU => 1,
202 202 ENABLE_FPU => 1,
203 203 FPU_NETLIST => 0,
204 204 ENABLE_DSU => 1,
205 205 ENABLE_AHB_UART => 1,
206 206 ENABLE_APB_UART => 1,
207 207 ENABLE_IRQMP => 1,
208 208 ENABLE_GPT => 1,
209 209 NB_AHB_MASTER => NB_AHB_MASTER,
210 210 NB_AHB_SLAVE => NB_AHB_SLAVE,
211 211 NB_APB_SLAVE => NB_APB_SLAVE)
212 212 PORT MAP (
213 213 clk => clk_25,
214 214 reset => rstn,
215 215 errorn => OPEN,
216 216
217 217 ahbrxd => TAG1,
218 218 ahbtxd => TAG3,
219 219 urxd1 => TAG2,
220 220 utxd1 => TAG4,
221 221
222 222 address => address,
223 223 data => data,
224 224 nSRAM_BE0 => nSRAM_BE0,
225 225 nSRAM_BE1 => nSRAM_BE1,
226 226 nSRAM_BE2 => nSRAM_BE2,
227 227 nSRAM_BE3 => nSRAM_BE3,
228 228 nSRAM_WE => nSRAM_WE,
229 229 nSRAM_CE => nSRAM_CE,
230 230 nSRAM_OE => nSRAM_OE,
231 231
232 232 apbi_ext => apbi_ext,
233 233 apbo_ext => apbo_ext,
234 234 ahbi_s_ext => ahbi_s_ext,
235 235 ahbo_s_ext => ahbo_s_ext,
236 236 ahbi_m_ext => ahbi_m_ext,
237 237 ahbo_m_ext => ahbo_m_ext);
238 238
239 239
240 240 -------------------------------------------------------------------------------
241 241 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
242 242 -------------------------------------------------------------------------------
243 243 apb_lfr_time_management_1 : apb_lfr_time_management
244 244 GENERIC MAP (
245 245 pindex => 6,
246 246 paddr => 6,
247 247 pmask => 16#fff#,
248 248 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
249 249 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
250 250 PORT MAP (
251 251 clk25MHz => clk_25,
252 252 clk24_576MHz => clk_24, -- 49.152MHz/2
253 253 resetn => rstn,
254 254 grspw_tick => swno.tickout,
255 255 apbi => apbi_ext,
256 256 apbo => apbo_ext(6),
257 257 coarse_time => coarse_time,
258 258 fine_time => fine_time,
259 259 LFR_soft_rstn => LFR_soft_rstn
260 260 );
261 261
262 262 -----------------------------------------------------------------------
263 263 --- SpaceWire --------------------------------------------------------
264 264 -----------------------------------------------------------------------
265 265
266 266 -- SPW_EN <= '1';
267 267
268 268 spw_clk <= clk_50_s;
269 269 spw_rxtxclk <= spw_clk;
270 270 spw_rxclkn <= NOT spw_rxtxclk;
271 271
272 272 -- PADS for SPW1
273 273 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
274 274 PORT MAP (spw1_din, dtmp(0));
275 275 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
276 276 PORT MAP (spw1_sin, stmp(0));
277 277 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
278 278 PORT MAP (spw1_dout, swno.d(0));
279 279 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
280 280 PORT MAP (spw1_sout, swno.s(0));
281 281 -- PADS FOR SPW2
282 282 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
283 283 PORT MAP (spw2_din, dtmp(1));
284 284 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
285 285 PORT MAP (spw2_sin, stmp(1));
286 286 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
287 287 PORT MAP (spw2_dout, swno.d(1));
288 288 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
289 289 PORT MAP (spw2_sout, swno.s(1));
290 290
291 291 -- GRSPW PHY
292 292 --spw1_input: if CFG_SPW_GRSPW = 1 generate
293 293 spw_inputloop : FOR j IN 0 TO 1 GENERATE
294 294 spw_phy0 : grspw_phy
295 295 GENERIC MAP(
296 296 tech => apa3e,
297 297 rxclkbuftype => 1,
298 298 scantest => 0)
299 299 PORT MAP(
300 300 rxrst => swno.rxrst,
301 301 di => dtmp(j),
302 302 si => stmp(j),
303 303 rxclko => spw_rxclk(j),
304 304 do => swni.d(j),
305 305 ndo => swni.nd(j*5+4 DOWNTO j*5),
306 306 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
307 307 END GENERATE spw_inputloop;
308 308
309 309 -- SPW core
310 310 sw0 : grspwm GENERIC MAP(
311 311 tech => apa3e,
312 312 hindex => 1,
313 313 pindex => 5,
314 314 paddr => 5,
315 315 pirq => 11,
316 316 sysfreq => 25000, -- CPU_FREQ
317 317 rmap => 1,
318 318 rmapcrc => 1,
319 319 fifosize1 => 16,
320 320 fifosize2 => 16,
321 321 rxclkbuftype => 1,
322 322 rxunaligned => 0,
323 323 rmapbufs => 4,
324 324 ft => 0,
325 325 netlist => 0,
326 326 ports => 2,
327 327 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
328 328 memtech => apa3e,
329 329 destkey => 2,
330 330 spwcore => 1
331 331 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
332 332 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
333 333 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
334 334 )
335 335 PORT MAP(rstn, clk_25, spw_rxclk(0),
336 336 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
337 337 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
338 338 swni, swno);
339 339
340 340 swni.tickin <= '0';
341 341 swni.rmapen <= '1';
342 342 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
343 343 swni.tickinraw <= '0';
344 344 swni.timein <= (OTHERS => '0');
345 345 swni.dcrstval <= (OTHERS => '0');
346 346 swni.timerrstval <= (OTHERS => '0');
347 347
348 348 -------------------------------------------------------------------------------
349 349 -- LFR ------------------------------------------------------------------------
350 350 -------------------------------------------------------------------------------
351 351 LFR_rstn <= LFR_soft_rstn AND rstn;
352 352
353 353 lpp_lfr_1 : lpp_lfr
354 354 GENERIC MAP (
355 355 Mem_use => use_RAM,
356 356 nb_data_by_buffer_size => 32,
357 357 --nb_word_by_buffer_size => 30,
358 358 nb_snapshot_param_size => 32,
359 359 delta_vector_size => 32,
360 360 delta_vector_size_f0_2 => 7, -- log2(96)
361 361 pindex => 15,
362 362 paddr => 15,
363 363 pmask => 16#fff#,
364 364 pirq_ms => 6,
365 365 pirq_wfp => 14,
366 366 hindex => 2,
367 top_lfr_version => X"010122") -- aa.bb.cc version
367 top_lfr_version => X"010123") -- aa.bb.cc version
368 368 -- AA : BOARD NUMBER
369 369 -- 0 => MINI_LFR
370 370 -- 1 => EM
371 371 PORT MAP (
372 372 clk => clk_25,
373 373 rstn => LFR_rstn,
374 374 sample_B => sample_s(2 DOWNTO 0),
375 375 sample_E => sample_s(7 DOWNTO 3),
376 376 sample_val => sample_val,
377 377 apbi => apbi_ext,
378 378 apbo => apbo_ext(15),
379 379 ahbi => ahbi_m_ext,
380 380 ahbo => ahbo_m_ext(2),
381 381 coarse_time => coarse_time,
382 382 fine_time => fine_time,
383 383 data_shaping_BW => bias_fail_sw);--,
384 384 --observation_vector_0 => OPEN,
385 385 --observation_vector_1 => OPEN,
386 386 --observation_reg => observation_reg);
387 387
388 388
389 389 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
390 390 sample_s(I) <= sample(I) & '0' & '0';
391 391 END GENERATE all_sample;
392 392
393 393 -----------------------------------------------------------------------------
394 394 --
395 395 -----------------------------------------------------------------------------
396 396 top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
397 397 GENERIC MAP (
398 398 ChanelCount => 8,
399 399 ncycle_cnv_high => 13,
400 400 ncycle_cnv => 25)
401 401 PORT MAP (
402 402 cnv_clk => clk_24,
403 403 cnv_rstn => rstn,
404 404 cnv => ADC_smpclk_s,
405 405 clk => clk_25,
406 406 rstn => rstn,
407 407 ADC_data => ADC_data,
408 408 ADC_nOE => ADC_OEB_bar_CH,
409 409 sample => sample,
410 410 sample_val => sample_val);
411 411
412 412
413 413
414 414
415 415 --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
416 416 -- GENERIC MAP (
417 417 -- ChanelCount => 8,
418 418 -- ncycle_cnv_high => 40, -- TODO : 79
419 419 -- ncycle_cnv => 250) -- TODO : 500
420 420 -- PORT MAP (
421 421 -- cnv_clk => clk_24, -- TODO : 49.152
422 422 -- cnv_rstn => rstn, -- ok
423 423 -- cnv => ADC_smpclk_s, -- ok
424 424 -- clk => clk_25, -- ok
425 425 -- rstn => rstn, -- ok
426 426 -- ADC_data => ADC_data, -- ok
427 427 -- ADC_nOE => ADC_OEB_bar_CH, -- ok
428 428 -- sample => sample, -- ok
429 429 -- sample_val => sample_val); -- ok
430 430
431 431 ADC_smpclk <= ADC_smpclk_s;
432 432
433 433 TAG8 <= ADC_smpclk_s;
434 434
435 435 END beh;
Show file before | Show file after | Hide comments
@@ -1,271 +1,280
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4 use IEEE.std_logic_textio.all;
5 5 LIBRARY STD;
6 6 use std.textio.all;
7 7
8 8 LIBRARY grlib;
9 9 USE grlib.stdlib.ALL;
10 10 LIBRARY gaisler;
11 11 USE gaisler.libdcom.ALL;
12 12 USE gaisler.sim.ALL;
13 13 USE gaisler.jtagtst.ALL;
14 14 LIBRARY techmap;
15 15 USE techmap.gencomp.ALL;
16 16
17 17 LIBRARY lpp;
18 18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
19 20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21 22
22 23
23 24 ENTITY testbench IS
24 25 END;
25 26
26 27 ARCHITECTURE behav OF testbench IS
27 28
28 29 COMPONENT MINI_LFR_top
29 30 PORT (
30 31 clk_50 : IN STD_LOGIC;
31 32 clk_49 : IN STD_LOGIC;
32 33 reset : IN STD_LOGIC;
33 34 BP0 : IN STD_LOGIC;
34 35 BP1 : IN STD_LOGIC;
35 36 LED0 : OUT STD_LOGIC;
36 37 LED1 : OUT STD_LOGIC;
37 38 LED2 : OUT STD_LOGIC;
38 39 TXD1 : IN STD_LOGIC;
39 40 RXD1 : OUT STD_LOGIC;
40 41 nCTS1 : OUT STD_LOGIC;
41 42 nRTS1 : IN STD_LOGIC;
42 43 TXD2 : IN STD_LOGIC;
43 44 RXD2 : OUT STD_LOGIC;
44 45 nCTS2 : OUT STD_LOGIC;
45 46 nDTR2 : IN STD_LOGIC;
46 47 nRTS2 : IN STD_LOGIC;
47 48 nDCD2 : OUT STD_LOGIC;
48 49 IO0 : INOUT STD_LOGIC;
49 50 IO1 : INOUT STD_LOGIC;
50 51 IO2 : INOUT STD_LOGIC;
51 52 IO3 : INOUT STD_LOGIC;
52 53 IO4 : INOUT STD_LOGIC;
53 54 IO5 : INOUT STD_LOGIC;
54 55 IO6 : INOUT STD_LOGIC;
55 56 IO7 : INOUT STD_LOGIC;
56 57 IO8 : INOUT STD_LOGIC;
57 58 IO9 : INOUT STD_LOGIC;
58 59 IO10 : INOUT STD_LOGIC;
59 60 IO11 : INOUT STD_LOGIC;
60 61 SPW_EN : OUT STD_LOGIC;
61 62 SPW_NOM_DIN : IN STD_LOGIC;
62 63 SPW_NOM_SIN : IN STD_LOGIC;
63 64 SPW_NOM_DOUT : OUT STD_LOGIC;
64 65 SPW_NOM_SOUT : OUT STD_LOGIC;
65 66 SPW_RED_DIN : IN STD_LOGIC;
66 67 SPW_RED_SIN : IN STD_LOGIC;
67 68 SPW_RED_DOUT : OUT STD_LOGIC;
68 69 SPW_RED_SOUT : OUT STD_LOGIC;
69 70 ADC_nCS : OUT STD_LOGIC;
70 71 ADC_CLK : OUT STD_LOGIC;
71 72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
72 73 SRAM_nWE : OUT STD_LOGIC;
73 74 SRAM_CE : OUT STD_LOGIC;
74 75 SRAM_nOE : OUT STD_LOGIC;
75 76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
76 77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
77 78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
78 79 END COMPONENT;
79 80
80 81 -----------------------------------------------------------------------------
81 82 SIGNAL clk_50 : STD_LOGIC := '0';
82 83 SIGNAL clk_49 : STD_LOGIC := '0';
83 84 SIGNAL reset : STD_LOGIC;
84 85 SIGNAL BP0 : STD_LOGIC;
85 86 SIGNAL BP1 : STD_LOGIC;
86 87 SIGNAL LED0 : STD_LOGIC;
87 88 SIGNAL LED1 : STD_LOGIC;
88 89 SIGNAL LED2 : STD_LOGIC;
89 90 SIGNAL TXD1 : STD_LOGIC;
90 91 SIGNAL RXD1 : STD_LOGIC;
91 92 SIGNAL nCTS1 : STD_LOGIC;
92 93 SIGNAL nRTS1 : STD_LOGIC;
93 94 SIGNAL TXD2 : STD_LOGIC;
94 95 SIGNAL RXD2 : STD_LOGIC;
95 96 SIGNAL nCTS2 : STD_LOGIC;
96 97 SIGNAL nDTR2 : STD_LOGIC;
97 98 SIGNAL nRTS2 : STD_LOGIC;
98 99 SIGNAL nDCD2 : STD_LOGIC;
99 100 SIGNAL IO0 : STD_LOGIC;
100 101 SIGNAL IO1 : STD_LOGIC;
101 102 SIGNAL IO2 : STD_LOGIC;
102 103 SIGNAL IO3 : STD_LOGIC;
103 104 SIGNAL IO4 : STD_LOGIC;
104 105 SIGNAL IO5 : STD_LOGIC;
105 106 SIGNAL IO6 : STD_LOGIC;
106 107 SIGNAL IO7 : STD_LOGIC;
107 108 SIGNAL IO8 : STD_LOGIC;
108 109 SIGNAL IO9 : STD_LOGIC;
109 110 SIGNAL IO10 : STD_LOGIC;
110 111 SIGNAL IO11 : STD_LOGIC;
111 112 SIGNAL SPW_EN : STD_LOGIC;
112 113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
113 114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
114 115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
115 116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
116 117 SIGNAL SPW_RED_DIN : STD_LOGIC;
117 118 SIGNAL SPW_RED_SIN : STD_LOGIC;
118 119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
119 120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
120 121 SIGNAL ADC_nCS : STD_LOGIC;
121 122 SIGNAL ADC_CLK : STD_LOGIC;
122 123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
123 124 SIGNAL SRAM_nWE : STD_LOGIC;
124 125 SIGNAL SRAM_CE : STD_LOGIC;
125 126 SIGNAL SRAM_nOE : STD_LOGIC;
126 127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
128 129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 130 -----------------------------------------------------------------------------
130 131
131 132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
132 133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
133 134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
134 135
135 136
136 137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
138
139 SIGNAL data_message : STRING(1 TO 15) := "---------------";
140 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
137 141
138 142 BEGIN
139 143
140 144 -----------------------------------------------------------------------------
141 145 -- TB
142 146 -----------------------------------------------------------------------------
143 147 PROCESS
144 148 CONSTANT txp : TIME := 320 ns;
149 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 150 BEGIN -- PROCESS
146 151 TXD1 <= '1';
147 152 reset <= '0';
148 153 WAIT FOR 500 ns;
149 154 reset <= '1';
150 155 WAIT FOR 10000 ns;
151 156 message_simu <= "0 - UART init ";
152 157 UART_INIT(TXD1,txp);
153 158
154 159 message_simu <= "1 - UART test ";
155 160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
156 161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
157 162 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
158
163 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
164 data_read <= data_read_v;
165 data_message <= "GPIO_data_write";
166
159 167 -- UNSET the LFR reset
160 168 message_simu <= "2 - LFR UNRESET";
161 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
162 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
169 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
171 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
163 172 --
164 173 message_simu <= "3 - LFR CONFIG ";
165 174 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
166 175
167 176 WAIT;
168 177 END PROCESS;
169 178
170 179 -----------------------------------------------------------------------------
171 180 -- CLOCK
172 181 -----------------------------------------------------------------------------
173 182 clk_50 <= NOT clk_50 AFTER 5 ns;
174 183 clk_49 <= NOT clk_49 AFTER 10172 ps;
175 184
176 185 -----------------------------------------------------------------------------
177 186 -- DON'T CARE
178 187 -----------------------------------------------------------------------------
179 188 BP0 <= '0';
180 189 BP1 <= '0';
181 190 nRTS1 <= '0' ;
182 191
183 192 TXD2 <= '1';
184 193 nRTS2 <= '1';
185 194 nDTR2 <= '1';
186 195
187 196 SPW_NOM_DIN <= '1';
188 197 SPW_NOM_SIN <= '1';
189 198 SPW_RED_DIN <= '1';
190 199 SPW_RED_SIN <= '1';
191 200
192 201 ADC_SDO <= x"AA";
193 202
194 203 SRAM_DQ <= (OTHERS => 'Z');
195 204 --IO0 <= 'Z';
196 205 --IO1 <= 'Z';
197 206 --IO2 <= 'Z';
198 207 --IO3 <= 'Z';
199 208 --IO4 <= 'Z';
200 209 --IO5 <= 'Z';
201 210 --IO6 <= 'Z';
202 211 --IO7 <= 'Z';
203 212 --IO8 <= 'Z';
204 213 --IO9 <= 'Z';
205 214 --IO10 <= 'Z';
206 215 --IO11 <= 'Z';
207 216
208 217 -----------------------------------------------------------------------------
209 218 -- DUT
210 219 -----------------------------------------------------------------------------
211 220 MINI_LFR_top_1: MINI_LFR_top
212 221 PORT MAP (
213 222 clk_50 => clk_50,
214 223 clk_49 => clk_49,
215 224 reset => reset,
216 225
217 226 BP0 => BP0,
218 227 BP1 => BP1,
219 228
220 229 LED0 => LED0,
221 230 LED1 => LED1,
222 231 LED2 => LED2,
223 232
224 233 TXD1 => TXD1,
225 234 RXD1 => RXD1,
226 235 nCTS1 => nCTS1,
227 236 nRTS1 => nRTS1,
228 237
229 238 TXD2 => TXD2,
230 239 RXD2 => RXD2,
231 240 nCTS2 => nCTS2,
232 241 nDTR2 => nDTR2,
233 242 nRTS2 => nRTS2,
234 243 nDCD2 => nDCD2,
235 244
236 245 IO0 => IO0,
237 246 IO1 => IO1,
238 247 IO2 => IO2,
239 248 IO3 => IO3,
240 249 IO4 => IO4,
241 250 IO5 => IO5,
242 251 IO6 => IO6,
243 252 IO7 => IO7,
244 253 IO8 => IO8,
245 254 IO9 => IO9,
246 255 IO10 => IO10,
247 256 IO11 => IO11,
248 257
249 258 SPW_EN => SPW_EN,
250 259 SPW_NOM_DIN => SPW_NOM_DIN,
251 260 SPW_NOM_SIN => SPW_NOM_SIN,
252 261 SPW_NOM_DOUT => SPW_NOM_DOUT,
253 262 SPW_NOM_SOUT => SPW_NOM_SOUT,
254 263 SPW_RED_DIN => SPW_RED_DIN,
255 264 SPW_RED_SIN => SPW_RED_SIN,
256 265 SPW_RED_DOUT => SPW_RED_DOUT,
257 266 SPW_RED_SOUT => SPW_RED_SOUT,
258 267
259 268 ADC_nCS => ADC_nCS,
260 269 ADC_CLK => ADC_CLK,
261 270 ADC_SDO => ADC_SDO,
262 271
263 272 SRAM_nWE => SRAM_nWE,
264 273 SRAM_CE => SRAM_CE,
265 274 SRAM_nOE => SRAM_nOE,
266 275 SRAM_nBE => SRAM_nBE,
267 276 SRAM_A => SRAM_A,
268 277 SRAM_DQ => SRAM_DQ);
269 278
270 279
271 280 END;
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@@ -1,201 +1,201
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 --USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
12 --USE lpp.lpp_top_lfr_pkg.ALL;
13 --USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY DMA_SubSystem IS
26 26
27 27 GENERIC (
28 28 hindex : INTEGER := 2);
29 29
30 30 PORT (
31 31 clk : IN STD_LOGIC;
32 32 rstn : IN STD_LOGIC;
33 33 run : IN STD_LOGIC;
34 34 -- AHB
35 35 ahbi : IN AHB_Mst_In_Type;
36 36 ahbo : OUT AHB_Mst_Out_Type;
37 37 ---------------------------------------------------------------------------
38 38 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
40 40 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 41 ---------------------------------------------------------------------------
42 42 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 43 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
44 44 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
45 45 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 46 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 47 ---------------------------------------------------------------------------
48 48 grant_error : OUT STD_LOGIC --
49 49
50 50 );
51 51
52 52 END DMA_SubSystem;
53 53
54 54
55 55 ARCHITECTURE beh OF DMA_SubSystem IS
56 56
57 57 COMPONENT DMA_SubSystem_GestionBuffer
58 58 GENERIC (
59 59 BUFFER_ADDR_SIZE : INTEGER;
60 60 BUFFER_LENGTH_SIZE : INTEGER);
61 61 PORT (
62 62 clk : IN STD_LOGIC;
63 63 rstn : IN STD_LOGIC;
64 64 run : IN STD_LOGIC;
65 65 buffer_new : IN STD_LOGIC;
66 66 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
67 67 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
68 68 buffer_full : OUT STD_LOGIC;
69 69 buffer_full_err : OUT STD_LOGIC;
70 70 burst_send : IN STD_LOGIC;
71 71 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
72 72 END COMPONENT;
73 73
74 74 COMPONENT DMA_SubSystem_Arbiter
75 75 PORT (
76 76 clk : IN STD_LOGIC;
77 77 rstn : IN STD_LOGIC;
78 78 run : IN STD_LOGIC;
79 79 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 80 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
81 81 END COMPONENT;
82 82
83 83 COMPONENT DMA_SubSystem_MUX
84 84 PORT (
85 85 clk : IN STD_LOGIC;
86 86 rstn : IN STD_LOGIC;
87 87 run : IN STD_LOGIC;
88 88 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
89 89 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
90 90 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
91 91 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
92 92 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 dma_send : OUT STD_LOGIC;
94 94 dma_valid_burst : OUT STD_LOGIC;
95 95 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 96 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 dma_ren : IN STD_LOGIC;
98 98 dma_done : IN STD_LOGIC;
99 99 grant_error : OUT STD_LOGIC);
100 100 END COMPONENT;
101 101
102 102 -----------------------------------------------------------------------------
103 103 SIGNAL dma_send : STD_LOGIC;
104 104 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
105 105 SIGNAL dma_done : STD_LOGIC;
106 106 SIGNAL dma_ren : STD_LOGIC;
107 107 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 109 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 110 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 111 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
112 112
113 113
114 114 BEGIN -- beh
115 115
116 116 -----------------------------------------------------------------------------
117 117 -- DMA
118 118 -----------------------------------------------------------------------------
119 119 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
120 120 GENERIC MAP (
121 121 tech => inferred,
122 122 hindex => hindex)
123 123 PORT MAP (
124 124 HCLK => clk,
125 125 HRESETn => rstn,
126 126 run => run,
127 127 AHB_Master_In => ahbi,
128 128 AHB_Master_Out => ahbo,
129 129
130 130 send => dma_send,
131 131 valid_burst => dma_valid_burst,
132 132 done => dma_done,
133 133 ren => dma_ren,
134 134 address => dma_address,
135 135 data => dma_data);
136 136
137 137
138 138 -----------------------------------------------------------------------------
139 139 -- RoundRobin Selection Channel For DMA
140 140 -----------------------------------------------------------------------------
141 141 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
142 142 PORT MAP (
143 143 clk => clk,
144 144 rstn => rstn,
145 145 run => run,
146 146 data_burst_valid => fifo_burst_valid,
147 147 data_burst_valid_grant => fifo_grant);
148 148
149 149
150 150 -----------------------------------------------------------------------------
151 151 -- Mux between the channel from Waveform Picker and Spectral Matrix
152 152 -----------------------------------------------------------------------------
153 153 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
154 154 PORT MAP (
155 155 clk => clk,
156 156 rstn => rstn,
157 157 run => run,
158 158
159 159 fifo_grant => fifo_grant,
160 160 fifo_data => fifo_data,
161 161 fifo_address => fifo_address,
162 162 fifo_ren => fifo_ren,
163 163 fifo_burst_done => burst_send,
164 164
165 165 dma_send => dma_send,
166 166 dma_valid_burst => dma_valid_burst,
167 167 dma_address => dma_address,
168 168 dma_data => dma_data,
169 169 dma_ren => dma_ren,
170 170 dma_done => dma_done,
171 171
172 172 grant_error => grant_error);
173 173
174 174
175 175 -----------------------------------------------------------------------------
176 176 -- GEN ADDR
177 177 -----------------------------------------------------------------------------
178 178 all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
179 179 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
180 180 GENERIC MAP (
181 181 BUFFER_ADDR_SIZE => 32,
182 182 BUFFER_LENGTH_SIZE => 26)
183 183 PORT MAP (
184 184 clk => clk,
185 185 rstn => rstn,
186 186 run => run,
187 187
188 188 buffer_new => buffer_new(I),
189 189 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
190 190 buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
191 191 buffer_full => buffer_full(I),
192 192 buffer_full_err => buffer_full_err(I),
193 193
194 194 burst_send => burst_send(I),
195 195 burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
196 196 );
197 197 END GENERATE all_buffer;
198 198
199 199
200 200
201 201 END beh;
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@@ -1,94 +1,94
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 --USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
12 --USE lpp.lpp_top_lfr_pkg.ALL;
13 --USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY DMA_SubSystem_Arbiter IS
26 26
27 27 PORT (
28 28 clk : IN STD_LOGIC;
29 29 rstn : IN STD_LOGIC;
30 30 run : IN STD_LOGIC;
31 31 --
32 32 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
34 34 );
35 35
36 36 END DMA_SubSystem_Arbiter;
37 37
38 38
39 39 ARCHITECTURE beh OF DMA_SubSystem_Arbiter IS
40 40
41 41 SIGNAL data_burst_valid_r : STD_LOGIC_VECTOR(4 DOWNTO 0);
42 42 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
43 43 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
44 44 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
45 45
46 46 BEGIN -- beh
47 47 -----------------------------------------------------------------------------
48 48 -- REG the burst valid signal
49 49 -----------------------------------------------------------------------------
50 50 PROCESS (clk, rstn)
51 51 BEGIN -- PROCESS
52 52 IF rstn = '0' THEN -- asynchronous reset (active low)
53 53 data_burst_valid_r <= (OTHERS => '0');
54 54 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
55 55 IF run = '1' THEN
56 56 data_burst_valid_r <= data_burst_valid;
57 57 ELSE
58 58 data_burst_valid_r <= (OTHERS => '0');
59 59 END IF;
60 60
61 61 END IF;
62 62 END PROCESS;
63 63
64 64 -----------------------------------------------------------------------------
65 65 -- ARBITER Between all the "WAVEFORM_PICKER" channel
66 66 -----------------------------------------------------------------------------
67 67 RR_Arbiter_4_1 : RR_Arbiter_4
68 68 PORT MAP (
69 69 clk => clk,
70 70 rstn => rstn,
71 71 in_valid => data_burst_valid_r(3 DOWNTO 0),
72 72 out_grant => dma_rr_grant_s);
73 73
74 74 dma_rr_valid_ms(0) <= data_burst_valid_r(4);--data_ms_valid OR data_ms_valid_burst;
75 75 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
76 76 dma_rr_valid_ms(2) <= '0';
77 77 dma_rr_valid_ms(3) <= '0';
78 78
79 79 -----------------------------------------------------------------------------
80 80 -- ARBITER Between all the "WAVEFORM_PICKER" and "SPECTRAL MATRIX"
81 81 -----------------------------------------------------------------------------
82 82
83 83 RR_Arbiter_4_2 : RR_Arbiter_4
84 84 PORT MAP (
85 85 clk => clk,
86 86 rstn => rstn,
87 87 in_valid => dma_rr_valid_ms,
88 88 out_grant => dma_rr_grant_ms);
89 89
90 90 data_burst_valid_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
91 91
92 92
93 93
94 94 END beh;
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@@ -1,118 +1,118
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 --USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
12 --USE lpp.lpp_top_lfr_pkg.ALL;
13 --USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY DMA_SubSystem_MUX IS
26 26
27 27 PORT (
28 28 clk : IN STD_LOGIC;
29 29 rstn : IN STD_LOGIC;
30 30 run : IN STD_LOGIC;
31 31 --
32 32 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
34 34 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
35 35 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --
36 36 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 37 --
38 38 dma_send : OUT STD_LOGIC;
39 39 dma_valid_burst : OUT STD_LOGIC; --
40 40 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
41 41 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
42 42 dma_ren : IN STD_LOGIC; --
43 43 dma_done : IN STD_LOGIC; --
44 44 --
45 45 grant_error : OUT STD_LOGIC --
46 46 );
47 47
48 48 END DMA_SubSystem_MUX;
49 49
50 50 ARCHITECTURE beh OF DMA_SubSystem_MUX IS
51 51 SIGNAL channel_ongoing : STD_LOGIC_VECTOR(4 DOWNTO 0);
52 52 SIGNAL one_grant : STD_LOGIC;
53 53 SIGNAL more_than_one_grant : STD_LOGIC;
54 54
55 55 BEGIN
56 56
57 57 one_grant <= '0' WHEN fifo_grant = "00000" ELSE '1';
58 58 more_than_one_grant <= '0' WHEN fifo_grant = "00000" OR
59 59 fifo_grant = "00001" OR
60 60 fifo_grant = "00010" OR
61 61 fifo_grant = "00100" OR
62 62 fifo_grant = "01000" OR
63 63 fifo_grant = "10000" ELSE '1';
64 64
65 65 PROCESS (clk, rstn)
66 66 BEGIN -- PROCESS
67 67 IF rstn = '0' THEN -- asynchronous reset (active low)
68 68 channel_ongoing <= (OTHERS => '0');
69 69 fifo_burst_done <= (OTHERS => '0');
70 70 dma_send <= '0';
71 71 dma_valid_burst <= '0';
72 72 grant_error <= '0';
73 73 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
74 74 grant_error <= '0';
75 75 IF run = '1' THEN
76 76 IF dma_done = '1' THEN
77 77 fifo_burst_done <= channel_ongoing;
78 78 ELSE
79 79 fifo_burst_done <= (OTHERS => '0');
80 80 END IF;
81 81
82 82 IF channel_ongoing = "00000" OR dma_done = '1' THEN
83 83 channel_ongoing <= fifo_grant;
84 84 grant_error <= more_than_one_grant;
85 85 dma_valid_burst <= one_grant;
86 86 dma_send <= one_grant;
87 87 ELSE
88 88 dma_send <= '0';
89 89 END IF;
90 90
91 91 ELSE
92 92 channel_ongoing <= (OTHERS => '0');
93 93 fifo_burst_done <= (OTHERS => '0');
94 94 dma_send <= '0';
95 95 dma_valid_burst <= '0';
96 96 END IF;
97 97 END IF;
98 98 END PROCESS;
99 99
100 100 -------------------------------------------------------------------------
101 101
102 102 all_channel : FOR I IN 4 DOWNTO 0 GENERATE
103 103 fifo_ren(I) <= dma_ren WHEN channel_ongoing(I) = '1' ELSE '1';
104 104 END GENERATE all_channel;
105 105
106 106 dma_data <= fifo_data(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
107 107 fifo_data(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
108 108 fifo_data(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
109 109 fifo_data(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
110 110 fifo_data(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE
111 111
112 112 dma_address <= fifo_address(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
113 113 fifo_address(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
114 114 fifo_address(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
115 115 fifo_address(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
116 116 fifo_address(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE
117 117
118 118 END beh;
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@@ -1,206 +1,206
1 1
2 2 ------------------------------------------------------------------------------
3 3 -- This file is a part of the LPP VHDL IP LIBRARY
4 4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 5 --
6 6 -- This program is free software; you can redistribute it and/or modify
7 7 -- it under the terms of the GNU General Public License as published by
8 8 -- the Free Software Foundation; either version 3 of the License, or
9 9 -- (at your option) any later version.
10 10 --
11 11 -- This program is distributed in the hope that it will be useful,
12 12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 14 -- GNU General Public License for more details.
15 15 --
16 16 -- You should have received a copy of the GNU General Public License
17 17 -- along with this program; if not, write to the Free Software
18 18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 -------------------------------------------------------------------------------
20 20 -- Author : Jean-christophe Pellion
21 21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 22 -- jean-christophe.pellion@easii-ic.com
23 23 -------------------------------------------------------------------------------
24 24 -- 1.0 - initial version
25 25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 26 -------------------------------------------------------------------------------
27 27 LIBRARY ieee;
28 28 USE ieee.std_logic_1164.ALL;
29 29 USE ieee.numeric_std.ALL;
30 30 LIBRARY grlib;
31 31 USE grlib.amba.ALL;
32 32 USE grlib.stdlib.ALL;
33 33 USE grlib.devices.ALL;
34 34 USE GRLIB.DMA2AHB_Package.ALL;
35 35 LIBRARY lpp;
36 36 USE lpp.lpp_amba.ALL;
37 37 USE lpp.apb_devices_list.ALL;
38 38 USE lpp.lpp_memory.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 --USE lpp.lpp_waveform_pkg.ALL;
41 41 LIBRARY techmap;
42 42 USE techmap.gencomp.ALL;
43 43
44 44
45 45 ENTITY lpp_dma_singleOrBurst IS
46 46 GENERIC (
47 47 tech : INTEGER := inferred;
48 48 hindex : INTEGER := 2
49 49 );
50 50 PORT (
51 51 -- AMBA AHB system signals
52 52 HCLK : IN STD_ULOGIC;
53 53 HRESETn : IN STD_ULOGIC;
54 54 --
55 55 run : IN STD_LOGIC;
56 56 -- AMBA AHB Master Interface
57 57 AHB_Master_In : IN AHB_Mst_In_Type;
58 58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 59 --
60 60 send : IN STD_LOGIC;
61 61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 62 done : OUT STD_LOGIC;
63 63 ren : OUT STD_LOGIC;
64 64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 66 --
67 67 debug_dmaout_okay : OUT STD_LOGIC
68 68
69 69 );
70 70 END;
71 71
72 72 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
73 73 -----------------------------------------------------------------------------
74 74 SIGNAL DMAIn : DMA_In_Type;
75 75 SIGNAL DMAOut : DMA_OUt_Type;
76 76 -----------------------------------------------------------------------------
77 77 -----------------------------------------------------------------------------
78 78 -- CONTROL
79 79 SIGNAL single_send : STD_LOGIC;
80 80 SIGNAL burst_send : STD_LOGIC;
81 81
82 82 -----------------------------------------------------------------------------
83 83 -- SEND SINGLE MODULE
84 84 SIGNAL single_dmai : DMA_In_Type;
85 85
86 86 SIGNAL single_send_ok : STD_LOGIC;
87 87 SIGNAL single_send_ko : STD_LOGIC;
88 88 SIGNAL single_ren : STD_LOGIC;
89 89 -----------------------------------------------------------------------------
90 90 -- SEND SINGLE MODULE
91 91 SIGNAL burst_dmai : DMA_In_Type;
92 92
93 93 SIGNAL burst_send_ok : STD_LOGIC;
94 94 SIGNAL burst_send_ko : STD_LOGIC;
95 95 SIGNAL burst_ren : STD_LOGIC;
96 96 -----------------------------------------------------------------------------
97 97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 -----------------------------------------------------------------------------
99 99 -- \/ -- 20/02/2014 -- JC Pellion
100 100 SIGNAL send_reg : STD_LOGIC;
101 101 SIGNAL send_s : STD_LOGIC;
102 102 -- /\ --
103 103
104 104
105 105 BEGIN
106 106
107 107 debug_dmaout_okay <= DMAOut.OKAY;
108 108
109 109
110 110 -----------------------------------------------------------------------------
111 111 -- DMA to AHB interface
112 112 DMA2AHB_1 : DMA2AHB
113 113 GENERIC MAP (
114 114 hindex => hindex,
115 115 vendorid => VENDOR_LPP,
116 116 deviceid => 10,
117 117 version => 0,
118 118 syncrst => 1,
119 119 boundary => 1) -- FIX 11/01/2013
120 120 PORT MAP (
121 121 HCLK => HCLK,
122 122 HRESETn => HRESETn,
123 123 DMAIn => DMAIn,
124 124 DMAOut => DMAOut,
125 125
126 126 AHBIn => AHB_Master_In,
127 127 AHBOut => AHB_Master_Out);
128 128 -----------------------------------------------------------------------------
129 129
130 130 -----------------------------------------------------------------------------
131 131 -- \/ -- 20/02/2014 -- JC Pellion
132 132 PROCESS (HCLK, HRESETn)
133 133 BEGIN
134 134 IF HRESETn = '0' THEN
135 135 send_reg <= '0';
136 136 ELSIF HCLK'event AND HCLK = '1' THEN
137 137 send_reg <= send;
138 138 END IF;
139 139 END PROCESS;
140 140 send_s <= send_reg;
141 141
142 142 single_send <= send_s WHEN valid_burst = '0' ELSE '0';
143 143 burst_send <= send_s WHEN valid_burst = '1' ELSE '0';
144 144 -- /\ --
145 145
146 146 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
147 147
148 148 -- TODO : verifier
149 149 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
150 150 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
151 151 -- burst_send_ok OR burst_send_ko;
152 152
153 153 --ren <= burst_ren WHEN valid_burst = '1' ELSE
154 154 -- NOT single_send_ok;
155 155 --ren <= burst_ren AND single_ren;
156 156
157 157 -- \/ JC - 20/01/2014 \/
158 158 ren <= burst_ren WHEN valid_burst = '1' ELSE
159 159 single_ren;
160 160
161 161
162 162 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
163 163 -- '1';
164 164 -- /\ JC - 20/01/2014 /\
165 165
166 166 -----------------------------------------------------------------------------
167 167 -- SEND 1 word by DMA
168 168 -----------------------------------------------------------------------------
169 169 lpp_dma_send_1word_1 : lpp_dma_send_1word
170 170 PORT MAP (
171 171 HCLK => HCLK,
172 172 HRESETn => HRESETn,
173 173 DMAIn => single_dmai,
174 174 DMAOut => DMAOut,
175 175
176 176 send => single_send,
177 177 address => address,
178 178 data => data_2_halfword,
179 179 ren => single_ren,
180 180
181 181 send_ok => single_send_ok, -- TODO
182 182 send_ko => single_send_ko -- TODO
183 183 );
184 184
185 185 -----------------------------------------------------------------------------
186 186 -- SEND 16 word by DMA (in burst mode)
187 187 -----------------------------------------------------------------------------
188 188 --data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
189 189 data_2_halfword(31 DOWNTO 0) <= data(31 DOWNTO 0);
190 190
191 191 lpp_dma_send_16word_1 : lpp_dma_send_16word
192 192 PORT MAP (
193 193 HCLK => HCLK,
194 194 HRESETn => HRESETn,
195 195 DMAIn => burst_dmai,
196 196 DMAOut => DMAOut,
197 197
198 198 send => burst_send,
199 199 address => address,
200 200 data => data_2_halfword,
201 201 ren => burst_ren,
202 202
203 203 send_ok => burst_send_ok,
204 204 send_ko => burst_send_ko);
205 205
206 206 END Behavioral;
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@@ -1,104 +1,139
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.libdcom.ALL;
30 30 USE gaisler.sim.ALL;
31 31 USE gaisler.jtagtst.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34
35 35 PACKAGE lpp_sim_pkg IS
36 36
37 37 PROCEDURE UART_INIT (
38 38 SIGNAL TX : OUT STD_LOGIC;
39 39 CONSTANT tx_period : IN TIME
40 40 );
41 41 PROCEDURE UART_WRITE_ADDR32 (
42 42 SIGNAL TX : OUT STD_LOGIC;
43 43 CONSTANT tx_period : IN TIME;
44 44 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
45 45 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
46 46 );
47 47 PROCEDURE UART_WRITE (
48 48 SIGNAL TX : OUT STD_LOGIC;
49 49 CONSTANT tx_period : IN TIME;
50 50 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
51 51 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
52 52 );
53
53 PROCEDURE UART_READ (
54 SIGNAL TX : OUT STD_LOGIC;
55 SIGNAL RX : IN STD_LOGIC;
56 CONSTANT tx_period : IN TIME;
57 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
58 DATA : OUT STD_LOGIC_VECTOR
59 );
60
61
54 62 END lpp_sim_pkg;
55 63
56 64 PACKAGE BODY lpp_sim_pkg IS
57 65
58 66 PROCEDURE UART_INIT (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME) IS
59 67 BEGIN
60 68 txc(TX, 16#55#, tx_period);
61 69 END;
62 70
63 71 PROCEDURE UART_WRITE_ADDR32 (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
64 72 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 73 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
66 74 BEGIN
67 75 txc(TX, 16#c0#, tx_period);
68 76 txa(TX,
69 77 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
70 78 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
71 79 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
72 80 to_integer(UNSIGNED(ADDR(7 DOWNTO 0))),
73 81 tx_period);
74 82 txa(TX,
75 83 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
76 84 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
77 85 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
78 86 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
79 87 tx_period);
80 88 END;
81 89
82 90 PROCEDURE UART_WRITE (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
83 91 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
84 92 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
85 93
86 94 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
87 95
88 96 BEGIN
89 97 txc(TX, 16#c0#, tx_period);
90 98 txa(TX,
91 99 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
92 100 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
93 101 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
94 102 to_integer(UNSIGNED(ADDR_last)),
95 103 tx_period);
96 104 txa(TX,
97 105 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
98 106 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
99 107 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
100 108 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
101 109 tx_period);
102 110 END;
103 111
112 PROCEDURE UART_READ (
113 SIGNAL TX : OUT STD_LOGIC;
114 SIGNAL RX : IN STD_LOGIC;
115 CONSTANT tx_period : IN TIME;
116 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
117 DATA : OUT STD_LOGIC_VECTOR )
118 IS
119 VARIABLE V_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
120 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
121 BEGIN
122 txc(TX, 16#80#, tx_period);
123 txa(TX,
124 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
125 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
126 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
127 to_integer(UNSIGNED(ADDR_last)),
128 tx_period);
129 rxc(RX,V_DATA,tx_period);
130 DATA(31 DOWNTO 24) := V_DATA;
131 rxc(RX,V_DATA,tx_period);
132 DATA(23 DOWNTO 16) := V_DATA;
133 rxc(RX,V_DATA,tx_period);
134 DATA(15 DOWNTO 8) := V_DATA;
135 rxc(RX,V_DATA,tx_period);
136 DATA(7 DOWNTO 0) := V_DATA;
137 END;
138
104 139 END lpp_sim_pkg;
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@@ -1,2 +1,3
1 1 lpp_sim_pkg.vhd
2 lpp_lfr_sim_pkg.vhd
2 3
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