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Update arbitration in front of FFT based on falling edge of fft_ready and sample_load
pellion -
r386:100ad6ccce4d (MINI-LFR) WFP_MS-0-1-21 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 BEGIN -- beh
179 BEGIN -- beh
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK
182 -- CLK
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184
184
185 PROCESS(clk_50)
185 PROCESS(clk_50)
186 BEGIN
186 BEGIN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 clk_50_s <= NOT clk_50_s;
188 clk_50_s <= NOT clk_50_s;
189 END IF;
189 END IF;
190 END PROCESS;
190 END PROCESS;
191
191
192 PROCESS(clk_50_s)
192 PROCESS(clk_50_s)
193 BEGIN
193 BEGIN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 clk_25 <= NOT clk_25;
195 clk_25 <= NOT clk_25;
196 END IF;
196 END IF;
197 END PROCESS;
197 END PROCESS;
198
198
199 PROCESS(clk_49)
199 PROCESS(clk_49)
200 BEGIN
200 BEGIN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 clk_24 <= NOT clk_24;
202 clk_24 <= NOT clk_24;
203 END IF;
203 END IF;
204 END PROCESS;
204 END PROCESS;
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207
207
208 PROCESS (clk_25, reset)
208 PROCESS (clk_25, reset)
209 BEGIN -- PROCESS
209 BEGIN -- PROCESS
210 IF reset = '0' THEN -- asynchronous reset (active low)
210 IF reset = '0' THEN -- asynchronous reset (active low)
211 LED0 <= '0';
211 LED0 <= '0';
212 LED1 <= '0';
212 LED1 <= '0';
213 LED2 <= '0';
213 LED2 <= '0';
214 --IO1 <= '0';
214 --IO1 <= '0';
215 --IO2 <= '1';
215 --IO2 <= '1';
216 --IO3 <= '0';
216 --IO3 <= '0';
217 --IO4 <= '0';
217 --IO4 <= '0';
218 --IO5 <= '0';
218 --IO5 <= '0';
219 --IO6 <= '0';
219 --IO6 <= '0';
220 --IO7 <= '0';
220 --IO7 <= '0';
221 --IO8 <= '0';
221 --IO8 <= '0';
222 --IO9 <= '0';
222 --IO9 <= '0';
223 --IO10 <= '0';
223 --IO10 <= '0';
224 --IO11 <= '0';
224 --IO11 <= '0';
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 LED0 <= '0';
226 LED0 <= '0';
227 LED1 <= '1';
227 LED1 <= '1';
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 --IO1 <= '1';
229 --IO1 <= '1';
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 --IO3 <= ADC_SDO(0);
231 --IO3 <= ADC_SDO(0);
232 --IO4 <= ADC_SDO(1);
232 --IO4 <= ADC_SDO(1);
233 --IO5 <= ADC_SDO(2);
233 --IO5 <= ADC_SDO(2);
234 --IO6 <= ADC_SDO(3);
234 --IO6 <= ADC_SDO(3);
235 --IO7 <= ADC_SDO(4);
235 --IO7 <= ADC_SDO(4);
236 --IO8 <= ADC_SDO(5);
236 --IO8 <= ADC_SDO(5);
237 --IO9 <= ADC_SDO(6);
237 --IO9 <= ADC_SDO(6);
238 --IO10 <= ADC_SDO(7);
238 --IO10 <= ADC_SDO(7);
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 END IF;
240 END IF;
241 END PROCESS;
241 END PROCESS;
242
242
243 PROCESS (clk_24, reset)
243 PROCESS (clk_24, reset)
244 BEGIN -- PROCESS
244 BEGIN -- PROCESS
245 IF reset = '0' THEN -- asynchronous reset (active low)
245 IF reset = '0' THEN -- asynchronous reset (active low)
246 I00_s <= '0';
246 I00_s <= '0';
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 I00_s <= NOT I00_s ;
248 I00_s <= NOT I00_s ;
249 END IF;
249 END IF;
250 END PROCESS;
250 END PROCESS;
251 -- IO0 <= I00_s;
251 -- IO0 <= I00_s;
252
252
253 --UARTs
253 --UARTs
254 nCTS1 <= '1';
254 nCTS1 <= '1';
255 nCTS2 <= '1';
255 nCTS2 <= '1';
256 nDCD2 <= '1';
256 nDCD2 <= '1';
257
257
258 --EXT CONNECTOR
258 --EXT CONNECTOR
259
259
260 --SPACE WIRE
260 --SPACE WIRE
261
261
262 leon3_soc_1 : leon3_soc
262 leon3_soc_1 : leon3_soc
263 GENERIC MAP (
263 GENERIC MAP (
264 fabtech => apa3e,
264 fabtech => apa3e,
265 memtech => apa3e,
265 memtech => apa3e,
266 padtech => inferred,
266 padtech => inferred,
267 clktech => inferred,
267 clktech => inferred,
268 disas => 0,
268 disas => 0,
269 dbguart => 0,
269 dbguart => 0,
270 pclow => 2,
270 pclow => 2,
271 clk_freq => 25000,
271 clk_freq => 25000,
272 NB_CPU => 1,
272 NB_CPU => 1,
273 ENABLE_FPU => 1,
273 ENABLE_FPU => 1,
274 FPU_NETLIST => 0,
274 FPU_NETLIST => 0,
275 ENABLE_DSU => 1,
275 ENABLE_DSU => 1,
276 ENABLE_AHB_UART => 1,
276 ENABLE_AHB_UART => 1,
277 ENABLE_APB_UART => 1,
277 ENABLE_APB_UART => 1,
278 ENABLE_IRQMP => 1,
278 ENABLE_IRQMP => 1,
279 ENABLE_GPT => 1,
279 ENABLE_GPT => 1,
280 NB_AHB_MASTER => NB_AHB_MASTER,
280 NB_AHB_MASTER => NB_AHB_MASTER,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 NB_APB_SLAVE => NB_APB_SLAVE)
282 NB_APB_SLAVE => NB_APB_SLAVE)
283 PORT MAP (
283 PORT MAP (
284 clk => clk_25,
284 clk => clk_25,
285 reset => reset,
285 reset => reset,
286 errorn => errorn,
286 errorn => errorn,
287 ahbrxd => TXD1,
287 ahbrxd => TXD1,
288 ahbtxd => RXD1,
288 ahbtxd => RXD1,
289 urxd1 => TXD2,
289 urxd1 => TXD2,
290 utxd1 => RXD2,
290 utxd1 => RXD2,
291 address => SRAM_A,
291 address => SRAM_A,
292 data => SRAM_DQ,
292 data => SRAM_DQ,
293 nSRAM_BE0 => SRAM_nBE(0),
293 nSRAM_BE0 => SRAM_nBE(0),
294 nSRAM_BE1 => SRAM_nBE(1),
294 nSRAM_BE1 => SRAM_nBE(1),
295 nSRAM_BE2 => SRAM_nBE(2),
295 nSRAM_BE2 => SRAM_nBE(2),
296 nSRAM_BE3 => SRAM_nBE(3),
296 nSRAM_BE3 => SRAM_nBE(3),
297 nSRAM_WE => SRAM_nWE,
297 nSRAM_WE => SRAM_nWE,
298 nSRAM_CE => SRAM_CE,
298 nSRAM_CE => SRAM_CE,
299 nSRAM_OE => SRAM_nOE,
299 nSRAM_OE => SRAM_nOE,
300
300
301 apbi_ext => apbi_ext,
301 apbi_ext => apbi_ext,
302 apbo_ext => apbo_ext,
302 apbo_ext => apbo_ext,
303 ahbi_s_ext => ahbi_s_ext,
303 ahbi_s_ext => ahbi_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
305 ahbi_m_ext => ahbi_m_ext,
305 ahbi_m_ext => ahbi_m_ext,
306 ahbo_m_ext => ahbo_m_ext);
306 ahbo_m_ext => ahbo_m_ext);
307
307
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 -------------------------------------------------------------------------------
310 -------------------------------------------------------------------------------
311 apb_lfr_time_management_1 : apb_lfr_time_management
311 apb_lfr_time_management_1 : apb_lfr_time_management
312 GENERIC MAP (
312 GENERIC MAP (
313 pindex => 6,
313 pindex => 6,
314 paddr => 6,
314 paddr => 6,
315 pmask => 16#fff#,
315 pmask => 16#fff#,
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 PORT MAP (
318 PORT MAP (
319 clk25MHz => clk_25,
319 clk25MHz => clk_25,
320 clk24_576MHz => clk_24, -- 49.152MHz/2
320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 resetn => reset,
321 resetn => reset,
322 grspw_tick => swno.tickout,
322 grspw_tick => swno.tickout,
323 apbi => apbi_ext,
323 apbi => apbi_ext,
324 apbo => apbo_ext(6),
324 apbo => apbo_ext(6),
325 coarse_time => coarse_time,
325 coarse_time => coarse_time,
326 fine_time => fine_time);
326 fine_time => fine_time);
327
327
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
330 -----------------------------------------------------------------------
330 -----------------------------------------------------------------------
331
331
332 SPW_EN <= '1';
332 SPW_EN <= '1';
333
333
334 spw_clk <= clk_50_s;
334 spw_clk <= clk_50_s;
335 spw_rxtxclk <= spw_clk;
335 spw_rxtxclk <= spw_clk;
336 spw_rxclkn <= NOT spw_rxtxclk;
336 spw_rxclkn <= NOT spw_rxtxclk;
337
337
338 -- PADS for SPW1
338 -- PADS for SPW1
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SIN, stmp(0));
342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 -- PADS FOR SPW2
347 -- PADS FOR SPW2
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_SIN, dtmp(1));
349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 PORT MAP (SPW_RED_DIN, stmp(1));
351 PORT MAP (SPW_RED_DIN, stmp(1));
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356
356
357 -- GRSPW PHY
357 -- GRSPW PHY
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 spw_phy0 : grspw_phy
360 spw_phy0 : grspw_phy
361 GENERIC MAP(
361 GENERIC MAP(
362 tech => apa3e,
362 tech => apa3e,
363 rxclkbuftype => 1,
363 rxclkbuftype => 1,
364 scantest => 0)
364 scantest => 0)
365 PORT MAP(
365 PORT MAP(
366 rxrst => swno.rxrst,
366 rxrst => swno.rxrst,
367 di => dtmp(j),
367 di => dtmp(j),
368 si => stmp(j),
368 si => stmp(j),
369 rxclko => spw_rxclk(j),
369 rxclko => spw_rxclk(j),
370 do => swni.d(j),
370 do => swni.d(j),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 END GENERATE spw_inputloop;
373 END GENERATE spw_inputloop;
374
374
375 -- SPW core
375 -- SPW core
376 sw0 : grspwm GENERIC MAP(
376 sw0 : grspwm GENERIC MAP(
377 tech => apa3e,
377 tech => apa3e,
378 hindex => 1,
378 hindex => 1,
379 pindex => 5,
379 pindex => 5,
380 paddr => 5,
380 paddr => 5,
381 pirq => 11,
381 pirq => 11,
382 sysfreq => 25000, -- CPU_FREQ
382 sysfreq => 25000, -- CPU_FREQ
383 rmap => 1,
383 rmap => 1,
384 rmapcrc => 1,
384 rmapcrc => 1,
385 fifosize1 => 16,
385 fifosize1 => 16,
386 fifosize2 => 16,
386 fifosize2 => 16,
387 rxclkbuftype => 1,
387 rxclkbuftype => 1,
388 rxunaligned => 0,
388 rxunaligned => 0,
389 rmapbufs => 4,
389 rmapbufs => 4,
390 ft => 0,
390 ft => 0,
391 netlist => 0,
391 netlist => 0,
392 ports => 2,
392 ports => 2,
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 memtech => apa3e,
394 memtech => apa3e,
395 destkey => 2,
395 destkey => 2,
396 spwcore => 1
396 spwcore => 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 )
400 )
401 PORT MAP(reset, clk_25, spw_rxclk(0),
401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 swni, swno);
404 swni, swno);
405
405
406 swni.tickin <= '0';
406 swni.tickin <= '0';
407 swni.rmapen <= '1';
407 swni.rmapen <= '1';
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 swni.tickinraw <= '0';
409 swni.tickinraw <= '0';
410 swni.timein <= (OTHERS => '0');
410 swni.timein <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
413
413
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
417 lpp_lfr_1 : lpp_lfr
417 lpp_lfr_1 : lpp_lfr
418 GENERIC MAP (
418 GENERIC MAP (
419 Mem_use => use_RAM,
419 Mem_use => use_RAM,
420 nb_data_by_buffer_size => 32,
420 nb_data_by_buffer_size => 32,
421 nb_word_by_buffer_size => 30,
421 nb_word_by_buffer_size => 30,
422 nb_snapshot_param_size => 32,
422 nb_snapshot_param_size => 32,
423 delta_vector_size => 32,
423 delta_vector_size => 32,
424 delta_vector_size_f0_2 => 7, -- log2(96)
424 delta_vector_size_f0_2 => 7, -- log2(96)
425 pindex => 15,
425 pindex => 15,
426 paddr => 15,
426 paddr => 15,
427 pmask => 16#fff#,
427 pmask => 16#fff#,
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"000114") -- aa.bb.cc version
431 top_lfr_version => X"000115") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
435 sample_B => sample_s(2 DOWNTO 0),
435 sample_B => sample_s(2 DOWNTO 0),
436 sample_E => sample_s(7 DOWNTO 3),
436 sample_E => sample_s(7 DOWNTO 3),
437 sample_val => sample_val,
437 sample_val => sample_val,
438 apbi => apbi_ext,
438 apbi => apbi_ext,
439 apbo => apbo_ext(15),
439 apbo => apbo_ext(15),
440 ahbi => ahbi_m_ext,
440 ahbi => ahbi_m_ext,
441 ahbo => ahbo_m_ext(2),
441 ahbo => ahbo_m_ext(2),
442 coarse_time => coarse_time,
442 coarse_time => coarse_time,
443 fine_time => fine_time,
443 fine_time => fine_time,
444 data_shaping_BW => bias_fail_sw_sig,
444 data_shaping_BW => bias_fail_sw_sig,
445 observation_vector_0=> observation_vector_0,
445 observation_vector_0=> observation_vector_0,
446 observation_vector_1 => observation_vector_1,
446 observation_vector_1 => observation_vector_1,
447 observation_reg => observation_reg);
447 observation_reg => observation_reg);
448
448
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
451 END GENERATE all_sample;
451 END GENERATE all_sample;
452
452
453
453
454
454
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
456 GENERIC MAP(
456 GENERIC MAP(
457 ChannelCount => 8,
457 ChannelCount => 8,
458 SampleNbBits => 14,
458 SampleNbBits => 14,
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
461 PORT MAP (
461 PORT MAP (
462 -- CONV
462 -- CONV
463 cnv_clk => clk_24,
463 cnv_clk => clk_24,
464 cnv_rstn => reset,
464 cnv_rstn => reset,
465 cnv => ADC_nCS_sig,
465 cnv => ADC_nCS_sig,
466 -- DATA
466 -- DATA
467 clk => clk_25,
467 clk => clk_25,
468 rstn => reset,
468 rstn => reset,
469 sck => ADC_CLK_sig,
469 sck => ADC_CLK_sig,
470 sdo => ADC_SDO_sig,
470 sdo => ADC_SDO_sig,
471 -- SAMPLE
471 -- SAMPLE
472 sample => sample,
472 sample => sample,
473 sample_val => sample_val);
473 sample_val => sample_val);
474
474
475 --IO10 <= ADC_SDO_sig(5);
475 --IO10 <= ADC_SDO_sig(5);
476 --IO9 <= ADC_SDO_sig(4);
476 --IO9 <= ADC_SDO_sig(4);
477 --IO8 <= ADC_SDO_sig(3);
477 --IO8 <= ADC_SDO_sig(3);
478
478
479 ADC_nCS <= ADC_nCS_sig;
479 ADC_nCS <= ADC_nCS_sig;
480 ADC_CLK <= ADC_CLK_sig;
480 ADC_CLK <= ADC_CLK_sig;
481 ADC_SDO_sig <= ADC_SDO;
481 ADC_SDO_sig <= ADC_SDO;
482
482
483 ----------------------------------------------------------------------
483 ----------------------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
485 ----------------------------------------------------------------------
485 ----------------------------------------------------------------------
486
486
487 grgpio0 : grgpio
487 grgpio0 : grgpio
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
490
490
491 --pio_pad_0 : iopad
491 --pio_pad_0 : iopad
492 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
494 --pio_pad_1 : iopad
494 --pio_pad_1 : iopad
495 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
497 --pio_pad_2 : iopad
497 --pio_pad_2 : iopad
498 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
500 --pio_pad_3 : iopad
500 --pio_pad_3 : iopad
501 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
503 --pio_pad_4 : iopad
503 --pio_pad_4 : iopad
504 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- GENERIC MAP (tech => CFG_PADTECH)
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
506 --pio_pad_5 : iopad
506 --pio_pad_5 : iopad
507 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- GENERIC MAP (tech => CFG_PADTECH)
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
509 --pio_pad_6 : iopad
509 --pio_pad_6 : iopad
510 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- GENERIC MAP (tech => CFG_PADTECH)
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
512 --pio_pad_7 : iopad
512 --pio_pad_7 : iopad
513 -- GENERIC MAP (tech => CFG_PADTECH)
513 -- GENERIC MAP (tech => CFG_PADTECH)
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
515
515
516 PROCESS (clk_25, reset)
516 PROCESS (clk_25, reset)
517 BEGIN -- PROCESS
517 BEGIN -- PROCESS
518 IF reset = '0' THEN -- asynchronous reset (active low)
518 IF reset = '0' THEN -- asynchronous reset (active low)
519 IO0 <= '0';
519 IO0 <= '0';
520 IO1 <= '0';
520 IO1 <= '0';
521 IO2 <= '0';
521 IO2 <= '0';
522 IO3 <= '0';
522 IO3 <= '0';
523 IO4 <= '0';
523 IO4 <= '0';
524 IO5 <= '0';
524 IO5 <= '0';
525 IO6 <= '0';
525 IO6 <= '0';
526 IO7 <= '0';
526 IO7 <= '0';
527 IO8 <= '0';
527 IO8 <= '0';
528 IO9 <= '0';
528 IO9 <= '0';
529 IO10 <= '0';
529 IO10 <= '0';
530 IO11 <= '0';
530 IO11 <= '0';
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
532 CASE gpioo.dout(2 DOWNTO 0) IS
532 CASE gpioo.dout(2 DOWNTO 0) IS
533 WHEN "011" =>
533 WHEN "011" =>
534 IO0 <= observation_reg(0 );
534 IO0 <= observation_reg(0 );
535 IO1 <= observation_reg(1 );
535 IO1 <= observation_reg(1 );
536 IO2 <= observation_reg(2 );
536 IO2 <= observation_reg(2 );
537 IO3 <= observation_reg(3 );
537 IO3 <= observation_reg(3 );
538 IO4 <= observation_reg(4 );
538 IO4 <= observation_reg(4 );
539 IO5 <= observation_reg(5 );
539 IO5 <= observation_reg(5 );
540 IO6 <= observation_reg(6 );
540 IO6 <= observation_reg(6 );
541 IO7 <= observation_reg(7 );
541 IO7 <= observation_reg(7 );
542 IO8 <= observation_reg(8 );
542 IO8 <= observation_reg(8 );
543 IO9 <= observation_reg(9 );
543 IO9 <= observation_reg(9 );
544 IO10 <= observation_reg(10);
544 IO10 <= observation_reg(10);
545 IO11 <= observation_reg(11);
545 IO11 <= observation_reg(11);
546 WHEN "001" =>
546 WHEN "001" =>
547 IO0 <= observation_reg(0 + 12);
547 IO0 <= observation_reg(0 + 12);
548 IO1 <= observation_reg(1 + 12);
548 IO1 <= observation_reg(1 + 12);
549 IO2 <= observation_reg(2 + 12);
549 IO2 <= observation_reg(2 + 12);
550 IO3 <= observation_reg(3 + 12);
550 IO3 <= observation_reg(3 + 12);
551 IO4 <= observation_reg(4 + 12);
551 IO4 <= observation_reg(4 + 12);
552 IO5 <= observation_reg(5 + 12);
552 IO5 <= observation_reg(5 + 12);
553 IO6 <= observation_reg(6 + 12);
553 IO6 <= observation_reg(6 + 12);
554 IO7 <= observation_reg(7 + 12);
554 IO7 <= observation_reg(7 + 12);
555 IO8 <= observation_reg(8 + 12);
555 IO8 <= observation_reg(8 + 12);
556 IO9 <= observation_reg(9 + 12);
556 IO9 <= observation_reg(9 + 12);
557 IO10 <= observation_reg(10 + 12);
557 IO10 <= observation_reg(10 + 12);
558 IO11 <= observation_reg(11 + 12);
558 IO11 <= observation_reg(11 + 12);
559 WHEN "010" =>
559 WHEN "010" =>
560 IO0 <= observation_reg(0 + 12 + 12);
560 IO0 <= observation_reg(0 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
568 IO8 <= '0';
568 IO8 <= '0';
569 IO9 <= '0';
569 IO9 <= '0';
570 IO10 <= '0';
570 IO10 <= '0';
571 IO11 <= '0';
571 IO11 <= '0';
572 WHEN "000" =>
572 WHEN "000" =>
573 IO0 <= observation_vector_0(0 );
573 IO0 <= observation_vector_0(0 );
574 IO1 <= observation_vector_0(1 );
574 IO1 <= observation_vector_0(1 );
575 IO2 <= observation_vector_0(2 );
575 IO2 <= observation_vector_0(2 );
576 IO3 <= observation_vector_0(3 );
576 IO3 <= observation_vector_0(3 );
577 IO4 <= observation_vector_0(4 );
577 IO4 <= observation_vector_0(4 );
578 IO5 <= observation_vector_0(5 );
578 IO5 <= observation_vector_0(5 );
579 IO6 <= observation_vector_0(6 );
579 IO6 <= observation_vector_0(6 );
580 IO7 <= observation_vector_0(7 );
580 IO7 <= observation_vector_0(7 );
581 IO8 <= observation_vector_0(8 );
581 IO8 <= observation_vector_0(8 );
582 IO9 <= observation_vector_0(9 );
582 IO9 <= observation_vector_0(9 );
583 IO10 <= observation_vector_0(10);
583 IO10 <= observation_vector_0(10);
584 IO11 <= observation_vector_0(11);
584 IO11 <= observation_vector_0(11);
585 WHEN "100" =>
585 WHEN "100" =>
586 IO0 <= observation_vector_1(0 );
586 IO0 <= observation_vector_1(0 );
587 IO1 <= observation_vector_1(1 );
587 IO1 <= observation_vector_1(1 );
588 IO2 <= observation_vector_1(2 );
588 IO2 <= observation_vector_1(2 );
589 IO3 <= observation_vector_1(3 );
589 IO3 <= observation_vector_1(3 );
590 IO4 <= observation_vector_1(4 );
590 IO4 <= observation_vector_1(4 );
591 IO5 <= observation_vector_1(5 );
591 IO5 <= observation_vector_1(5 );
592 IO6 <= observation_vector_1(6 );
592 IO6 <= observation_vector_1(6 );
593 IO7 <= observation_vector_1(7 );
593 IO7 <= observation_vector_1(7 );
594 IO8 <= observation_vector_1(8 );
594 IO8 <= observation_vector_1(8 );
595 IO9 <= observation_vector_1(9 );
595 IO9 <= observation_vector_1(9 );
596 IO10 <= observation_vector_1(10);
596 IO10 <= observation_vector_1(10);
597 IO11 <= observation_vector_1(11);
597 IO11 <= observation_vector_1(11);
598 WHEN OTHERS => NULL;
598 WHEN OTHERS => NULL;
599 END CASE;
599 END CASE;
600
600
601 END IF;
601 END IF;
602 END PROCESS;
602 END PROCESS;
603
603
604 END beh;
604 END beh;
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@@ -1,996 +1,1009
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
15 USE lpp.fft_components.ALL;
16
16
17 ENTITY lpp_lfr_ms IS
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
19 Mem_use : INTEGER := use_RAM
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
24
25 ---------------------------------------------------------------------------
25 ---------------------------------------------------------------------------
26 -- DATA INPUT
26 -- DATA INPUT
27 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
28 -- TIME
28 -- TIME
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 --
31 --
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
34 --
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- DMA
42 -- DMA
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 dma_valid : OUT STD_LOGIC;
46 dma_valid : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
50
50
51 -- Reg out
51 -- Reg out
52 ready_matrix_f0 : OUT STD_LOGIC;
52 ready_matrix_f0 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58
58
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 --
60 --
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63
63
64 -- Reg In
64 -- Reg In
65 status_ready_matrix_f0 : IN STD_LOGIC;
65 status_ready_matrix_f0 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
68
68
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
78
78
79 );
79 );
80 END;
80 END;
81
81
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83
83
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89
89
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95
95
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100
100
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102
102
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107
107
108 SIGNAL error_wen_f0 : STD_LOGIC;
108 SIGNAL error_wen_f0 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
111
111
112 SIGNAL one_sample_f1_full : STD_LOGIC;
112 SIGNAL one_sample_f1_full : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
116
116
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 -- FSM / SWITCH SELECT CHANNEL
118 -- FSM / SWITCH SELECT CHANNEL
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123
123
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128
128
129 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 -- FSM LOAD FFT
130 -- FSM LOAD FFT
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135
135
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 SIGNAL sample_load : STD_LOGIC;
137 SIGNAL sample_load : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141
141
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- FFT
144 -- FFT
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 SIGNAL fft_read : STD_LOGIC;
146 SIGNAL fft_read : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_valid : STD_LOGIC;
150 SIGNAL fft_data_valid : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 SIGNAL current_fifo_empty : STD_LOGIC;
158 SIGNAL current_fifo_empty : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162
162
163 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176
176
177 SIGNAL SM_correlation_start : STD_LOGIC;
177 SIGNAL SM_correlation_start : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
184
184
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188
188
189 SIGNAL current_matrix_write : STD_LOGIC;
189 SIGNAL current_matrix_write : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 SIGNAL fifo_0_ready : STD_LOGIC;
192 SIGNAL fifo_0_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
195
195
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
207
207
208 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
209 -- TIME REG & INFOs
209 -- TIME REG & INFOs
210 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212
212
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
217
217
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222
222
223 --SIGNAL time_update_f0_A : STD_LOGIC;
223 --SIGNAL time_update_f0_A : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
227 --
227 --
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
231
231
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237 SIGNAL fft_ongoing_counter : STD_LOGIC_VECTOR(1 DOWNTO 0);
237 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
238
238
239 SIGNAL fft_ready_reg : STD_LOGIC;
239 SIGNAL fft_ready_reg : STD_LOGIC;
240 SIGNAL fft_ready_rising_down : STD_LOGIC;
240 SIGNAL fft_ready_rising_down : STD_LOGIC;
241
241
242 SIGNAL sample_load_reg : STD_LOGIC;
242 SIGNAL sample_load_reg : STD_LOGIC;
243 SIGNAL sample_load_rising_down : STD_LOGIC;
243 SIGNAL sample_load_rising_down : STD_LOGIC;
244
244
245 BEGIN
245 BEGIN
246
246
247
247
248 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
248 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
249
249
250
250
251 switch_f0_inst : spectral_matrix_switch_f0
251 switch_f0_inst : spectral_matrix_switch_f0
252 PORT MAP (
252 PORT MAP (
253 clk => clk,
253 clk => clk,
254 rstn => rstn,
254 rstn => rstn,
255
255
256 sample_wen => sample_f0_wen,
256 sample_wen => sample_f0_wen,
257
257
258 fifo_A_empty => sample_f0_A_empty,
258 fifo_A_empty => sample_f0_A_empty,
259 fifo_A_full => sample_f0_A_full,
259 fifo_A_full => sample_f0_A_full,
260 fifo_A_wen => sample_f0_A_wen,
260 fifo_A_wen => sample_f0_A_wen,
261
261
262 fifo_B_empty => sample_f0_B_empty,
262 fifo_B_empty => sample_f0_B_empty,
263 fifo_B_full => sample_f0_B_full,
263 fifo_B_full => sample_f0_B_full,
264 fifo_B_wen => sample_f0_B_wen,
264 fifo_B_wen => sample_f0_B_wen,
265
265
266 error_wen => error_wen_f0); -- TODO
266 error_wen => error_wen_f0); -- TODO
267
267
268 -----------------------------------------------------------------------------
268 -----------------------------------------------------------------------------
269 -- FIFO IN
269 -- FIFO IN
270 -----------------------------------------------------------------------------
270 -----------------------------------------------------------------------------
271 lppFIFOxN_f0_a : lppFIFOxN
271 lppFIFOxN_f0_a : lppFIFOxN
272 GENERIC MAP (
272 GENERIC MAP (
273 tech => 0,
273 tech => 0,
274 Mem_use => Mem_use,
274 Mem_use => Mem_use,
275 Data_sz => 16,
275 Data_sz => 16,
276 Addr_sz => 8,
276 Addr_sz => 8,
277 FifoCnt => 5)
277 FifoCnt => 5)
278 PORT MAP (
278 PORT MAP (
279 clk => clk,
279 clk => clk,
280 rstn => rstn,
280 rstn => rstn,
281
281
282 ReUse => (OTHERS => '0'),
282 ReUse => (OTHERS => '0'),
283
283
284 wen => sample_f0_A_wen,
284 wen => sample_f0_A_wen,
285 wdata => sample_f0_wdata,
285 wdata => sample_f0_wdata,
286
286
287 ren => sample_f0_A_ren,
287 ren => sample_f0_A_ren,
288 rdata => sample_f0_A_rdata,
288 rdata => sample_f0_A_rdata,
289
289
290 empty => sample_f0_A_empty,
290 empty => sample_f0_A_empty,
291 full => sample_f0_A_full,
291 full => sample_f0_A_full,
292 almost_full => OPEN);
292 almost_full => OPEN);
293
293
294 lppFIFOxN_f0_b : lppFIFOxN
294 lppFIFOxN_f0_b : lppFIFOxN
295 GENERIC MAP (
295 GENERIC MAP (
296 tech => 0,
296 tech => 0,
297 Mem_use => Mem_use,
297 Mem_use => Mem_use,
298 Data_sz => 16,
298 Data_sz => 16,
299 Addr_sz => 8,
299 Addr_sz => 8,
300 FifoCnt => 5)
300 FifoCnt => 5)
301 PORT MAP (
301 PORT MAP (
302 clk => clk,
302 clk => clk,
303 rstn => rstn,
303 rstn => rstn,
304
304
305 ReUse => (OTHERS => '0'),
305 ReUse => (OTHERS => '0'),
306
306
307 wen => sample_f0_B_wen,
307 wen => sample_f0_B_wen,
308 wdata => sample_f0_wdata,
308 wdata => sample_f0_wdata,
309 ren => sample_f0_B_ren,
309 ren => sample_f0_B_ren,
310 rdata => sample_f0_B_rdata,
310 rdata => sample_f0_B_rdata,
311 empty => sample_f0_B_empty,
311 empty => sample_f0_B_empty,
312 full => sample_f0_B_full,
312 full => sample_f0_B_full,
313 almost_full => OPEN);
313 almost_full => OPEN);
314
314
315 -----------------------------------------------------------------------------
316 -- sample_f1_wen in
317 -- sample_f1_wdata in
318 -- sample_f1_full OUT
319
320
321
322
315 lppFIFOxN_f1 : lppFIFOxN
323 lppFIFOxN_f1 : lppFIFOxN
316 GENERIC MAP (
324 GENERIC MAP (
317 tech => 0,
325 tech => 0,
318 Mem_use => Mem_use,
326 Mem_use => Mem_use,
319 Data_sz => 16,
327 Data_sz => 16,
320 Addr_sz => 8,
328 Addr_sz => 8,
321 FifoCnt => 5)
329 FifoCnt => 5)
322 PORT MAP (
330 PORT MAP (
323 clk => clk,
331 clk => clk,
324 rstn => rstn,
332 rstn => rstn,
325
333
326 ReUse => (OTHERS => '0'),
334 ReUse => (OTHERS => '0'),
327
335
328 wen => sample_f1_wen,
336 wen => sample_f1_wen,
329 wdata => sample_f1_wdata,
337 wdata => sample_f1_wdata,
330 ren => sample_f1_ren,
338 ren => sample_f1_ren,
331 rdata => sample_f1_rdata,
339 rdata => sample_f1_rdata,
332 empty => sample_f1_empty,
340 empty => sample_f1_empty,
333 full => sample_f1_full,
341 full => sample_f1_full,
334 almost_full => sample_f1_almost_full);
342 almost_full => sample_f1_almost_full);
335
343
336
344
337 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
345 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
338
346
339 PROCESS (clk, rstn)
347 PROCESS (clk, rstn)
340 BEGIN -- PROCESS
348 BEGIN -- PROCESS
341 IF rstn = '0' THEN -- asynchronous reset (active low)
349 IF rstn = '0' THEN -- asynchronous reset (active low)
342 one_sample_f1_full <= '0';
350 one_sample_f1_full <= '0';
343 error_wen_f1 <= '0';
351 error_wen_f1 <= '0';
344 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
352 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
345 IF sample_f1_full = "00000" THEN
353 IF sample_f1_full = "00000" THEN
346 one_sample_f1_full <= '0';
354 one_sample_f1_full <= '0';
347 ELSE
355 ELSE
348 one_sample_f1_full <= '1';
356 one_sample_f1_full <= '1';
349 END IF;
357 END IF;
350 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
358 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
351 END IF;
359 END IF;
352 END PROCESS;
360 END PROCESS;
353
361
362 -----------------------------------------------------------------------------
363
354
364
355 lppFIFOxN_f2 : lppFIFOxN
365 lppFIFOxN_f2 : lppFIFOxN
356 GENERIC MAP (
366 GENERIC MAP (
357 tech => 0,
367 tech => 0,
358 Mem_use => Mem_use,
368 Mem_use => Mem_use,
359 Data_sz => 16,
369 Data_sz => 16,
360 Addr_sz => 8,
370 Addr_sz => 8,
361 FifoCnt => 5)
371 FifoCnt => 5)
362 PORT MAP (
372 PORT MAP (
363 clk => clk,
373 clk => clk,
364 rstn => rstn,
374 rstn => rstn,
365
375
366 ReUse => (OTHERS => '0'),
376 ReUse => (OTHERS => '0'),
367
377
368 wen => sample_f2_wen,
378 wen => sample_f2_wen,
369 wdata => sample_f2_wdata,
379 wdata => sample_f2_wdata,
370 ren => sample_f2_ren,
380 ren => sample_f2_ren,
371 rdata => sample_f2_rdata,
381 rdata => sample_f2_rdata,
372 empty => sample_f2_empty,
382 empty => sample_f2_empty,
373 full => sample_f2_full,
383 full => sample_f2_full,
374 almost_full => OPEN);
384 almost_full => OPEN);
375
385
376
386
377 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
387 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
378
388
379 PROCESS (clk, rstn)
389 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
390 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
391 IF rstn = '0' THEN -- asynchronous reset (active low)
382 one_sample_f2_full <= '0';
392 one_sample_f2_full <= '0';
383 error_wen_f2 <= '0';
393 error_wen_f2 <= '0';
384 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
394 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
385 IF sample_f2_full = "00000" THEN
395 IF sample_f2_full = "00000" THEN
386 one_sample_f2_full <= '0';
396 one_sample_f2_full <= '0';
387 ELSE
397 ELSE
388 one_sample_f2_full <= '1';
398 one_sample_f2_full <= '1';
389 END IF;
399 END IF;
390 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
400 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
391 END IF;
401 END IF;
392 END PROCESS;
402 END PROCESS;
393
403
394 -----------------------------------------------------------------------------
404 -----------------------------------------------------------------------------
395 -- FSM SELECT CHANNEL
405 -- FSM SELECT CHANNEL
396 -----------------------------------------------------------------------------
406 -----------------------------------------------------------------------------
397 PROCESS (clk, rstn)
407 PROCESS (clk, rstn)
398 BEGIN
408 BEGIN
399 IF rstn = '0' THEN
409 IF rstn = '0' THEN
400 state_fsm_select_channel <= IDLE;
410 state_fsm_select_channel <= IDLE;
401 ELSIF clk'EVENT AND clk = '1' THEN
411 ELSIF clk'EVENT AND clk = '1' THEN
402 CASE state_fsm_select_channel IS
412 CASE state_fsm_select_channel IS
403 WHEN IDLE =>
413 WHEN IDLE =>
404 IF sample_f1_full = "11111" THEN
414 IF sample_f1_full = "11111" THEN
405 state_fsm_select_channel <= SWITCH_F1;
415 state_fsm_select_channel <= SWITCH_F1;
406 ELSIF sample_f1_almost_full = "00000" THEN
416 ELSIF sample_f1_almost_full = "00000" THEN
407 IF sample_f0_A_full = "11111" THEN
417 IF sample_f0_A_full = "11111" THEN
408 state_fsm_select_channel <= SWITCH_F0_A;
418 state_fsm_select_channel <= SWITCH_F0_A;
409 ELSIF sample_f0_B_full = "11111" THEN
419 ELSIF sample_f0_B_full = "11111" THEN
410 state_fsm_select_channel <= SWITCH_F0_B;
420 state_fsm_select_channel <= SWITCH_F0_B;
411 ELSIF sample_f2_full = "11111" THEN
421 ELSIF sample_f2_full = "11111" THEN
412 state_fsm_select_channel <= SWITCH_F2;
422 state_fsm_select_channel <= SWITCH_F2;
413 END IF;
423 END IF;
414 END IF;
424 END IF;
415
425
416 WHEN SWITCH_F0_A =>
426 WHEN SWITCH_F0_A =>
417 IF sample_f0_A_empty = "11111" THEN
427 IF sample_f0_A_empty = "11111" THEN
418 state_fsm_select_channel <= IDLE;
428 state_fsm_select_channel <= IDLE;
419 END IF;
429 END IF;
420 WHEN SWITCH_F0_B =>
430 WHEN SWITCH_F0_B =>
421 IF sample_f0_B_empty = "11111" THEN
431 IF sample_f0_B_empty = "11111" THEN
422 state_fsm_select_channel <= IDLE;
432 state_fsm_select_channel <= IDLE;
423 END IF;
433 END IF;
424 WHEN SWITCH_F1 =>
434 WHEN SWITCH_F1 =>
425 IF sample_f1_empty = "11111" THEN
435 IF sample_f1_empty = "11111" THEN
426 state_fsm_select_channel <= IDLE;
436 state_fsm_select_channel <= IDLE;
427 END IF;
437 END IF;
428 WHEN SWITCH_F2 =>
438 WHEN SWITCH_F2 =>
429 IF sample_f2_empty = "11111" THEN
439 IF sample_f2_empty = "11111" THEN
430 state_fsm_select_channel <= IDLE;
440 state_fsm_select_channel <= IDLE;
431 END IF;
441 END IF;
432 WHEN OTHERS => NULL;
442 WHEN OTHERS => NULL;
433 END CASE;
443 END CASE;
434
444
435 END IF;
445 END IF;
436 END PROCESS;
446 END PROCESS;
437
447
438 PROCESS (clk, rstn)
448 PROCESS (clk, rstn)
439 BEGIN
449 BEGIN
440 IF rstn = '0' THEN
450 IF rstn = '0' THEN
441 pre_state_fsm_select_channel <= IDLE;
451 pre_state_fsm_select_channel <= IDLE;
442 ELSIF clk'EVENT AND clk = '1' THEN
452 ELSIF clk'EVENT AND clk = '1' THEN
443 pre_state_fsm_select_channel <= state_fsm_select_channel;
453 pre_state_fsm_select_channel <= state_fsm_select_channel;
444 END IF;
454 END IF;
445 END PROCESS;
455 END PROCESS;
446
456
447
457
448 -----------------------------------------------------------------------------
458 -----------------------------------------------------------------------------
449 -- SWITCH SELECT CHANNEL
459 -- SWITCH SELECT CHANNEL
450 -----------------------------------------------------------------------------
460 -----------------------------------------------------------------------------
451 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
461 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
452 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
462 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
453 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
463 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
454 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
464 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
455 (OTHERS => '1');
465 (OTHERS => '1');
456
466
457 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
467 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
458 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
468 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
459 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
469 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
460 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
470 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
461 (OTHERS => '0');
471 (OTHERS => '0');
462
472
463 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
473 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
464 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
474 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
465 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
475 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
466 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
476 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
467
477
468
478
469 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
479 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
470 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
480 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
471 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
481 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
472 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
482 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
473
483
474
484
475 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
485 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
476 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
486 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
477 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
487 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
478 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
488 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
479
489
480 -----------------------------------------------------------------------------
490 -----------------------------------------------------------------------------
481 -- FSM LOAD FFT
491 -- FSM LOAD FFT
482 -----------------------------------------------------------------------------
492 -----------------------------------------------------------------------------
483
493
484 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = "10" ELSE
494 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
485 sample_ren_s WHEN sample_load = '1' ELSE
495 sample_ren_s WHEN sample_load = '1' ELSE
486 (OTHERS => '1');
496 (OTHERS => '1');
487
497
488 PROCESS (clk, rstn)
498 PROCESS (clk, rstn)
489 BEGIN
499 BEGIN
490 IF rstn = '0' THEN
500 IF rstn = '0' THEN
491 sample_ren_s <= (OTHERS => '1');
501 sample_ren_s <= (OTHERS => '1');
492 state_fsm_load_FFT <= IDLE;
502 state_fsm_load_FFT <= IDLE;
493 status_MS_input <= (OTHERS => '0');
503 status_MS_input <= (OTHERS => '0');
494 --next_state_fsm_load_FFT <= IDLE;
504 --next_state_fsm_load_FFT <= IDLE;
495 --sample_valid <= '0';
505 --sample_valid <= '0';
496 ELSIF clk'EVENT AND clk = '1' THEN
506 ELSIF clk'EVENT AND clk = '1' THEN
497 CASE state_fsm_load_FFT IS
507 CASE state_fsm_load_FFT IS
498 WHEN IDLE =>
508 WHEN IDLE =>
499 --sample_valid <= '0';
509 --sample_valid <= '0';
500 sample_ren_s <= (OTHERS => '1');
510 sample_ren_s <= (OTHERS => '1');
501 IF sample_full = "11111" AND sample_load = '1' THEN
511 IF sample_full = "11111" AND sample_load = '1' THEN
502 state_fsm_load_FFT <= FIFO_1;
512 state_fsm_load_FFT <= FIFO_1;
503 status_MS_input <= status_channel;
513 status_MS_input <= status_channel;
504 END IF;
514 END IF;
505
515
506 WHEN FIFO_1 =>
516 WHEN FIFO_1 =>
507 sample_ren_s <= "1111" & NOT(sample_load);
517 sample_ren_s <= "1111" & NOT(sample_load);
508 IF sample_empty(0) = '1' THEN
518 IF sample_empty(0) = '1' THEN
509 sample_ren_s <= (OTHERS => '1');
519 sample_ren_s <= (OTHERS => '1');
510 state_fsm_load_FFT <= FIFO_2;
520 state_fsm_load_FFT <= FIFO_2;
511 END IF;
521 END IF;
512
522
513 WHEN FIFO_2 =>
523 WHEN FIFO_2 =>
514 sample_ren_s <= "111" & NOT(sample_load) & '1';
524 sample_ren_s <= "111" & NOT(sample_load) & '1';
515 IF sample_empty(1) = '1' THEN
525 IF sample_empty(1) = '1' THEN
516 sample_ren_s <= (OTHERS => '1');
526 sample_ren_s <= (OTHERS => '1');
517 state_fsm_load_FFT <= FIFO_3;
527 state_fsm_load_FFT <= FIFO_3;
518 END IF;
528 END IF;
519
529
520 WHEN FIFO_3 =>
530 WHEN FIFO_3 =>
521 sample_ren_s <= "11" & NOT(sample_load) & "11";
531 sample_ren_s <= "11" & NOT(sample_load) & "11";
522 IF sample_empty(2) = '1' THEN
532 IF sample_empty(2) = '1' THEN
523 sample_ren_s <= (OTHERS => '1');
533 sample_ren_s <= (OTHERS => '1');
524 state_fsm_load_FFT <= FIFO_4;
534 state_fsm_load_FFT <= FIFO_4;
525 END IF;
535 END IF;
526
536
527 WHEN FIFO_4 =>
537 WHEN FIFO_4 =>
528 sample_ren_s <= '1' & NOT(sample_load) & "111";
538 sample_ren_s <= '1' & NOT(sample_load) & "111";
529 IF sample_empty(3) = '1' THEN
539 IF sample_empty(3) = '1' THEN
530 sample_ren_s <= (OTHERS => '1');
540 sample_ren_s <= (OTHERS => '1');
531 state_fsm_load_FFT <= FIFO_5;
541 state_fsm_load_FFT <= FIFO_5;
532 END IF;
542 END IF;
533
543
534 WHEN FIFO_5 =>
544 WHEN FIFO_5 =>
535 sample_ren_s <= NOT(sample_load) & "1111";
545 sample_ren_s <= NOT(sample_load) & "1111";
536 IF sample_empty(4) = '1' THEN
546 IF sample_empty(4) = '1' THEN
537 sample_ren_s <= (OTHERS => '1');
547 sample_ren_s <= (OTHERS => '1');
538 state_fsm_load_FFT <= IDLE;
548 state_fsm_load_FFT <= IDLE;
539 END IF;
549 END IF;
540 WHEN OTHERS => NULL;
550 WHEN OTHERS => NULL;
541 END CASE;
551 END CASE;
542 END IF;
552 END IF;
543 END PROCESS;
553 END PROCESS;
544
554
545 PROCESS (clk, rstn)
555 PROCESS (clk, rstn)
546 BEGIN
556 BEGIN
547 IF rstn = '0' THEN
557 IF rstn = '0' THEN
548 sample_valid_r <= '0';
558 sample_valid_r <= '0';
549 next_state_fsm_load_FFT <= IDLE;
559 next_state_fsm_load_FFT <= IDLE;
550 ELSIF clk'EVENT AND clk = '1' THEN
560 ELSIF clk'EVENT AND clk = '1' THEN
551 next_state_fsm_load_FFT <= state_fsm_load_FFT;
561 next_state_fsm_load_FFT <= state_fsm_load_FFT;
552 IF sample_ren_s = "11111" THEN
562 IF sample_ren_s = "11111" THEN
553 sample_valid_r <= '0';
563 sample_valid_r <= '0';
554 ELSE
564 ELSE
555 sample_valid_r <= '1';
565 sample_valid_r <= '1';
556 END IF;
566 END IF;
557 END IF;
567 END IF;
558 END PROCESS;
568 END PROCESS;
559
569
560 sample_valid <= '0' WHEN fft_ongoing_counter = "10" ELSE sample_valid_r AND sample_load;
570 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
561
571
562 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
572 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
563 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
573 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
564 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
574 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
565 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
575 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
566 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
576 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
567
577
568 -----------------------------------------------------------------------------
578 -----------------------------------------------------------------------------
569 -- FFT
579 -- FFT
570 -----------------------------------------------------------------------------
580 -----------------------------------------------------------------------------
571 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
581 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
572 PORT MAP (
582 PORT MAP (
573 clk => clk,
583 clk => clk,
574 rstn => rstn,
584 rstn => rstn,
575 sample_valid => sample_valid,
585 sample_valid => sample_valid,
576 fft_read => fft_read,
586 fft_read => fft_read,
577 sample_data => sample_data,
587 sample_data => sample_data,
578 sample_load => sample_load,
588 sample_load => sample_load,
579 fft_pong => fft_pong,
589 fft_pong => fft_pong,
580 fft_data_im => fft_data_im,
590 fft_data_im => fft_data_im,
581 fft_data_re => fft_data_re,
591 fft_data_re => fft_data_re,
582 fft_data_valid => fft_data_valid,
592 fft_data_valid => fft_data_valid,
583 fft_ready => fft_ready);
593 fft_ready => fft_ready);
584
594
585 observation_vector_0(11 DOWNTO 0) <= "00" & --11 10
595 observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
586 fft_ongoing_counter & --9 8
596 fft_ongoing_counter & --9 8
587 sample_load_rising_down & --7
597 sample_load_rising_down & --7
588 fft_ready_rising_down & --6
598 fft_ready_rising_down & --6
589 fft_ready & --5
599 fft_ready & --5
590 fft_data_valid & --4
600 fft_data_valid & --4
591 fft_pong & --3
601 fft_pong & --3
592 sample_load & --2
602 sample_load & --2
593 fft_read & --1
603 fft_read & --1
594 sample_valid; --0
604 sample_valid; --0
595
605
596 -----------------------------------------------------------------------------
606 -----------------------------------------------------------------------------
597 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
607 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
598 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
608 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
599
609
600 PROCESS (clk, rstn)
610 PROCESS (clk, rstn)
601 BEGIN
611 BEGIN
602 IF rstn = '0' THEN
612 IF rstn = '0' THEN
603 fft_ready_reg <= '0';
613 fft_ready_reg <= '0';
604 sample_load_reg <= '0';
614 sample_load_reg <= '0';
605
615
606 fft_ongoing_counter <= "00";
616 fft_ongoing_counter <= '0';
607 ELSIF clk'event AND clk = '1' THEN
617 ELSIF clk'event AND clk = '1' THEN
608 fft_ready_reg <= fft_ready;
618 fft_ready_reg <= fft_ready;
609 sample_load_reg <= sample_load;
619 sample_load_reg <= sample_load;
610
620
611 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
621 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
612 CASE fft_ongoing_counter IS
622 fft_ongoing_counter <= '0';
613 WHEN "01" => fft_ongoing_counter <= "00";
623
614 WHEN "10" => fft_ongoing_counter <= "01";
624 -- CASE fft_ongoing_counter IS
615 WHEN OTHERS => NULL;
625 -- WHEN "01" => fft_ongoing_counter <= "00";
616 END CASE;
626 ---- WHEN "10" => fft_ongoing_counter <= "01";
627 -- WHEN OTHERS => NULL;
628 -- END CASE;
617 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
629 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
618 CASE fft_ongoing_counter IS
630 fft_ongoing_counter <= '1';
619 WHEN "00" => fft_ongoing_counter <= "01";
631 -- CASE fft_ongoing_counter IS
620 WHEN "01" => fft_ongoing_counter <= "10";
632 -- WHEN "00" => fft_ongoing_counter <= "01";
621 WHEN OTHERS => NULL;
633 ---- WHEN "01" => fft_ongoing_counter <= "10";
622 END CASE;
634 -- WHEN OTHERS => NULL;
635 -- END CASE;
623 END IF;
636 END IF;
624
637
625 END IF;
638 END IF;
626 END PROCESS;
639 END PROCESS;
627
640
628 -----------------------------------------------------------------------------
641 -----------------------------------------------------------------------------
629 PROCESS (clk, rstn)
642 PROCESS (clk, rstn)
630 BEGIN
643 BEGIN
631 IF rstn = '0' THEN
644 IF rstn = '0' THEN
632 state_fsm_load_MS_memory <= IDLE;
645 state_fsm_load_MS_memory <= IDLE;
633 current_fifo_load <= "00001";
646 current_fifo_load <= "00001";
634 ELSIF clk'EVENT AND clk = '1' THEN
647 ELSIF clk'EVENT AND clk = '1' THEN
635 CASE state_fsm_load_MS_memory IS
648 CASE state_fsm_load_MS_memory IS
636 WHEN IDLE =>
649 WHEN IDLE =>
637 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
650 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
638 state_fsm_load_MS_memory <= LOAD_FIFO;
651 state_fsm_load_MS_memory <= LOAD_FIFO;
639 END IF;
652 END IF;
640 WHEN LOAD_FIFO =>
653 WHEN LOAD_FIFO =>
641 IF current_fifo_full = '1' THEN
654 IF current_fifo_full = '1' THEN
642 state_fsm_load_MS_memory <= TRASH_FFT;
655 state_fsm_load_MS_memory <= TRASH_FFT;
643 END IF;
656 END IF;
644 WHEN TRASH_FFT =>
657 WHEN TRASH_FFT =>
645 IF fft_ready = '0' THEN
658 IF fft_ready = '0' THEN
646 state_fsm_load_MS_memory <= IDLE;
659 state_fsm_load_MS_memory <= IDLE;
647 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
660 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
648 END IF;
661 END IF;
649 WHEN OTHERS => NULL;
662 WHEN OTHERS => NULL;
650 END CASE;
663 END CASE;
651
664
652 END IF;
665 END IF;
653 END PROCESS;
666 END PROCESS;
654
667
655 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
668 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
656 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
669 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
657 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
670 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
658 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
671 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
659 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
672 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
660
673
661 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
674 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
662 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
675 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
663 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
676 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
664 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
677 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
665 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
678 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
666
679
667 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
680 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
668 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
681 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
669 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
682 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
670 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
683 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
671 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
684 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
672
685
673 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
686 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
674
687
675 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
688 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
676 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
689 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
677 AND state_fsm_load_MS_memory = LOAD_FIFO
690 AND state_fsm_load_MS_memory = LOAD_FIFO
678 AND current_fifo_load(I) = '1'
691 AND current_fifo_load(I) = '1'
679 ELSE '1';
692 ELSE '1';
680 END GENERATE all_fifo;
693 END GENERATE all_fifo;
681
694
682 PROCESS (clk, rstn)
695 PROCESS (clk, rstn)
683 BEGIN
696 BEGIN
684 IF rstn = '0' THEN
697 IF rstn = '0' THEN
685 MEM_IN_SM_wen <= (OTHERS => '1');
698 MEM_IN_SM_wen <= (OTHERS => '1');
686 ELSIF clk'EVENT AND clk = '1' THEN
699 ELSIF clk'EVENT AND clk = '1' THEN
687 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
700 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
688 END IF;
701 END IF;
689 END PROCESS;
702 END PROCESS;
690
703
691 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
704 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
692 (fft_data_im & fft_data_re) &
705 (fft_data_im & fft_data_re) &
693 (fft_data_im & fft_data_re) &
706 (fft_data_im & fft_data_re) &
694 (fft_data_im & fft_data_re) &
707 (fft_data_im & fft_data_re) &
695 (fft_data_im & fft_data_re);
708 (fft_data_im & fft_data_re);
696 -----------------------------------------------------------------------------
709 -----------------------------------------------------------------------------
697
710
698
711
699 -----------------------------------------------------------------------------
712 -----------------------------------------------------------------------------
700 Mem_In_SpectralMatrix : lppFIFOxN
713 Mem_In_SpectralMatrix : lppFIFOxN
701 GENERIC MAP (
714 GENERIC MAP (
702 tech => 0,
715 tech => 0,
703 Mem_use => Mem_use,
716 Mem_use => Mem_use,
704 Data_sz => 32, --16,
717 Data_sz => 32, --16,
705 Addr_sz => 7, --8
718 Addr_sz => 7, --8
706 FifoCnt => 5)
719 FifoCnt => 5)
707 PORT MAP (
720 PORT MAP (
708 clk => clk,
721 clk => clk,
709 rstn => rstn,
722 rstn => rstn,
710
723
711 ReUse => MEM_IN_SM_ReUse,
724 ReUse => MEM_IN_SM_ReUse,
712
725
713 wen => MEM_IN_SM_wen,
726 wen => MEM_IN_SM_wen,
714 wdata => MEM_IN_SM_wData,
727 wdata => MEM_IN_SM_wData,
715
728
716 ren => MEM_IN_SM_ren,
729 ren => MEM_IN_SM_ren,
717 rdata => MEM_IN_SM_rData,
730 rdata => MEM_IN_SM_rData,
718 full => MEM_IN_SM_Full,
731 full => MEM_IN_SM_Full,
719 empty => MEM_IN_SM_Empty,
732 empty => MEM_IN_SM_Empty,
720 almost_full => OPEN);
733 almost_full => OPEN);
721
734
722 -----------------------------------------------------------------------------
735 -----------------------------------------------------------------------------
723
736
724 observation_vector_1(11 DOWNTO 0) <= '0' &
737 observation_vector_1(11 DOWNTO 0) <= '0' &
725 SM_correlation_done & --4
738 SM_correlation_done & --4
726 SM_correlation_auto & --3
739 SM_correlation_auto & --3
727 SM_correlation_start &
740 SM_correlation_start &
728 SM_correlation_start & --7
741 SM_correlation_start & --7
729 status_MS_input(1 DOWNTO 0)& --6..5
742 status_MS_input(1 DOWNTO 0)& --6..5
730 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
743 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
731
744
732 -----------------------------------------------------------------------------
745 -----------------------------------------------------------------------------
733 MS_control_1 : MS_control
746 MS_control_1 : MS_control
734 PORT MAP (
747 PORT MAP (
735 clk => clk,
748 clk => clk,
736 rstn => rstn,
749 rstn => rstn,
737
750
738 current_status_ms => status_MS_input,
751 current_status_ms => status_MS_input,
739
752
740 fifo_in_lock => MEM_IN_SM_locked,
753 fifo_in_lock => MEM_IN_SM_locked,
741 fifo_in_data => MEM_IN_SM_rdata,
754 fifo_in_data => MEM_IN_SM_rdata,
742 fifo_in_full => MEM_IN_SM_Full,
755 fifo_in_full => MEM_IN_SM_Full,
743 fifo_in_empty => MEM_IN_SM_Empty,
756 fifo_in_empty => MEM_IN_SM_Empty,
744 fifo_in_ren => MEM_IN_SM_ren,
757 fifo_in_ren => MEM_IN_SM_ren,
745 fifo_in_reuse => MEM_IN_SM_ReUse,
758 fifo_in_reuse => MEM_IN_SM_ReUse,
746
759
747 fifo_out_data => SM_in_data,
760 fifo_out_data => SM_in_data,
748 fifo_out_ren => SM_in_ren,
761 fifo_out_ren => SM_in_ren,
749 fifo_out_empty => SM_in_empty,
762 fifo_out_empty => SM_in_empty,
750
763
751 current_status_component => status_component,
764 current_status_component => status_component,
752
765
753 correlation_start => SM_correlation_start,
766 correlation_start => SM_correlation_start,
754 correlation_auto => SM_correlation_auto,
767 correlation_auto => SM_correlation_auto,
755 correlation_done => SM_correlation_done);
768 correlation_done => SM_correlation_done);
756
769
757
770
758 MS_calculation_1 : MS_calculation
771 MS_calculation_1 : MS_calculation
759 PORT MAP (
772 PORT MAP (
760 clk => clk,
773 clk => clk,
761 rstn => rstn,
774 rstn => rstn,
762
775
763 fifo_in_data => SM_in_data,
776 fifo_in_data => SM_in_data,
764 fifo_in_ren => SM_in_ren,
777 fifo_in_ren => SM_in_ren,
765 fifo_in_empty => SM_in_empty,
778 fifo_in_empty => SM_in_empty,
766
779
767 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
780 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
768 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
781 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
769 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
782 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
770
783
771 correlation_start => SM_correlation_start,
784 correlation_start => SM_correlation_start,
772 correlation_auto => SM_correlation_auto,
785 correlation_auto => SM_correlation_auto,
773 correlation_begin => SM_correlation_begin,
786 correlation_begin => SM_correlation_begin,
774 correlation_done => SM_correlation_done);
787 correlation_done => SM_correlation_done);
775
788
776 -----------------------------------------------------------------------------
789 -----------------------------------------------------------------------------
777 PROCESS (clk, rstn)
790 PROCESS (clk, rstn)
778 BEGIN -- PROCESS
791 BEGIN -- PROCESS
779 IF rstn = '0' THEN -- asynchronous reset (active low)
792 IF rstn = '0' THEN -- asynchronous reset (active low)
780 current_matrix_write <= '0';
793 current_matrix_write <= '0';
781 current_matrix_wait_empty <= '1';
794 current_matrix_wait_empty <= '1';
782 status_component_fifo_0 <= (OTHERS => '0');
795 status_component_fifo_0 <= (OTHERS => '0');
783 status_component_fifo_1 <= (OTHERS => '0');
796 status_component_fifo_1 <= (OTHERS => '0');
784 status_component_fifo_0_end <= '0';
797 status_component_fifo_0_end <= '0';
785 status_component_fifo_1_end <= '0';
798 status_component_fifo_1_end <= '0';
786 SM_correlation_done_reg1 <= '0';
799 SM_correlation_done_reg1 <= '0';
787 SM_correlation_done_reg2 <= '0';
800 SM_correlation_done_reg2 <= '0';
788 SM_correlation_done_reg3 <= '0';
801 SM_correlation_done_reg3 <= '0';
789
802
790 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
803 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
791 SM_correlation_done_reg1 <= SM_correlation_done;
804 SM_correlation_done_reg1 <= SM_correlation_done;
792 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
805 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
793 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
806 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
794 status_component_fifo_0_end <= '0';
807 status_component_fifo_0_end <= '0';
795 status_component_fifo_1_end <= '0';
808 status_component_fifo_1_end <= '0';
796 IF SM_correlation_begin = '1' THEN
809 IF SM_correlation_begin = '1' THEN
797 IF current_matrix_write = '0' THEN
810 IF current_matrix_write = '0' THEN
798 status_component_fifo_0 <= status_component;
811 status_component_fifo_0 <= status_component;
799 ELSE
812 ELSE
800 status_component_fifo_1 <= status_component;
813 status_component_fifo_1 <= status_component;
801 END IF;
814 END IF;
802 END IF;
815 END IF;
803
816
804 IF SM_correlation_done_reg3 = '1' THEN
817 IF SM_correlation_done_reg3 = '1' THEN
805 IF current_matrix_write = '0' THEN
818 IF current_matrix_write = '0' THEN
806 status_component_fifo_0_end <= '1';
819 status_component_fifo_0_end <= '1';
807 ELSE
820 ELSE
808 status_component_fifo_1_end <= '1';
821 status_component_fifo_1_end <= '1';
809 END IF;
822 END IF;
810 current_matrix_wait_empty <= '1';
823 current_matrix_wait_empty <= '1';
811 current_matrix_write <= NOT current_matrix_write;
824 current_matrix_write <= NOT current_matrix_write;
812 END IF;
825 END IF;
813
826
814 IF current_matrix_wait_empty <= '1' THEN
827 IF current_matrix_wait_empty <= '1' THEN
815 IF current_matrix_write = '0' THEN
828 IF current_matrix_write = '0' THEN
816 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
829 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
817 ELSE
830 ELSE
818 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
831 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
819 END IF;
832 END IF;
820 END IF;
833 END IF;
821
834
822 END IF;
835 END IF;
823 END PROCESS;
836 END PROCESS;
824
837
825 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
838 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
826 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
839 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
827 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
840 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
828 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
841 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
829 '1' WHEN current_matrix_wait_empty = '1' ELSE
842 '1' WHEN current_matrix_wait_empty = '1' ELSE
830 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
843 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
831 MEM_OUT_SM_Full(1);
844 MEM_OUT_SM_Full(1);
832
845
833 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
846 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
834 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
847 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
835
848
836 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
849 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
837 -----------------------------------------------------------------------------
850 -----------------------------------------------------------------------------
838
851
839 Mem_Out_SpectralMatrix : lppFIFOxN
852 Mem_Out_SpectralMatrix : lppFIFOxN
840 GENERIC MAP (
853 GENERIC MAP (
841 tech => 0,
854 tech => 0,
842 Mem_use => Mem_use,
855 Mem_use => Mem_use,
843 Data_sz => 32,
856 Data_sz => 32,
844 Addr_sz => 8,
857 Addr_sz => 8,
845 FifoCnt => 2)
858 FifoCnt => 2)
846 PORT MAP (
859 PORT MAP (
847 clk => clk,
860 clk => clk,
848 rstn => rstn,
861 rstn => rstn,
849
862
850 ReUse => (OTHERS => '0'),
863 ReUse => (OTHERS => '0'),
851
864
852 wen => MEM_OUT_SM_Write,
865 wen => MEM_OUT_SM_Write,
853 wdata => MEM_OUT_SM_Data_in,
866 wdata => MEM_OUT_SM_Data_in,
854
867
855 ren => MEM_OUT_SM_Read,
868 ren => MEM_OUT_SM_Read,
856 rdata => MEM_OUT_SM_Data_out,
869 rdata => MEM_OUT_SM_Data_out,
857
870
858 full => MEM_OUT_SM_Full,
871 full => MEM_OUT_SM_Full,
859 empty => MEM_OUT_SM_Empty,
872 empty => MEM_OUT_SM_Empty,
860 almost_full => OPEN);
873 almost_full => OPEN);
861
874
862 -----------------------------------------------------------------------------
875 -----------------------------------------------------------------------------
863 -- MEM_OUT_SM_Read <= "00";
876 -- MEM_OUT_SM_Read <= "00";
864 PROCESS (clk, rstn)
877 PROCESS (clk, rstn)
865 BEGIN
878 BEGIN
866 IF rstn = '0' THEN
879 IF rstn = '0' THEN
867 fifo_0_ready <= '0';
880 fifo_0_ready <= '0';
868 fifo_1_ready <= '0';
881 fifo_1_ready <= '0';
869 fifo_ongoing <= '0';
882 fifo_ongoing <= '0';
870 ELSIF clk'EVENT AND clk = '1' THEN
883 ELSIF clk'EVENT AND clk = '1' THEN
871 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
884 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
872 fifo_ongoing <= '1';
885 fifo_ongoing <= '1';
873 fifo_0_ready <= '0';
886 fifo_0_ready <= '0';
874 ELSIF status_component_fifo_0_end = '1' THEN
887 ELSIF status_component_fifo_0_end = '1' THEN
875 fifo_0_ready <= '1';
888 fifo_0_ready <= '1';
876 END IF;
889 END IF;
877
890
878 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
891 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
879 fifo_ongoing <= '0';
892 fifo_ongoing <= '0';
880 fifo_1_ready <= '0';
893 fifo_1_ready <= '0';
881 ELSIF status_component_fifo_1_end = '1' THEN
894 ELSIF status_component_fifo_1_end = '1' THEN
882 fifo_1_ready <= '1';
895 fifo_1_ready <= '1';
883 END IF;
896 END IF;
884
897
885 END IF;
898 END IF;
886 END PROCESS;
899 END PROCESS;
887
900
888 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
901 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
889 '1' WHEN fifo_0_ready = '0' ELSE
902 '1' WHEN fifo_0_ready = '0' ELSE
890 FSM_DMA_fifo_ren;
903 FSM_DMA_fifo_ren;
891
904
892 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
905 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
893 '1' WHEN fifo_1_ready = '0' ELSE
906 '1' WHEN fifo_1_ready = '0' ELSE
894 FSM_DMA_fifo_ren;
907 FSM_DMA_fifo_ren;
895
908
896 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
909 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
897 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
910 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
898 '1';
911 '1';
899
912
900 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
913 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
901 status_component_fifo_1;
914 status_component_fifo_1;
902
915
903 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
916 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
904 MEM_OUT_SM_Data_out(63 DOWNTO 32);
917 MEM_OUT_SM_Data_out(63 DOWNTO 32);
905
918
906 -----------------------------------------------------------------------------
919 -----------------------------------------------------------------------------
907 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
920 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
908 PORT MAP (
921 PORT MAP (
909 HCLK => clk,
922 HCLK => clk,
910 HRESETn => rstn,
923 HRESETn => rstn,
911
924
912 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
925 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
913 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
926 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
914 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
927 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
915 fifo_data => FSM_DMA_fifo_data,
928 fifo_data => FSM_DMA_fifo_data,
916 fifo_empty => FSM_DMA_fifo_empty,
929 fifo_empty => FSM_DMA_fifo_empty,
917 fifo_ren => FSM_DMA_fifo_ren,
930 fifo_ren => FSM_DMA_fifo_ren,
918
931
919 dma_addr => dma_addr,
932 dma_addr => dma_addr,
920 dma_data => dma_data,
933 dma_data => dma_data,
921 dma_valid => dma_valid,
934 dma_valid => dma_valid,
922 dma_valid_burst => dma_valid_burst,
935 dma_valid_burst => dma_valid_burst,
923 dma_ren => dma_ren,
936 dma_ren => dma_ren,
924 dma_done => dma_done,
937 dma_done => dma_done,
925
938
926 ready_matrix_f0 => ready_matrix_f0,
939 ready_matrix_f0 => ready_matrix_f0,
927 ready_matrix_f1 => ready_matrix_f1,
940 ready_matrix_f1 => ready_matrix_f1,
928 ready_matrix_f2 => ready_matrix_f2,
941 ready_matrix_f2 => ready_matrix_f2,
929
942
930 error_bad_component_error => error_bad_component_error,
943 error_bad_component_error => error_bad_component_error,
931 error_buffer_full => error_buffer_full,
944 error_buffer_full => error_buffer_full,
932
945
933 debug_reg => debug_reg,
946 debug_reg => debug_reg,
934 status_ready_matrix_f0 => status_ready_matrix_f0,
947 status_ready_matrix_f0 => status_ready_matrix_f0,
935 status_ready_matrix_f1 => status_ready_matrix_f1,
948 status_ready_matrix_f1 => status_ready_matrix_f1,
936 status_ready_matrix_f2 => status_ready_matrix_f2,
949 status_ready_matrix_f2 => status_ready_matrix_f2,
937
950
938 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
951 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
939 config_active_interruption_onError => config_active_interruption_onError,
952 config_active_interruption_onError => config_active_interruption_onError,
940
953
941 addr_matrix_f0 => addr_matrix_f0,
954 addr_matrix_f0 => addr_matrix_f0,
942 addr_matrix_f1 => addr_matrix_f1,
955 addr_matrix_f1 => addr_matrix_f1,
943 addr_matrix_f2 => addr_matrix_f2,
956 addr_matrix_f2 => addr_matrix_f2,
944
957
945 matrix_time_f0 => matrix_time_f0,
958 matrix_time_f0 => matrix_time_f0,
946 matrix_time_f1 => matrix_time_f1,
959 matrix_time_f1 => matrix_time_f1,
947 matrix_time_f2 => matrix_time_f2
960 matrix_time_f2 => matrix_time_f2
948 );
961 );
949 -----------------------------------------------------------------------------
962 -----------------------------------------------------------------------------
950
963
951
964
952
965
953
966
954
967
955 -----------------------------------------------------------------------------
968 -----------------------------------------------------------------------------
956 -- TIME MANAGMENT
969 -- TIME MANAGMENT
957 -----------------------------------------------------------------------------
970 -----------------------------------------------------------------------------
958 all_time <= coarse_time & fine_time;
971 all_time <= coarse_time & fine_time;
959 --
972 --
960 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
973 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
961 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
974 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
962 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
975 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
963 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
976 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
964
977
965 all_time_reg: FOR I IN 0 TO 3 GENERATE
978 all_time_reg: FOR I IN 0 TO 3 GENERATE
966
979
967 PROCESS (clk, rstn)
980 PROCESS (clk, rstn)
968 BEGIN
981 BEGIN
969 IF rstn = '0' THEN
982 IF rstn = '0' THEN
970 f_empty_reg(I) <= '1';
983 f_empty_reg(I) <= '1';
971 ELSIF clk'event AND clk = '1' THEN
984 ELSIF clk'event AND clk = '1' THEN
972 f_empty_reg(I) <= f_empty(I);
985 f_empty_reg(I) <= f_empty(I);
973 END IF;
986 END IF;
974 END PROCESS;
987 END PROCESS;
975
988
976 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
989 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
977
990
978 s_m_t_m_f0_A : spectral_matrix_time_managment
991 s_m_t_m_f0_A : spectral_matrix_time_managment
979 PORT MAP (
992 PORT MAP (
980 clk => clk,
993 clk => clk,
981 rstn => rstn,
994 rstn => rstn,
982 time_in => all_time,
995 time_in => all_time,
983 update_1 => time_update_f(I),
996 update_1 => time_update_f(I),
984 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
997 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
985 );
998 );
986
999
987 END GENERATE all_time_reg;
1000 END GENERATE all_time_reg;
988
1001
989 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1002 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
990 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1003 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
991 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1004 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
992 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1005 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
993
1006
994 -----------------------------------------------------------------------------
1007 -----------------------------------------------------------------------------
995
1008
996 END Behavioral;
1009 END Behavioral;
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