@@ -511,7 +511,7 BEGIN -- beh | |||||
511 | pirq_ms => 6, |
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511 | pirq_ms => 6, | |
512 | pirq_wfp => 14, |
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512 | pirq_wfp => 14, | |
513 | hindex => 2, |
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513 | hindex => 2, | |
514 |
top_lfr_version => X"00012 |
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514 | top_lfr_version => X"000129") -- aa.bb.cc version | |
515 | PORT MAP ( |
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515 | PORT MAP ( | |
516 | clk => clk_25, |
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516 | clk => clk_25, | |
517 | rstn => LFR_rstn, |
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517 | rstn => LFR_rstn, |
@@ -234,6 +234,7 ARCHITECTURE Behavioral OF leon3_soc IS | |||||
234 | SIGNAl mbe : std_logic; -- enable memory programming |
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234 | SIGNAl mbe : std_logic; -- enable memory programming | |
235 | SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal |
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235 | SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal | |
236 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0); |
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236 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0); | |
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237 | SIGNAL nSRAM_OE_s : STD_LOGIC; | |||
237 | --IRQ |
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238 | --IRQ | |
238 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); |
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239 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); | |
239 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); |
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240 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); | |
@@ -324,6 +325,9 ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERA | |||||
324 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
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325 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
325 | memi.bexcn <= '1'; |
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326 | memi.bexcn <= '1'; | |
326 | memi.brdyn <= '1'; |
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327 | memi.brdyn <= '1'; | |
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328 | ||||
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329 | nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0)); | |||
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330 | nSRAM_OE_s <= memo.ramoen(0); | |||
327 | END GENERATE; |
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331 | END GENERATE; | |
328 |
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332 | |||
329 | IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE |
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333 | IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE | |
@@ -366,6 +370,10 IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERA | |||||
366 | i => mbe, |
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370 | i => mbe, | |
367 | en => mbe_drive, |
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371 | en => mbe_drive, | |
368 | o => memi.bexcn ); |
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372 | o => memi.bexcn ); | |
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373 | ||||
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374 | nSRAM_CE_s <= (memo.ramsn(1 downto 0)); | |||
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375 | nSRAM_OE_s <= memo.oen; | |||
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376 | ||||
369 | END GENERATE; |
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377 | END GENERATE; | |
370 |
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378 | |||
371 |
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379 | |||
@@ -384,9 +392,8 END GENERATE; | |||||
384 |
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392 | |||
385 | addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech) |
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393 | addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech) | |
386 | PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2)); |
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394 | PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2)); | |
387 | nSRAM_CE_s <= (memo.ramsn(1 downto 0)); |
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388 | rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s); |
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395 | rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s); | |
389 |
oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, |
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396 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s); | |
390 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
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397 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
391 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
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398 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
392 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
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399 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
@@ -481,4 +488,4 END GENERATE; | |||||
481 |
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488 | |||
482 |
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489 | |||
483 |
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490 | |||
484 | END Behavioral; No newline at end of file |
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491 | END Behavioral; |
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