@@ -1,720 +1,720 | |||||
1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
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19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
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21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
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22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
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23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
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24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
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25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
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26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
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27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
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28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
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29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
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30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
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31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
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32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
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33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
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34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; |
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35 | USE gaisler.spacewire.ALL; | |
36 | LIBRARY esa; |
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36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
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37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
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38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
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39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
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40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
43 | USE lpp.iir_filter.ALL; |
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43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
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44 | USE lpp.general_purpose.ALL; | |
45 | USE lpp.lpp_lfr_time_management.ALL; |
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45 | USE lpp.lpp_lfr_time_management.ALL; | |
46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
47 |
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47 | |||
48 | ENTITY MINI_LFR_top IS |
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48 | ENTITY MINI_LFR_top IS | |
49 |
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49 | |||
50 | PORT ( |
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50 | PORT ( | |
51 | clk_50 : IN STD_LOGIC; |
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51 | clk_50 : IN STD_LOGIC; | |
52 | clk_49 : IN STD_LOGIC; |
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52 | clk_49 : IN STD_LOGIC; | |
53 | reset : IN STD_LOGIC; |
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53 | reset : IN STD_LOGIC; | |
54 | --BPs |
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54 | --BPs | |
55 | BP0 : IN STD_LOGIC; |
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55 | BP0 : IN STD_LOGIC; | |
56 | BP1 : IN STD_LOGIC; |
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56 | BP1 : IN STD_LOGIC; | |
57 | --LEDs |
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57 | --LEDs | |
58 | LED0 : OUT STD_LOGIC; |
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58 | LED0 : OUT STD_LOGIC; | |
59 | LED1 : OUT STD_LOGIC; |
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59 | LED1 : OUT STD_LOGIC; | |
60 | LED2 : OUT STD_LOGIC; |
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60 | LED2 : OUT STD_LOGIC; | |
61 | --UARTs |
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61 | --UARTs | |
62 | TXD1 : IN STD_LOGIC; |
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62 | TXD1 : IN STD_LOGIC; | |
63 | RXD1 : OUT STD_LOGIC; |
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63 | RXD1 : OUT STD_LOGIC; | |
64 | nCTS1 : OUT STD_LOGIC; |
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64 | nCTS1 : OUT STD_LOGIC; | |
65 | nRTS1 : IN STD_LOGIC; |
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65 | nRTS1 : IN STD_LOGIC; | |
66 |
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66 | |||
67 | TXD2 : IN STD_LOGIC; |
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67 | TXD2 : IN STD_LOGIC; | |
68 | RXD2 : OUT STD_LOGIC; |
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68 | RXD2 : OUT STD_LOGIC; | |
69 | nCTS2 : OUT STD_LOGIC; |
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69 | nCTS2 : OUT STD_LOGIC; | |
70 | nDTR2 : IN STD_LOGIC; |
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70 | nDTR2 : IN STD_LOGIC; | |
71 | nRTS2 : IN STD_LOGIC; |
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71 | nRTS2 : IN STD_LOGIC; | |
72 | nDCD2 : OUT STD_LOGIC; |
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72 | nDCD2 : OUT STD_LOGIC; | |
73 |
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73 | |||
74 | --EXT CONNECTOR |
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74 | --EXT CONNECTOR | |
75 | IO0 : INOUT STD_LOGIC; |
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75 | IO0 : INOUT STD_LOGIC; | |
76 | IO1 : INOUT STD_LOGIC; |
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76 | IO1 : INOUT STD_LOGIC; | |
77 | IO2 : INOUT STD_LOGIC; |
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77 | IO2 : INOUT STD_LOGIC; | |
78 | IO3 : INOUT STD_LOGIC; |
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78 | IO3 : INOUT STD_LOGIC; | |
79 | IO4 : INOUT STD_LOGIC; |
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79 | IO4 : INOUT STD_LOGIC; | |
80 | IO5 : INOUT STD_LOGIC; |
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80 | IO5 : INOUT STD_LOGIC; | |
81 | IO6 : INOUT STD_LOGIC; |
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81 | IO6 : INOUT STD_LOGIC; | |
82 | IO7 : INOUT STD_LOGIC; |
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82 | IO7 : INOUT STD_LOGIC; | |
83 | IO8 : INOUT STD_LOGIC; |
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83 | IO8 : INOUT STD_LOGIC; | |
84 | IO9 : INOUT STD_LOGIC; |
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84 | IO9 : INOUT STD_LOGIC; | |
85 | IO10 : INOUT STD_LOGIC; |
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85 | IO10 : INOUT STD_LOGIC; | |
86 | IO11 : INOUT STD_LOGIC; |
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86 | IO11 : INOUT STD_LOGIC; | |
87 |
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87 | |||
88 | --SPACE WIRE |
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88 | --SPACE WIRE | |
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
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89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
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90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
91 | SPW_NOM_SIN : IN STD_LOGIC; |
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91 | SPW_NOM_SIN : IN STD_LOGIC; | |
92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
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94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
95 | SPW_RED_SIN : IN STD_LOGIC; |
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95 | SPW_RED_SIN : IN STD_LOGIC; | |
96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
98 | -- MINI LFR ADC INPUTS |
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98 | -- MINI LFR ADC INPUTS | |
99 | ADC_nCS : OUT STD_LOGIC; |
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99 | ADC_nCS : OUT STD_LOGIC; | |
100 | ADC_CLK : OUT STD_LOGIC; |
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100 | ADC_CLK : OUT STD_LOGIC; | |
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
102 |
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102 | |||
103 | -- SRAM |
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103 | -- SRAM | |
104 | SRAM_nWE : OUT STD_LOGIC; |
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104 | SRAM_nWE : OUT STD_LOGIC; | |
105 | SRAM_CE : OUT STD_LOGIC; |
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105 | SRAM_CE : OUT STD_LOGIC; | |
106 | SRAM_nOE : OUT STD_LOGIC; |
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106 | SRAM_nOE : OUT STD_LOGIC; | |
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
110 | ); |
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110 | ); | |
111 |
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111 | |||
112 | END MINI_LFR_top; |
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112 | END MINI_LFR_top; | |
113 |
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113 | |||
114 |
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114 | |||
115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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118 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
119 | ----------------------------------------------------------------------------- |
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119 | ----------------------------------------------------------------------------- | |
120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
122 | -- |
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122 | -- | |
123 | SIGNAL errorn : STD_LOGIC; |
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123 | SIGNAL errorn : STD_LOGIC; | |
124 | -- UART AHB --------------------------------------------------------------- |
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124 | -- UART AHB --------------------------------------------------------------- | |
125 | -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
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125 | -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
126 | -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
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126 | -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
127 |
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127 | |||
128 | -- UART APB --------------------------------------------------------------- |
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128 | -- UART APB --------------------------------------------------------------- | |
129 | -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
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129 | -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
130 | -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
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130 | -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
131 | -- |
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131 | -- | |
132 | SIGNAL I00_s : STD_LOGIC; |
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132 | SIGNAL I00_s : STD_LOGIC; | |
133 |
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133 | |||
134 | -- CONSTANTS |
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134 | -- CONSTANTS | |
135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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135 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
136 | -- |
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136 | -- | |
137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
140 |
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140 | |||
141 | SIGNAL apbi_ext : apb_slv_in_type; |
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141 | SIGNAL apbi_ext : apb_slv_in_type; | |
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); |
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142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); | |
143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); |
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144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); | |
145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); |
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146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); | |
147 |
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147 | |||
148 | -- Spacewire signals |
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148 | -- Spacewire signals | |
149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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152 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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153 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
154 | SIGNAL spw_clk : STD_LOGIC; |
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154 | SIGNAL spw_clk : STD_LOGIC; | |
155 | SIGNAL swni : grspw_in_type; |
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155 | SIGNAL swni : grspw_in_type; | |
156 | SIGNAL swno : grspw_out_type; |
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156 | SIGNAL swno : grspw_out_type; | |
157 | -- SIGNAL clkmn : STD_ULOGIC; |
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157 | -- SIGNAL clkmn : STD_ULOGIC; | |
158 | -- SIGNAL txclk : STD_ULOGIC; |
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158 | -- SIGNAL txclk : STD_ULOGIC; | |
159 |
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159 | |||
160 | --GPIO |
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160 | --GPIO | |
161 | SIGNAL gpioi : gpio_in_type; |
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161 | SIGNAL gpioi : gpio_in_type; | |
162 | SIGNAL gpioo : gpio_out_type; |
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162 | SIGNAL gpioo : gpio_out_type; | |
163 |
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163 | |||
164 | -- AD Converter ADS7886 |
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164 | -- AD Converter ADS7886 | |
165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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165 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
166 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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166 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
167 | SIGNAL sample_val : STD_LOGIC; |
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167 | SIGNAL sample_val : STD_LOGIC; | |
168 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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168 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
169 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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169 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
171 |
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171 | |||
172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
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172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
173 |
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173 | |||
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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175 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
176 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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176 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
177 | ----------------------------------------------------------------------------- |
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177 | ----------------------------------------------------------------------------- | |
178 |
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178 | |||
179 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
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179 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
180 | SIGNAL LFR_rstn : STD_LOGIC; |
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180 | SIGNAL LFR_rstn : STD_LOGIC; | |
181 |
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181 | |||
182 |
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182 | |||
183 | SIGNAL rstn_25 : STD_LOGIC; |
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183 | SIGNAL rstn_25 : STD_LOGIC; | |
184 | SIGNAL rstn_25_d1 : STD_LOGIC; |
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184 | SIGNAL rstn_25_d1 : STD_LOGIC; | |
185 | SIGNAL rstn_25_d2 : STD_LOGIC; |
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185 | SIGNAL rstn_25_d2 : STD_LOGIC; | |
186 | SIGNAL rstn_25_d3 : STD_LOGIC; |
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186 | SIGNAL rstn_25_d3 : STD_LOGIC; | |
187 |
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187 | |||
188 | SIGNAL rstn_50 : STD_LOGIC; |
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188 | SIGNAL rstn_50 : STD_LOGIC; | |
189 | SIGNAL rstn_50_d1 : STD_LOGIC; |
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189 | SIGNAL rstn_50_d1 : STD_LOGIC; | |
190 | SIGNAL rstn_50_d2 : STD_LOGIC; |
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190 | SIGNAL rstn_50_d2 : STD_LOGIC; | |
191 | SIGNAL rstn_50_d3 : STD_LOGIC; |
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191 | SIGNAL rstn_50_d3 : STD_LOGIC; | |
192 |
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192 | |||
193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
195 |
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195 | |||
196 | -- |
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196 | -- | |
197 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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197 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
198 |
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198 | |||
199 | BEGIN -- beh |
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199 | BEGIN -- beh | |
200 |
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200 | |||
201 | ----------------------------------------------------------------------------- |
|
201 | ----------------------------------------------------------------------------- | |
202 | -- CLK |
|
202 | -- CLK | |
203 | ----------------------------------------------------------------------------- |
|
203 | ----------------------------------------------------------------------------- | |
204 |
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204 | |||
205 | --PROCESS(clk_50) |
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205 | --PROCESS(clk_50) | |
206 | --BEGIN |
|
206 | --BEGIN | |
207 | -- IF clk_50'EVENT AND clk_50 = '1' THEN |
|
207 | -- IF clk_50'EVENT AND clk_50 = '1' THEN | |
208 | -- clk_50_s <= NOT clk_50_s; |
|
208 | -- clk_50_s <= NOT clk_50_s; | |
209 | -- END IF; |
|
209 | -- END IF; | |
210 | --END PROCESS; |
|
210 | --END PROCESS; | |
211 |
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211 | |||
212 | --PROCESS(clk_50_s) |
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212 | --PROCESS(clk_50_s) | |
213 | --BEGIN |
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213 | --BEGIN | |
214 | -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
214 | -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
215 | -- clk_25 <= NOT clk_25; |
|
215 | -- clk_25 <= NOT clk_25; | |
216 | -- END IF; |
|
216 | -- END IF; | |
217 | --END PROCESS; |
|
217 | --END PROCESS; | |
218 |
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218 | |||
219 | --PROCESS(clk_49) |
|
219 | --PROCESS(clk_49) | |
220 | --BEGIN |
|
220 | --BEGIN | |
221 | -- IF clk_49'EVENT AND clk_49 = '1' THEN |
|
221 | -- IF clk_49'EVENT AND clk_49 = '1' THEN | |
222 | -- clk_24 <= NOT clk_24; |
|
222 | -- clk_24 <= NOT clk_24; | |
223 | -- END IF; |
|
223 | -- END IF; | |
224 | --END PROCESS; |
|
224 | --END PROCESS; | |
225 |
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225 | |||
226 | --PROCESS(clk_25) |
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226 | --PROCESS(clk_25) | |
227 | --BEGIN |
|
227 | --BEGIN | |
228 | -- IF clk_25'EVENT AND clk_25 = '1' THEN |
|
228 | -- IF clk_25'EVENT AND clk_25 = '1' THEN | |
229 | -- rstn_25 <= reset; |
|
229 | -- rstn_25 <= reset; | |
230 | -- END IF; |
|
230 | -- END IF; | |
231 | --END PROCESS; |
|
231 | --END PROCESS; | |
232 |
|
232 | |||
233 | PROCESS (clk_50, reset) |
|
233 | PROCESS (clk_50, reset) | |
234 | BEGIN -- PROCESS |
|
234 | BEGIN -- PROCESS | |
235 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
235 | IF reset = '0' THEN -- asynchronous reset (active low) | |
236 | clk_50_s <= '0'; |
|
236 | clk_50_s <= '0'; | |
237 | rstn_50 <= '0'; |
|
237 | rstn_50 <= '0'; | |
238 | rstn_50_d1 <= '0'; |
|
238 | rstn_50_d1 <= '0'; | |
239 | rstn_50_d2 <= '0'; |
|
239 | rstn_50_d2 <= '0'; | |
240 | rstn_50_d3 <= '0'; |
|
240 | rstn_50_d3 <= '0'; | |
241 |
|
241 | |||
242 | ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge |
|
242 | ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge | |
243 | clk_50_s <= NOT clk_50_s; |
|
243 | clk_50_s <= NOT clk_50_s; | |
244 | rstn_50_d1 <= '1'; |
|
244 | rstn_50_d1 <= '1'; | |
245 | rstn_50_d2 <= rstn_50_d1; |
|
245 | rstn_50_d2 <= rstn_50_d1; | |
246 | rstn_50_d3 <= rstn_50_d2; |
|
246 | rstn_50_d3 <= rstn_50_d2; | |
247 | rstn_50 <= rstn_50_d3; |
|
247 | rstn_50 <= rstn_50_d3; | |
248 | END IF; |
|
248 | END IF; | |
249 | END PROCESS; |
|
249 | END PROCESS; | |
250 |
|
250 | |||
251 | PROCESS (clk_50_s, rstn_50) |
|
251 | PROCESS (clk_50_s, rstn_50) | |
252 | BEGIN -- PROCESS |
|
252 | BEGIN -- PROCESS | |
253 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) |
|
253 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) | |
254 | clk_25 <= '0'; |
|
254 | clk_25 <= '0'; | |
255 | rstn_25 <= '0'; |
|
255 | rstn_25 <= '0'; | |
256 | rstn_25_d1 <= '0'; |
|
256 | rstn_25_d1 <= '0'; | |
257 | rstn_25_d2 <= '0'; |
|
257 | rstn_25_d2 <= '0'; | |
258 | rstn_25_d3 <= '0'; |
|
258 | rstn_25_d3 <= '0'; | |
259 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge |
|
259 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge | |
260 | clk_25 <= NOT clk_25; |
|
260 | clk_25 <= NOT clk_25; | |
261 | rstn_25_d1 <= '1'; |
|
261 | rstn_25_d1 <= '1'; | |
262 | rstn_25_d2 <= rstn_25_d1; |
|
262 | rstn_25_d2 <= rstn_25_d1; | |
263 | rstn_25_d3 <= rstn_25_d2; |
|
263 | rstn_25_d3 <= rstn_25_d2; | |
264 | rstn_25 <= rstn_25_d3; |
|
264 | rstn_25 <= rstn_25_d3; | |
265 | END IF; |
|
265 | END IF; | |
266 | END PROCESS; |
|
266 | END PROCESS; | |
267 |
|
267 | |||
268 | PROCESS (clk_49, reset) |
|
268 | PROCESS (clk_49, reset) | |
269 | BEGIN -- PROCESS |
|
269 | BEGIN -- PROCESS | |
270 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
270 | IF reset = '0' THEN -- asynchronous reset (active low) | |
271 | clk_24 <= '0'; |
|
271 | clk_24 <= '0'; | |
272 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge |
|
272 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
273 | clk_24 <= NOT clk_24; |
|
273 | clk_24 <= NOT clk_24; | |
274 | END IF; |
|
274 | END IF; | |
275 | END PROCESS; |
|
275 | END PROCESS; | |
276 |
|
276 | |||
277 | ----------------------------------------------------------------------------- |
|
277 | ----------------------------------------------------------------------------- | |
278 |
|
278 | |||
279 | PROCESS (clk_25, rstn_25) |
|
279 | PROCESS (clk_25, rstn_25) | |
280 | BEGIN -- PROCESS |
|
280 | BEGIN -- PROCESS | |
281 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
281 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
282 | LED0 <= '0'; |
|
282 | LED0 <= '0'; | |
283 | LED1 <= '0'; |
|
283 | LED1 <= '0'; | |
284 | LED2 <= '0'; |
|
284 | LED2 <= '0'; | |
285 | --IO1 <= '0'; |
|
285 | --IO1 <= '0'; | |
286 | --IO2 <= '1'; |
|
286 | --IO2 <= '1'; | |
287 | --IO3 <= '0'; |
|
287 | --IO3 <= '0'; | |
288 | --IO4 <= '0'; |
|
288 | --IO4 <= '0'; | |
289 | --IO5 <= '0'; |
|
289 | --IO5 <= '0'; | |
290 | --IO6 <= '0'; |
|
290 | --IO6 <= '0'; | |
291 | --IO7 <= '0'; |
|
291 | --IO7 <= '0'; | |
292 | --IO8 <= '0'; |
|
292 | --IO8 <= '0'; | |
293 | --IO9 <= '0'; |
|
293 | --IO9 <= '0'; | |
294 | --IO10 <= '0'; |
|
294 | --IO10 <= '0'; | |
295 | --IO11 <= '0'; |
|
295 | --IO11 <= '0'; | |
296 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
296 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
297 | LED0 <= '0'; |
|
297 | LED0 <= '0'; | |
298 | LED1 <= '1'; |
|
298 | LED1 <= '1'; | |
299 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
299 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
300 | --IO1 <= '1'; |
|
300 | --IO1 <= '1'; | |
301 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
301 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
302 | --IO3 <= ADC_SDO(0); |
|
302 | --IO3 <= ADC_SDO(0); | |
303 | --IO4 <= ADC_SDO(1); |
|
303 | --IO4 <= ADC_SDO(1); | |
304 | --IO5 <= ADC_SDO(2); |
|
304 | --IO5 <= ADC_SDO(2); | |
305 | --IO6 <= ADC_SDO(3); |
|
305 | --IO6 <= ADC_SDO(3); | |
306 | --IO7 <= ADC_SDO(4); |
|
306 | --IO7 <= ADC_SDO(4); | |
307 | --IO8 <= ADC_SDO(5); |
|
307 | --IO8 <= ADC_SDO(5); | |
308 | --IO9 <= ADC_SDO(6); |
|
308 | --IO9 <= ADC_SDO(6); | |
309 | --IO10 <= ADC_SDO(7); |
|
309 | --IO10 <= ADC_SDO(7); | |
310 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
310 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
311 | END IF; |
|
311 | END IF; | |
312 | END PROCESS; |
|
312 | END PROCESS; | |
313 |
|
313 | |||
314 | PROCESS (clk_24, rstn_25) |
|
314 | PROCESS (clk_24, rstn_25) | |
315 | BEGIN -- PROCESS |
|
315 | BEGIN -- PROCESS | |
316 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
316 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
317 | I00_s <= '0'; |
|
317 | I00_s <= '0'; | |
318 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
318 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge | |
319 | I00_s <= NOT I00_s; |
|
319 | I00_s <= NOT I00_s; | |
320 | END IF; |
|
320 | END IF; | |
321 | END PROCESS; |
|
321 | END PROCESS; | |
322 | -- IO0 <= I00_s; |
|
322 | -- IO0 <= I00_s; | |
323 |
|
323 | |||
324 | --UARTs |
|
324 | --UARTs | |
325 | nCTS1 <= '1'; |
|
325 | nCTS1 <= '1'; | |
326 | nCTS2 <= '1'; |
|
326 | nCTS2 <= '1'; | |
327 | nDCD2 <= '1'; |
|
327 | nDCD2 <= '1'; | |
328 |
|
328 | |||
329 | --EXT CONNECTOR |
|
329 | --EXT CONNECTOR | |
330 |
|
330 | |||
331 | --SPACE WIRE |
|
331 | --SPACE WIRE | |
332 |
|
332 | |||
333 | leon3_soc_1 : leon3_soc |
|
333 | leon3_soc_1 : leon3_soc | |
334 | GENERIC MAP ( |
|
334 | GENERIC MAP ( | |
335 | fabtech => apa3e, |
|
335 | fabtech => apa3e, | |
336 | memtech => apa3e, |
|
336 | memtech => apa3e, | |
337 | padtech => inferred, |
|
337 | padtech => inferred, | |
338 | clktech => inferred, |
|
338 | clktech => inferred, | |
339 | disas => 0, |
|
339 | disas => 0, | |
340 | dbguart => 0, |
|
340 | dbguart => 0, | |
341 | pclow => 2, |
|
341 | pclow => 2, | |
342 | clk_freq => 25000, |
|
342 | clk_freq => 25000, | |
343 | NB_CPU => 1, |
|
343 | NB_CPU => 1, | |
344 | ENABLE_FPU => 1, |
|
344 | ENABLE_FPU => 1, | |
345 | FPU_NETLIST => 0, |
|
345 | FPU_NETLIST => 0, | |
346 | ENABLE_DSU => 1, |
|
346 | ENABLE_DSU => 1, | |
347 | ENABLE_AHB_UART => 1, |
|
347 | ENABLE_AHB_UART => 1, | |
348 | ENABLE_APB_UART => 1, |
|
348 | ENABLE_APB_UART => 1, | |
349 | ENABLE_IRQMP => 1, |
|
349 | ENABLE_IRQMP => 1, | |
350 | ENABLE_GPT => 1, |
|
350 | ENABLE_GPT => 1, | |
351 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
351 | NB_AHB_MASTER => NB_AHB_MASTER, | |
352 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
352 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
353 | NB_APB_SLAVE => NB_APB_SLAVE, |
|
353 | NB_APB_SLAVE => NB_APB_SLAVE, | |
354 | ADDRESS_SIZE => 20, |
|
354 | ADDRESS_SIZE => 20, | |
355 | USES_IAP_MEMCTRLR => 0) |
|
355 | USES_IAP_MEMCTRLR => 0) | |
356 | PORT MAP ( |
|
356 | PORT MAP ( | |
357 | clk => clk_25, |
|
357 | clk => clk_25, | |
358 | reset => rstn_25, |
|
358 | reset => rstn_25, | |
359 | errorn => errorn, |
|
359 | errorn => errorn, | |
360 | ahbrxd => TXD1, |
|
360 | ahbrxd => TXD1, | |
361 | ahbtxd => RXD1, |
|
361 | ahbtxd => RXD1, | |
362 | urxd1 => TXD2, |
|
362 | urxd1 => TXD2, | |
363 | utxd1 => RXD2, |
|
363 | utxd1 => RXD2, | |
364 | address => SRAM_A, |
|
364 | address => SRAM_A, | |
365 | data => SRAM_DQ, |
|
365 | data => SRAM_DQ, | |
366 | nSRAM_BE0 => SRAM_nBE(0), |
|
366 | nSRAM_BE0 => SRAM_nBE(0), | |
367 | nSRAM_BE1 => SRAM_nBE(1), |
|
367 | nSRAM_BE1 => SRAM_nBE(1), | |
368 | nSRAM_BE2 => SRAM_nBE(2), |
|
368 | nSRAM_BE2 => SRAM_nBE(2), | |
369 | nSRAM_BE3 => SRAM_nBE(3), |
|
369 | nSRAM_BE3 => SRAM_nBE(3), | |
370 | nSRAM_WE => SRAM_nWE, |
|
370 | nSRAM_WE => SRAM_nWE, | |
371 | nSRAM_CE => SRAM_CE_s, |
|
371 | nSRAM_CE => SRAM_CE_s, | |
372 | nSRAM_OE => SRAM_nOE, |
|
372 | nSRAM_OE => SRAM_nOE, | |
373 | nSRAM_READY => '0', |
|
373 | nSRAM_READY => '0', | |
374 | SRAM_MBE => OPEN, |
|
374 | SRAM_MBE => OPEN, | |
375 | apbi_ext => apbi_ext, |
|
375 | apbi_ext => apbi_ext, | |
376 | apbo_ext => apbo_ext, |
|
376 | apbo_ext => apbo_ext, | |
377 | ahbi_s_ext => ahbi_s_ext, |
|
377 | ahbi_s_ext => ahbi_s_ext, | |
378 | ahbo_s_ext => ahbo_s_ext, |
|
378 | ahbo_s_ext => ahbo_s_ext, | |
379 | ahbi_m_ext => ahbi_m_ext, |
|
379 | ahbi_m_ext => ahbi_m_ext, | |
380 | ahbo_m_ext => ahbo_m_ext); |
|
380 | ahbo_m_ext => ahbo_m_ext); | |
381 |
|
381 | |||
382 | SRAM_CE <= SRAM_CE_s(0); |
|
382 | SRAM_CE <= SRAM_CE_s(0); | |
383 | ------------------------------------------------------------------------------- |
|
383 | ------------------------------------------------------------------------------- | |
384 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
384 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
385 | ------------------------------------------------------------------------------- |
|
385 | ------------------------------------------------------------------------------- | |
386 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
386 | apb_lfr_time_management_1 : apb_lfr_time_management | |
387 | GENERIC MAP ( |
|
387 | GENERIC MAP ( | |
388 | pindex => 6, |
|
388 | pindex => 6, | |
389 | paddr => 6, |
|
389 | paddr => 6, | |
390 | pmask => 16#fff#, |
|
390 | pmask => 16#fff#, | |
391 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
391 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
392 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
392 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
393 | PORT MAP ( |
|
393 | PORT MAP ( | |
394 | clk25MHz => clk_25, |
|
394 | clk25MHz => clk_25, | |
395 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
395 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
396 | resetn => rstn_25, |
|
396 | resetn => rstn_25, | |
397 | grspw_tick => swno.tickout, |
|
397 | grspw_tick => swno.tickout, | |
398 | apbi => apbi_ext, |
|
398 | apbi => apbi_ext, | |
399 | apbo => apbo_ext(6), |
|
399 | apbo => apbo_ext(6), | |
400 | coarse_time => coarse_time, |
|
400 | coarse_time => coarse_time, | |
401 | fine_time => fine_time, |
|
401 | fine_time => fine_time, | |
402 | LFR_soft_rstn => LFR_soft_rstn |
|
402 | LFR_soft_rstn => LFR_soft_rstn | |
403 | ); |
|
403 | ); | |
404 |
|
404 | |||
405 | ----------------------------------------------------------------------- |
|
405 | ----------------------------------------------------------------------- | |
406 | --- SpaceWire -------------------------------------------------------- |
|
406 | --- SpaceWire -------------------------------------------------------- | |
407 | ----------------------------------------------------------------------- |
|
407 | ----------------------------------------------------------------------- | |
408 |
|
408 | |||
409 | SPW_EN <= '1'; |
|
409 | SPW_EN <= '1'; | |
410 |
|
410 | |||
411 | spw_clk <= clk_50_s; |
|
411 | spw_clk <= clk_50_s; | |
412 | spw_rxtxclk <= spw_clk; |
|
412 | spw_rxtxclk <= spw_clk; | |
413 | spw_rxclkn <= NOT spw_rxtxclk; |
|
413 | spw_rxclkn <= NOT spw_rxtxclk; | |
414 |
|
414 | |||
415 | -- PADS for SPW1 |
|
415 | -- PADS for SPW1 | |
416 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
416 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
417 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
417 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
418 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
418 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
419 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
419 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
420 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
420 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
421 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
421 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
422 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
422 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
423 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
423 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
424 | -- PADS FOR SPW2 |
|
424 | -- PADS FOR SPW2 | |
425 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
425 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
426 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
426 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
427 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
427 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
428 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
428 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
429 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
429 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
430 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
430 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
431 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
431 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
432 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
432 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
433 |
|
433 | |||
434 | -- GRSPW PHY |
|
434 | -- GRSPW PHY | |
435 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
435 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
436 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
436 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
437 | spw_phy0 : grspw_phy |
|
437 | spw_phy0 : grspw_phy | |
438 | GENERIC MAP( |
|
438 | GENERIC MAP( | |
439 | tech => apa3e, |
|
439 | tech => apa3e, | |
440 | rxclkbuftype => 1, |
|
440 | rxclkbuftype => 1, | |
441 | scantest => 0) |
|
441 | scantest => 0) | |
442 | PORT MAP( |
|
442 | PORT MAP( | |
443 | rxrst => swno.rxrst, |
|
443 | rxrst => swno.rxrst, | |
444 | di => dtmp(j), |
|
444 | di => dtmp(j), | |
445 | si => stmp(j), |
|
445 | si => stmp(j), | |
446 | rxclko => spw_rxclk(j), |
|
446 | rxclko => spw_rxclk(j), | |
447 | do => swni.d(j), |
|
447 | do => swni.d(j), | |
448 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
448 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
449 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
449 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
450 | END GENERATE spw_inputloop; |
|
450 | END GENERATE spw_inputloop; | |
451 |
|
451 | |||
452 | swni.rmapnodeaddr <= (OTHERS => '0'); |
|
452 | swni.rmapnodeaddr <= (OTHERS => '0'); | |
453 |
|
453 | |||
454 | -- SPW core |
|
454 | -- SPW core | |
455 | sw0 : grspwm GENERIC MAP( |
|
455 | sw0 : grspwm GENERIC MAP( | |
456 | tech => apa3e, |
|
456 | tech => apa3e, | |
457 | hindex => 1, |
|
457 | hindex => 1, | |
458 | pindex => 5, |
|
458 | pindex => 5, | |
459 | paddr => 5, |
|
459 | paddr => 5, | |
460 | pirq => 11, |
|
460 | pirq => 11, | |
461 | sysfreq => 25000, -- CPU_FREQ |
|
461 | sysfreq => 25000, -- CPU_FREQ | |
462 | rmap => 1, |
|
462 | rmap => 1, | |
463 | rmapcrc => 1, |
|
463 | rmapcrc => 1, | |
464 | fifosize1 => 16, |
|
464 | fifosize1 => 16, | |
465 | fifosize2 => 16, |
|
465 | fifosize2 => 16, | |
466 | rxclkbuftype => 1, |
|
466 | rxclkbuftype => 1, | |
467 | rxunaligned => 0, |
|
467 | rxunaligned => 0, | |
468 | rmapbufs => 4, |
|
468 | rmapbufs => 4, | |
469 | ft => 0, |
|
469 | ft => 0, | |
470 | netlist => 0, |
|
470 | netlist => 0, | |
471 | ports => 2, |
|
471 | ports => 2, | |
472 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
472 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
473 | memtech => apa3e, |
|
473 | memtech => apa3e, | |
474 | destkey => 2, |
|
474 | destkey => 2, | |
475 | spwcore => 1 |
|
475 | spwcore => 1 | |
476 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
476 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
477 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
477 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
478 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
478 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
479 | ) |
|
479 | ) | |
480 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
480 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), | |
481 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
481 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
482 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
482 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
483 | swni, swno); |
|
483 | swni, swno); | |
484 |
|
484 | |||
485 | swni.tickin <= '0'; |
|
485 | swni.tickin <= '0'; | |
486 | swni.rmapen <= '1'; |
|
486 | swni.rmapen <= '1'; | |
487 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
487 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
488 | swni.tickinraw <= '0'; |
|
488 | swni.tickinraw <= '0'; | |
489 | swni.timein <= (OTHERS => '0'); |
|
489 | swni.timein <= (OTHERS => '0'); | |
490 | swni.dcrstval <= (OTHERS => '0'); |
|
490 | swni.dcrstval <= (OTHERS => '0'); | |
491 | swni.timerrstval <= (OTHERS => '0'); |
|
491 | swni.timerrstval <= (OTHERS => '0'); | |
492 |
|
492 | |||
493 | ------------------------------------------------------------------------------- |
|
493 | ------------------------------------------------------------------------------- | |
494 | -- LFR ------------------------------------------------------------------------ |
|
494 | -- LFR ------------------------------------------------------------------------ | |
495 | ------------------------------------------------------------------------------- |
|
495 | ------------------------------------------------------------------------------- | |
496 |
|
496 | |||
497 |
|
497 | |||
498 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
498 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
499 | --LFR_rstn <= rstn_25; |
|
499 | --LFR_rstn <= rstn_25; | |
500 |
|
500 | |||
501 | lpp_lfr_1 : lpp_lfr |
|
501 | lpp_lfr_1 : lpp_lfr | |
502 | GENERIC MAP ( |
|
502 | GENERIC MAP ( | |
503 | Mem_use => use_RAM, |
|
503 | Mem_use => use_RAM, | |
504 | nb_data_by_buffer_size => 32, |
|
504 | nb_data_by_buffer_size => 32, | |
505 | nb_snapshot_param_size => 32, |
|
505 | nb_snapshot_param_size => 32, | |
506 | delta_vector_size => 32, |
|
506 | delta_vector_size => 32, | |
507 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
507 | delta_vector_size_f0_2 => 7, -- log2(96) | |
508 | pindex => 15, |
|
508 | pindex => 15, | |
509 | paddr => 15, |
|
509 | paddr => 15, | |
510 | pmask => 16#fff#, |
|
510 | pmask => 16#fff#, | |
511 | pirq_ms => 6, |
|
511 | pirq_ms => 6, | |
512 | pirq_wfp => 14, |
|
512 | pirq_wfp => 14, | |
513 | hindex => 2, |
|
513 | hindex => 2, | |
514 |
top_lfr_version => X"00012 |
|
514 | top_lfr_version => X"000129") -- aa.bb.cc version | |
515 | PORT MAP ( |
|
515 | PORT MAP ( | |
516 | clk => clk_25, |
|
516 | clk => clk_25, | |
517 | rstn => LFR_rstn, |
|
517 | rstn => LFR_rstn, | |
518 | sample_B => sample_s(2 DOWNTO 0), |
|
518 | sample_B => sample_s(2 DOWNTO 0), | |
519 | sample_E => sample_s(7 DOWNTO 3), |
|
519 | sample_E => sample_s(7 DOWNTO 3), | |
520 | sample_val => sample_val, |
|
520 | sample_val => sample_val, | |
521 | apbi => apbi_ext, |
|
521 | apbi => apbi_ext, | |
522 | apbo => apbo_ext(15), |
|
522 | apbo => apbo_ext(15), | |
523 | ahbi => ahbi_m_ext, |
|
523 | ahbi => ahbi_m_ext, | |
524 | ahbo => ahbo_m_ext(2), |
|
524 | ahbo => ahbo_m_ext(2), | |
525 | coarse_time => coarse_time, |
|
525 | coarse_time => coarse_time, | |
526 | fine_time => fine_time, |
|
526 | fine_time => fine_time, | |
527 | data_shaping_BW => bias_fail_sw_sig, |
|
527 | data_shaping_BW => bias_fail_sw_sig, | |
528 | debug_vector => lfr_debug_vector, |
|
528 | debug_vector => lfr_debug_vector, | |
529 | debug_vector_ms => lfr_debug_vector_ms |
|
529 | debug_vector_ms => lfr_debug_vector_ms | |
530 | ); |
|
530 | ); | |
531 |
|
531 | |||
532 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; |
|
532 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; | |
533 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); |
|
533 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); | |
534 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; |
|
534 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; | |
535 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; |
|
535 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; | |
536 | IO0 <= rstn_25; |
|
536 | IO0 <= rstn_25; | |
537 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid |
|
537 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid | |
538 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready |
|
538 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready | |
539 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full |
|
539 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full | |
540 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full |
|
540 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full | |
541 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 |
|
541 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 | |
542 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 |
|
542 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 | |
543 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 |
|
543 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 | |
544 |
|
544 | |||
545 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
545 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
546 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
546 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; | |
547 | END GENERATE all_sample; |
|
547 | END GENERATE all_sample; | |
548 |
|
548 | |||
549 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
549 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
550 | GENERIC MAP( |
|
550 | GENERIC MAP( | |
551 | ChannelCount => 8, |
|
551 | ChannelCount => 8, | |
552 | SampleNbBits => 14, |
|
552 | SampleNbBits => 14, | |
553 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
553 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |
554 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
554 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
555 | PORT MAP ( |
|
555 | PORT MAP ( | |
556 | -- CONV |
|
556 | -- CONV | |
557 | cnv_clk => clk_24, |
|
557 | cnv_clk => clk_24, | |
558 | cnv_rstn => rstn_25, |
|
558 | cnv_rstn => rstn_25, | |
559 | cnv => ADC_nCS_sig, |
|
559 | cnv => ADC_nCS_sig, | |
560 | -- DATA |
|
560 | -- DATA | |
561 | clk => clk_25, |
|
561 | clk => clk_25, | |
562 | rstn => rstn_25, |
|
562 | rstn => rstn_25, | |
563 | sck => ADC_CLK_sig, |
|
563 | sck => ADC_CLK_sig, | |
564 | sdo => ADC_SDO_sig, |
|
564 | sdo => ADC_SDO_sig, | |
565 | -- SAMPLE |
|
565 | -- SAMPLE | |
566 | sample => sample, |
|
566 | sample => sample, | |
567 | sample_val => sample_val); |
|
567 | sample_val => sample_val); | |
568 |
|
568 | |||
569 | --IO10 <= ADC_SDO_sig(5); |
|
569 | --IO10 <= ADC_SDO_sig(5); | |
570 | --IO9 <= ADC_SDO_sig(4); |
|
570 | --IO9 <= ADC_SDO_sig(4); | |
571 | --IO8 <= ADC_SDO_sig(3); |
|
571 | --IO8 <= ADC_SDO_sig(3); | |
572 |
|
572 | |||
573 | ADC_nCS <= ADC_nCS_sig; |
|
573 | ADC_nCS <= ADC_nCS_sig; | |
574 | ADC_CLK <= ADC_CLK_sig; |
|
574 | ADC_CLK <= ADC_CLK_sig; | |
575 | ADC_SDO_sig <= ADC_SDO; |
|
575 | ADC_SDO_sig <= ADC_SDO; | |
576 |
|
576 | |||
577 | ---------------------------------------------------------------------- |
|
577 | ---------------------------------------------------------------------- | |
578 | --- GPIO ----------------------------------------------------------- |
|
578 | --- GPIO ----------------------------------------------------------- | |
579 | ---------------------------------------------------------------------- |
|
579 | ---------------------------------------------------------------------- | |
580 |
|
580 | |||
581 | grgpio0 : grgpio |
|
581 | grgpio0 : grgpio | |
582 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
582 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
583 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
583 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
584 |
|
584 | |||
585 | gpioi.sig_en <= (OTHERS => '0'); |
|
585 | gpioi.sig_en <= (OTHERS => '0'); | |
586 | gpioi.sig_in <= (OTHERS => '0'); |
|
586 | gpioi.sig_in <= (OTHERS => '0'); | |
587 | gpioi.din <= (OTHERS => '0'); |
|
587 | gpioi.din <= (OTHERS => '0'); | |
588 | --pio_pad_0 : iopad |
|
588 | --pio_pad_0 : iopad | |
589 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
589 | -- GENERIC MAP (tech => CFG_PADTECH) | |
590 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
590 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
591 | --pio_pad_1 : iopad |
|
591 | --pio_pad_1 : iopad | |
592 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
592 | -- GENERIC MAP (tech => CFG_PADTECH) | |
593 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
593 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
594 | --pio_pad_2 : iopad |
|
594 | --pio_pad_2 : iopad | |
595 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
595 | -- GENERIC MAP (tech => CFG_PADTECH) | |
596 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
596 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
597 | --pio_pad_3 : iopad |
|
597 | --pio_pad_3 : iopad | |
598 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
598 | -- GENERIC MAP (tech => CFG_PADTECH) | |
599 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
599 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
600 | --pio_pad_4 : iopad |
|
600 | --pio_pad_4 : iopad | |
601 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
601 | -- GENERIC MAP (tech => CFG_PADTECH) | |
602 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
602 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
603 | --pio_pad_5 : iopad |
|
603 | --pio_pad_5 : iopad | |
604 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
604 | -- GENERIC MAP (tech => CFG_PADTECH) | |
605 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
605 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
606 | --pio_pad_6 : iopad |
|
606 | --pio_pad_6 : iopad | |
607 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
607 | -- GENERIC MAP (tech => CFG_PADTECH) | |
608 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
608 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
609 | --pio_pad_7 : iopad |
|
609 | --pio_pad_7 : iopad | |
610 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
610 | -- GENERIC MAP (tech => CFG_PADTECH) | |
611 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
611 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
612 |
|
612 | |||
613 | PROCESS (clk_25, rstn_25) |
|
613 | PROCESS (clk_25, rstn_25) | |
614 | BEGIN -- PROCESS |
|
614 | BEGIN -- PROCESS | |
615 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
615 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
616 | -- --IO0 <= '0'; |
|
616 | -- --IO0 <= '0'; | |
617 | -- IO1 <= '0'; |
|
617 | -- IO1 <= '0'; | |
618 | -- IO2 <= '0'; |
|
618 | -- IO2 <= '0'; | |
619 | -- IO3 <= '0'; |
|
619 | -- IO3 <= '0'; | |
620 | -- IO4 <= '0'; |
|
620 | -- IO4 <= '0'; | |
621 | -- IO5 <= '0'; |
|
621 | -- IO5 <= '0'; | |
622 | -- IO6 <= '0'; |
|
622 | -- IO6 <= '0'; | |
623 | -- IO7 <= '0'; |
|
623 | -- IO7 <= '0'; | |
624 | IO8 <= '0'; |
|
624 | IO8 <= '0'; | |
625 | IO9 <= '0'; |
|
625 | IO9 <= '0'; | |
626 | IO10 <= '0'; |
|
626 | IO10 <= '0'; | |
627 | IO11 <= '0'; |
|
627 | IO11 <= '0'; | |
628 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
628 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
629 | CASE gpioo.dout(2 DOWNTO 0) IS |
|
629 | CASE gpioo.dout(2 DOWNTO 0) IS | |
630 | WHEN "011" => |
|
630 | WHEN "011" => | |
631 | -- --IO0 <= observation_reg(0 ); |
|
631 | -- --IO0 <= observation_reg(0 ); | |
632 | -- IO1 <= observation_reg(1 ); |
|
632 | -- IO1 <= observation_reg(1 ); | |
633 | -- IO2 <= observation_reg(2 ); |
|
633 | -- IO2 <= observation_reg(2 ); | |
634 | -- IO3 <= observation_reg(3 ); |
|
634 | -- IO3 <= observation_reg(3 ); | |
635 | -- IO4 <= observation_reg(4 ); |
|
635 | -- IO4 <= observation_reg(4 ); | |
636 | -- IO5 <= observation_reg(5 ); |
|
636 | -- IO5 <= observation_reg(5 ); | |
637 | -- IO6 <= observation_reg(6 ); |
|
637 | -- IO6 <= observation_reg(6 ); | |
638 | -- IO7 <= observation_reg(7 ); |
|
638 | -- IO7 <= observation_reg(7 ); | |
639 | IO8 <= observation_reg(8); |
|
639 | IO8 <= observation_reg(8); | |
640 | IO9 <= observation_reg(9); |
|
640 | IO9 <= observation_reg(9); | |
641 | IO10 <= observation_reg(10); |
|
641 | IO10 <= observation_reg(10); | |
642 | IO11 <= observation_reg(11); |
|
642 | IO11 <= observation_reg(11); | |
643 | WHEN "001" => |
|
643 | WHEN "001" => | |
644 | -- --IO0 <= observation_reg(0 + 12); |
|
644 | -- --IO0 <= observation_reg(0 + 12); | |
645 | -- IO1 <= observation_reg(1 + 12); |
|
645 | -- IO1 <= observation_reg(1 + 12); | |
646 | -- IO2 <= observation_reg(2 + 12); |
|
646 | -- IO2 <= observation_reg(2 + 12); | |
647 | -- IO3 <= observation_reg(3 + 12); |
|
647 | -- IO3 <= observation_reg(3 + 12); | |
648 | -- IO4 <= observation_reg(4 + 12); |
|
648 | -- IO4 <= observation_reg(4 + 12); | |
649 | -- IO5 <= observation_reg(5 + 12); |
|
649 | -- IO5 <= observation_reg(5 + 12); | |
650 | -- IO6 <= observation_reg(6 + 12); |
|
650 | -- IO6 <= observation_reg(6 + 12); | |
651 | -- IO7 <= observation_reg(7 + 12); |
|
651 | -- IO7 <= observation_reg(7 + 12); | |
652 | IO8 <= observation_reg(8 + 12); |
|
652 | IO8 <= observation_reg(8 + 12); | |
653 | IO9 <= observation_reg(9 + 12); |
|
653 | IO9 <= observation_reg(9 + 12); | |
654 | IO10 <= observation_reg(10 + 12); |
|
654 | IO10 <= observation_reg(10 + 12); | |
655 | IO11 <= observation_reg(11 + 12); |
|
655 | IO11 <= observation_reg(11 + 12); | |
656 | WHEN "010" => |
|
656 | WHEN "010" => | |
657 | -- --IO0 <= observation_reg(0 + 12 + 12); |
|
657 | -- --IO0 <= observation_reg(0 + 12 + 12); | |
658 | -- IO1 <= observation_reg(1 + 12 + 12); |
|
658 | -- IO1 <= observation_reg(1 + 12 + 12); | |
659 | -- IO2 <= observation_reg(2 + 12 + 12); |
|
659 | -- IO2 <= observation_reg(2 + 12 + 12); | |
660 | -- IO3 <= observation_reg(3 + 12 + 12); |
|
660 | -- IO3 <= observation_reg(3 + 12 + 12); | |
661 | -- IO4 <= observation_reg(4 + 12 + 12); |
|
661 | -- IO4 <= observation_reg(4 + 12 + 12); | |
662 | -- IO5 <= observation_reg(5 + 12 + 12); |
|
662 | -- IO5 <= observation_reg(5 + 12 + 12); | |
663 | -- IO6 <= observation_reg(6 + 12 + 12); |
|
663 | -- IO6 <= observation_reg(6 + 12 + 12); | |
664 | -- IO7 <= observation_reg(7 + 12 + 12); |
|
664 | -- IO7 <= observation_reg(7 + 12 + 12); | |
665 | IO8 <= '0'; |
|
665 | IO8 <= '0'; | |
666 | IO9 <= '0'; |
|
666 | IO9 <= '0'; | |
667 | IO10 <= '0'; |
|
667 | IO10 <= '0'; | |
668 | IO11 <= '0'; |
|
668 | IO11 <= '0'; | |
669 | WHEN "000" => |
|
669 | WHEN "000" => | |
670 | -- --IO0 <= observation_vector_0(0 ); |
|
670 | -- --IO0 <= observation_vector_0(0 ); | |
671 | -- IO1 <= observation_vector_0(1 ); |
|
671 | -- IO1 <= observation_vector_0(1 ); | |
672 | -- IO2 <= observation_vector_0(2 ); |
|
672 | -- IO2 <= observation_vector_0(2 ); | |
673 | -- IO3 <= observation_vector_0(3 ); |
|
673 | -- IO3 <= observation_vector_0(3 ); | |
674 | -- IO4 <= observation_vector_0(4 ); |
|
674 | -- IO4 <= observation_vector_0(4 ); | |
675 | -- IO5 <= observation_vector_0(5 ); |
|
675 | -- IO5 <= observation_vector_0(5 ); | |
676 | -- IO6 <= observation_vector_0(6 ); |
|
676 | -- IO6 <= observation_vector_0(6 ); | |
677 | -- IO7 <= observation_vector_0(7 ); |
|
677 | -- IO7 <= observation_vector_0(7 ); | |
678 | IO8 <= observation_vector_0(8); |
|
678 | IO8 <= observation_vector_0(8); | |
679 | IO9 <= observation_vector_0(9); |
|
679 | IO9 <= observation_vector_0(9); | |
680 | IO10 <= observation_vector_0(10); |
|
680 | IO10 <= observation_vector_0(10); | |
681 | IO11 <= observation_vector_0(11); |
|
681 | IO11 <= observation_vector_0(11); | |
682 | WHEN "100" => |
|
682 | WHEN "100" => | |
683 | -- --IO0 <= observation_vector_1(0 ); |
|
683 | -- --IO0 <= observation_vector_1(0 ); | |
684 | -- IO1 <= observation_vector_1(1 ); |
|
684 | -- IO1 <= observation_vector_1(1 ); | |
685 | -- IO2 <= observation_vector_1(2 ); |
|
685 | -- IO2 <= observation_vector_1(2 ); | |
686 | -- IO3 <= observation_vector_1(3 ); |
|
686 | -- IO3 <= observation_vector_1(3 ); | |
687 | -- IO4 <= observation_vector_1(4 ); |
|
687 | -- IO4 <= observation_vector_1(4 ); | |
688 | -- IO5 <= observation_vector_1(5 ); |
|
688 | -- IO5 <= observation_vector_1(5 ); | |
689 | -- IO6 <= observation_vector_1(6 ); |
|
689 | -- IO6 <= observation_vector_1(6 ); | |
690 | -- IO7 <= observation_vector_1(7 ); |
|
690 | -- IO7 <= observation_vector_1(7 ); | |
691 | IO8 <= observation_vector_1(8); |
|
691 | IO8 <= observation_vector_1(8); | |
692 | IO9 <= observation_vector_1(9); |
|
692 | IO9 <= observation_vector_1(9); | |
693 | IO10 <= observation_vector_1(10); |
|
693 | IO10 <= observation_vector_1(10); | |
694 | IO11 <= observation_vector_1(11); |
|
694 | IO11 <= observation_vector_1(11); | |
695 | WHEN OTHERS => NULL; |
|
695 | WHEN OTHERS => NULL; | |
696 | END CASE; |
|
696 | END CASE; | |
697 |
|
697 | |||
698 | END IF; |
|
698 | END IF; | |
699 | END PROCESS; |
|
699 | END PROCESS; | |
700 | ----------------------------------------------------------------------------- |
|
700 | ----------------------------------------------------------------------------- | |
701 | -- |
|
701 | -- | |
702 | ----------------------------------------------------------------------------- |
|
702 | ----------------------------------------------------------------------------- | |
703 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE |
|
703 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE | |
704 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE |
|
704 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE | |
705 | apbo_ext(I) <= apb_none; |
|
705 | apbo_ext(I) <= apb_none; | |
706 | END GENERATE apbo_ext_not_used; |
|
706 | END GENERATE apbo_ext_not_used; | |
707 | END GENERATE all_apbo_ext; |
|
707 | END GENERATE all_apbo_ext; | |
708 |
|
708 | |||
709 |
|
709 | |||
710 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE |
|
710 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE | |
711 | ahbo_s_ext(I) <= ahbs_none; |
|
711 | ahbo_s_ext(I) <= ahbs_none; | |
712 | END GENERATE all_ahbo_ext; |
|
712 | END GENERATE all_ahbo_ext; | |
713 |
|
713 | |||
714 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE |
|
714 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE | |
715 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE |
|
715 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE | |
716 | ahbo_m_ext(I) <= ahbm_none; |
|
716 | ahbo_m_ext(I) <= ahbm_none; | |
717 | END GENERATE ahbo_m_ext_not_used; |
|
717 | END GENERATE ahbo_m_ext_not_used; | |
718 | END GENERATE all_ahbo_m_ext; |
|
718 | END GENERATE all_ahbo_m_ext; | |
719 |
|
719 | |||
720 | END beh; |
|
720 | END beh; |
@@ -1,484 +1,491 | |||||
1 | ----------------------------------------------------------------------------- |
|
1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
|
2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 |
|
19 | |||
20 |
|
20 | |||
21 | LIBRARY ieee; |
|
21 | LIBRARY ieee; | |
22 | USE ieee.std_logic_1164.ALL; |
|
22 | USE ieee.std_logic_1164.ALL; | |
23 | LIBRARY grlib; |
|
23 | LIBRARY grlib; | |
24 | USE grlib.amba.ALL; |
|
24 | USE grlib.amba.ALL; | |
25 | USE grlib.stdlib.ALL; |
|
25 | USE grlib.stdlib.ALL; | |
26 | LIBRARY techmap; |
|
26 | LIBRARY techmap; | |
27 | USE techmap.gencomp.ALL; |
|
27 | USE techmap.gencomp.ALL; | |
28 | LIBRARY gaisler; |
|
28 | LIBRARY gaisler; | |
29 | USE gaisler.memctrl.ALL; |
|
29 | USE gaisler.memctrl.ALL; | |
30 | USE gaisler.leon3.ALL; |
|
30 | USE gaisler.leon3.ALL; | |
31 | USE gaisler.uart.ALL; |
|
31 | USE gaisler.uart.ALL; | |
32 | USE gaisler.misc.ALL; |
|
32 | USE gaisler.misc.ALL; | |
33 | USE gaisler.spacewire.ALL; -- PLE |
|
33 | USE gaisler.spacewire.ALL; -- PLE | |
34 | LIBRARY esa; |
|
34 | LIBRARY esa; | |
35 | USE esa.memoryctrl.ALL; |
|
35 | USE esa.memoryctrl.ALL; | |
36 | LIBRARY lpp; |
|
36 | LIBRARY lpp; | |
37 | USE lpp.lpp_memory.ALL; |
|
37 | USE lpp.lpp_memory.ALL; | |
38 | USE lpp.lpp_ad_conv.ALL; |
|
38 | USE lpp.lpp_ad_conv.ALL; | |
39 | USE lpp.lpp_lfr_pkg.ALL; |
|
39 | USE lpp.lpp_lfr_pkg.ALL; | |
40 | USE lpp.iir_filter.ALL; |
|
40 | USE lpp.iir_filter.ALL; | |
41 | USE lpp.general_purpose.ALL; |
|
41 | USE lpp.general_purpose.ALL; | |
42 | USE lpp.lpp_lfr_time_management.ALL; |
|
42 | USE lpp.lpp_lfr_time_management.ALL; | |
43 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
43 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
44 | LIBRARY iap; |
|
44 | LIBRARY iap; | |
45 | USE iap.memctrl.all; |
|
45 | USE iap.memctrl.all; | |
46 |
|
46 | |||
47 |
|
47 | |||
48 | ENTITY leon3_soc IS |
|
48 | ENTITY leon3_soc IS | |
49 | GENERIC ( |
|
49 | GENERIC ( | |
50 | fabtech : INTEGER := apa3e; |
|
50 | fabtech : INTEGER := apa3e; | |
51 | memtech : INTEGER := apa3e; |
|
51 | memtech : INTEGER := apa3e; | |
52 | padtech : INTEGER := inferred; |
|
52 | padtech : INTEGER := inferred; | |
53 | clktech : INTEGER := inferred; |
|
53 | clktech : INTEGER := inferred; | |
54 | disas : INTEGER := 0; -- Enable disassembly to console |
|
54 | disas : INTEGER := 0; -- Enable disassembly to console | |
55 | dbguart : INTEGER := 0; -- Print UART on console |
|
55 | dbguart : INTEGER := 0; -- Print UART on console | |
56 | pclow : INTEGER := 2; |
|
56 | pclow : INTEGER := 2; | |
57 | -- |
|
57 | -- | |
58 | clk_freq : INTEGER := 25000; --kHz |
|
58 | clk_freq : INTEGER := 25000; --kHz | |
59 | -- |
|
59 | -- | |
60 | NB_CPU : INTEGER := 1; |
|
60 | NB_CPU : INTEGER := 1; | |
61 | ENABLE_FPU : INTEGER := 1; |
|
61 | ENABLE_FPU : INTEGER := 1; | |
62 | FPU_NETLIST : INTEGER := 1; |
|
62 | FPU_NETLIST : INTEGER := 1; | |
63 | ENABLE_DSU : INTEGER := 1; |
|
63 | ENABLE_DSU : INTEGER := 1; | |
64 | ENABLE_AHB_UART : INTEGER := 1; |
|
64 | ENABLE_AHB_UART : INTEGER := 1; | |
65 | ENABLE_APB_UART : INTEGER := 1; |
|
65 | ENABLE_APB_UART : INTEGER := 1; | |
66 | ENABLE_IRQMP : INTEGER := 1; |
|
66 | ENABLE_IRQMP : INTEGER := 1; | |
67 | ENABLE_GPT : INTEGER := 1; |
|
67 | ENABLE_GPT : INTEGER := 1; | |
68 | -- |
|
68 | -- | |
69 | NB_AHB_MASTER : INTEGER := 0; |
|
69 | NB_AHB_MASTER : INTEGER := 0; | |
70 | NB_AHB_SLAVE : INTEGER := 0; |
|
70 | NB_AHB_SLAVE : INTEGER := 0; | |
71 | NB_APB_SLAVE : INTEGER := 0; |
|
71 | NB_APB_SLAVE : INTEGER := 0; | |
72 | -- |
|
72 | -- | |
73 | ADDRESS_SIZE : INTEGER := 20; |
|
73 | ADDRESS_SIZE : INTEGER := 20; | |
74 | USES_IAP_MEMCTRLR : INTEGER := 0 |
|
74 | USES_IAP_MEMCTRLR : INTEGER := 0 | |
75 |
|
75 | |||
76 | ); |
|
76 | ); | |
77 | PORT ( |
|
77 | PORT ( | |
78 | clk : IN STD_ULOGIC; |
|
78 | clk : IN STD_ULOGIC; | |
79 | reset : IN STD_ULOGIC; |
|
79 | reset : IN STD_ULOGIC; | |
80 |
|
80 | |||
81 | errorn : OUT STD_ULOGIC; |
|
81 | errorn : OUT STD_ULOGIC; | |
82 |
|
82 | |||
83 | -- UART AHB --------------------------------------------------------------- |
|
83 | -- UART AHB --------------------------------------------------------------- | |
84 | ahbrxd : IN STD_ULOGIC; -- DSU rx data |
|
84 | ahbrxd : IN STD_ULOGIC; -- DSU rx data | |
85 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data |
|
85 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data | |
86 |
|
86 | |||
87 | -- UART APB --------------------------------------------------------------- |
|
87 | -- UART APB --------------------------------------------------------------- | |
88 | urxd1 : IN STD_ULOGIC; -- UART1 rx data |
|
88 | urxd1 : IN STD_ULOGIC; -- UART1 rx data | |
89 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data |
|
89 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data | |
90 |
|
90 | |||
91 | -- RAM -------------------------------------------------------------------- |
|
91 | -- RAM -------------------------------------------------------------------- | |
92 | address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0); |
|
92 | address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0); | |
93 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
94 | nSRAM_BE0 : OUT STD_LOGIC; |
|
94 | nSRAM_BE0 : OUT STD_LOGIC; | |
95 | nSRAM_BE1 : OUT STD_LOGIC; |
|
95 | nSRAM_BE1 : OUT STD_LOGIC; | |
96 | nSRAM_BE2 : OUT STD_LOGIC; |
|
96 | nSRAM_BE2 : OUT STD_LOGIC; | |
97 | nSRAM_BE3 : OUT STD_LOGIC; |
|
97 | nSRAM_BE3 : OUT STD_LOGIC; | |
98 | nSRAM_WE : OUT STD_LOGIC; |
|
98 | nSRAM_WE : OUT STD_LOGIC; | |
99 | nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0); |
|
99 | nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0); | |
100 | nSRAM_OE : OUT STD_LOGIC; |
|
100 | nSRAM_OE : OUT STD_LOGIC; | |
101 | nSRAM_READY : IN STD_LOGIC; |
|
101 | nSRAM_READY : IN STD_LOGIC; | |
102 | SRAM_MBE : INOUT STD_LOGIC; |
|
102 | SRAM_MBE : INOUT STD_LOGIC; | |
103 | -- APB -------------------------------------------------------------------- |
|
103 | -- APB -------------------------------------------------------------------- | |
104 | apbi_ext : OUT apb_slv_in_type; |
|
104 | apbi_ext : OUT apb_slv_in_type; | |
105 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); |
|
105 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); | |
106 | -- AHB_Slave -------------------------------------------------------------- |
|
106 | -- AHB_Slave -------------------------------------------------------------- | |
107 | ahbi_s_ext : OUT ahb_slv_in_type; |
|
107 | ahbi_s_ext : OUT ahb_slv_in_type; | |
108 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); |
|
108 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); | |
109 | -- AHB_Master ------------------------------------------------------------- |
|
109 | -- AHB_Master ------------------------------------------------------------- | |
110 | ahbi_m_ext : OUT AHB_Mst_In_Type; |
|
110 | ahbi_m_ext : OUT AHB_Mst_In_Type; | |
111 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) |
|
111 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) | |
112 |
|
112 | |||
113 | ); |
|
113 | ); | |
114 | END; |
|
114 | END; | |
115 |
|
115 | |||
116 | ARCHITECTURE Behavioral OF leon3_soc IS |
|
116 | ARCHITECTURE Behavioral OF leon3_soc IS | |
117 |
|
117 | |||
118 | ----------------------------------------------------------------------------- |
|
118 | ----------------------------------------------------------------------------- | |
119 | -- CONFIG ------------------------------------------------------------------- |
|
119 | -- CONFIG ------------------------------------------------------------------- | |
120 | ----------------------------------------------------------------------------- |
|
120 | ----------------------------------------------------------------------------- | |
121 |
|
121 | |||
122 | -- Clock generator |
|
122 | -- Clock generator | |
123 | constant CFG_CLKMUL : integer := (1); |
|
123 | constant CFG_CLKMUL : integer := (1); | |
124 | constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz |
|
124 | constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz | |
125 | constant CFG_OCLKDIV : integer := (1); |
|
125 | constant CFG_OCLKDIV : integer := (1); | |
126 | constant CFG_CLK_NOFB : integer := 0; |
|
126 | constant CFG_CLK_NOFB : integer := 0; | |
127 | -- LEON3 processor core |
|
127 | -- LEON3 processor core | |
128 | constant CFG_LEON3 : integer := 1; |
|
128 | constant CFG_LEON3 : integer := 1; | |
129 | constant CFG_NCPU : integer := NB_CPU; |
|
129 | constant CFG_NCPU : integer := NB_CPU; | |
130 | constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC |
|
130 | constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC | |
131 | constant CFG_V8 : integer := 0; |
|
131 | constant CFG_V8 : integer := 0; | |
132 | constant CFG_MAC : integer := 0; |
|
132 | constant CFG_MAC : integer := 0; | |
133 | constant CFG_SVT : integer := 0; |
|
133 | constant CFG_SVT : integer := 0; | |
134 | constant CFG_RSTADDR : integer := 16#00000#; |
|
134 | constant CFG_RSTADDR : integer := 16#00000#; | |
135 | constant CFG_LDDEL : integer := (1); |
|
135 | constant CFG_LDDEL : integer := (1); | |
136 | constant CFG_NWP : integer := (0); |
|
136 | constant CFG_NWP : integer := (0); | |
137 | constant CFG_PWD : integer := 1*2; |
|
137 | constant CFG_PWD : integer := 1*2; | |
138 | constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST); |
|
138 | constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST); | |
139 | -- 1*(8 + 16 * 0) => grfpu-light |
|
139 | -- 1*(8 + 16 * 0) => grfpu-light | |
140 | -- 1*(8 + 16 * 1) => netlist |
|
140 | -- 1*(8 + 16 * 1) => netlist | |
141 | -- 0*(8 + 16 * 0) => No FPU |
|
141 | -- 0*(8 + 16 * 0) => No FPU | |
142 | -- 0*(8 + 16 * 1) => No FPU; |
|
142 | -- 0*(8 + 16 * 1) => No FPU; | |
143 | constant CFG_ICEN : integer := 1; |
|
143 | constant CFG_ICEN : integer := 1; | |
144 | constant CFG_ISETS : integer := 1; |
|
144 | constant CFG_ISETS : integer := 1; | |
145 | constant CFG_ISETSZ : integer := 4; |
|
145 | constant CFG_ISETSZ : integer := 4; | |
146 | constant CFG_ILINE : integer := 4; |
|
146 | constant CFG_ILINE : integer := 4; | |
147 | constant CFG_IREPL : integer := 0; |
|
147 | constant CFG_IREPL : integer := 0; | |
148 | constant CFG_ILOCK : integer := 0; |
|
148 | constant CFG_ILOCK : integer := 0; | |
149 | constant CFG_ILRAMEN : integer := 0; |
|
149 | constant CFG_ILRAMEN : integer := 0; | |
150 | constant CFG_ILRAMADDR: integer := 16#8E#; |
|
150 | constant CFG_ILRAMADDR: integer := 16#8E#; | |
151 | constant CFG_ILRAMSZ : integer := 1; |
|
151 | constant CFG_ILRAMSZ : integer := 1; | |
152 | constant CFG_DCEN : integer := 1; |
|
152 | constant CFG_DCEN : integer := 1; | |
153 | constant CFG_DSETS : integer := 1; |
|
153 | constant CFG_DSETS : integer := 1; | |
154 | constant CFG_DSETSZ : integer := 4; |
|
154 | constant CFG_DSETSZ : integer := 4; | |
155 | constant CFG_DLINE : integer := 4; |
|
155 | constant CFG_DLINE : integer := 4; | |
156 | constant CFG_DREPL : integer := 0; |
|
156 | constant CFG_DREPL : integer := 0; | |
157 | constant CFG_DLOCK : integer := 0; |
|
157 | constant CFG_DLOCK : integer := 0; | |
158 | constant CFG_DSNOOP : integer := 0 + 0 + 4*0; |
|
158 | constant CFG_DSNOOP : integer := 0 + 0 + 4*0; | |
159 | constant CFG_DLRAMEN : integer := 0; |
|
159 | constant CFG_DLRAMEN : integer := 0; | |
160 | constant CFG_DLRAMADDR: integer := 16#8F#; |
|
160 | constant CFG_DLRAMADDR: integer := 16#8F#; | |
161 | constant CFG_DLRAMSZ : integer := 1; |
|
161 | constant CFG_DLRAMSZ : integer := 1; | |
162 | constant CFG_MMUEN : integer := 0; |
|
162 | constant CFG_MMUEN : integer := 0; | |
163 | constant CFG_ITLBNUM : integer := 2; |
|
163 | constant CFG_ITLBNUM : integer := 2; | |
164 | constant CFG_DTLBNUM : integer := 2; |
|
164 | constant CFG_DTLBNUM : integer := 2; | |
165 | constant CFG_TLB_TYPE : integer := 1 + 0*2; |
|
165 | constant CFG_TLB_TYPE : integer := 1 + 0*2; | |
166 | constant CFG_TLB_REP : integer := 1; |
|
166 | constant CFG_TLB_REP : integer := 1; | |
167 |
|
167 | |||
168 | constant CFG_DSU : integer := ENABLE_DSU; |
|
168 | constant CFG_DSU : integer := ENABLE_DSU; | |
169 | constant CFG_ITBSZ : integer := 0; |
|
169 | constant CFG_ITBSZ : integer := 0; | |
170 | constant CFG_ATBSZ : integer := 0; |
|
170 | constant CFG_ATBSZ : integer := 0; | |
171 |
|
171 | |||
172 | -- AMBA settings |
|
172 | -- AMBA settings | |
173 | constant CFG_DEFMST : integer := (0); |
|
173 | constant CFG_DEFMST : integer := (0); | |
174 | constant CFG_RROBIN : integer := 1; |
|
174 | constant CFG_RROBIN : integer := 1; | |
175 | constant CFG_SPLIT : integer := 0; |
|
175 | constant CFG_SPLIT : integer := 0; | |
176 | constant CFG_AHBIO : integer := 16#FFF#; |
|
176 | constant CFG_AHBIO : integer := 16#FFF#; | |
177 | constant CFG_APBADDR : integer := 16#800#; |
|
177 | constant CFG_APBADDR : integer := 16#800#; | |
178 |
|
178 | |||
179 | -- DSU UART |
|
179 | -- DSU UART | |
180 | constant CFG_AHB_UART : integer := ENABLE_AHB_UART; |
|
180 | constant CFG_AHB_UART : integer := ENABLE_AHB_UART; | |
181 |
|
181 | |||
182 | -- LEON2 memory controller |
|
182 | -- LEON2 memory controller | |
183 | constant CFG_MCTRL_SDEN : integer := 0; |
|
183 | constant CFG_MCTRL_SDEN : integer := 0; | |
184 |
|
184 | |||
185 | -- UART 1 |
|
185 | -- UART 1 | |
186 | constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART; |
|
186 | constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART; | |
187 | constant CFG_UART1_FIFO : integer := 1; |
|
187 | constant CFG_UART1_FIFO : integer := 1; | |
188 |
|
188 | |||
189 | -- LEON3 interrupt controller |
|
189 | -- LEON3 interrupt controller | |
190 | constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP; |
|
190 | constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP; | |
191 |
|
191 | |||
192 | -- Modular timer |
|
192 | -- Modular timer | |
193 | constant CFG_GPT_ENABLE : integer := ENABLE_GPT; |
|
193 | constant CFG_GPT_ENABLE : integer := ENABLE_GPT; | |
194 | constant CFG_GPT_NTIM : integer := (2); |
|
194 | constant CFG_GPT_NTIM : integer := (2); | |
195 | constant CFG_GPT_SW : integer := (8); |
|
195 | constant CFG_GPT_SW : integer := (8); | |
196 | constant CFG_GPT_TW : integer := (32); |
|
196 | constant CFG_GPT_TW : integer := (32); | |
197 | constant CFG_GPT_IRQ : integer := (8); |
|
197 | constant CFG_GPT_IRQ : integer := (8); | |
198 | constant CFG_GPT_SEPIRQ : integer := 1; |
|
198 | constant CFG_GPT_SEPIRQ : integer := 1; | |
199 | constant CFG_GPT_WDOGEN : integer := 0; |
|
199 | constant CFG_GPT_WDOGEN : integer := 0; | |
200 | constant CFG_GPT_WDOG : integer := 16#0#; |
|
200 | constant CFG_GPT_WDOG : integer := 16#0#; | |
201 | ----------------------------------------------------------------------------- |
|
201 | ----------------------------------------------------------------------------- | |
202 |
|
202 | |||
203 | ----------------------------------------------------------------------------- |
|
203 | ----------------------------------------------------------------------------- | |
204 | -- SIGNALs |
|
204 | -- SIGNALs | |
205 | ----------------------------------------------------------------------------- |
|
205 | ----------------------------------------------------------------------------- | |
206 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; |
|
206 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; | |
207 | -- CLK & RST -- |
|
207 | -- CLK & RST -- | |
208 | SIGNAL clk2x : STD_ULOGIC; |
|
208 | SIGNAL clk2x : STD_ULOGIC; | |
209 | SIGNAL clkmn : STD_ULOGIC; |
|
209 | SIGNAL clkmn : STD_ULOGIC; | |
210 | SIGNAL clkm : STD_ULOGIC; |
|
210 | SIGNAL clkm : STD_ULOGIC; | |
211 | SIGNAL rstn : STD_ULOGIC; |
|
211 | SIGNAL rstn : STD_ULOGIC; | |
212 | SIGNAL rstraw : STD_ULOGIC; |
|
212 | SIGNAL rstraw : STD_ULOGIC; | |
213 | SIGNAL pciclk : STD_ULOGIC; |
|
213 | SIGNAL pciclk : STD_ULOGIC; | |
214 | SIGNAL sdclkl : STD_ULOGIC; |
|
214 | SIGNAL sdclkl : STD_ULOGIC; | |
215 | SIGNAL cgi : clkgen_in_type; |
|
215 | SIGNAL cgi : clkgen_in_type; | |
216 | SIGNAL cgo : clkgen_out_type; |
|
216 | SIGNAL cgo : clkgen_out_type; | |
217 | --- AHB / APB |
|
217 | --- AHB / APB | |
218 | SIGNAL apbi : apb_slv_in_type; |
|
218 | SIGNAL apbi : apb_slv_in_type; | |
219 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
|
219 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
220 | SIGNAL ahbsi : ahb_slv_in_type; |
|
220 | SIGNAL ahbsi : ahb_slv_in_type; | |
221 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
|
221 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
222 | SIGNAL ahbmi : ahb_mst_in_type; |
|
222 | SIGNAL ahbmi : ahb_mst_in_type; | |
223 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
|
223 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
224 | --UART |
|
224 | --UART | |
225 | SIGNAL ahbuarti : uart_in_type; |
|
225 | SIGNAL ahbuarti : uart_in_type; | |
226 | SIGNAL ahbuarto : uart_out_type; |
|
226 | SIGNAL ahbuarto : uart_out_type; | |
227 | SIGNAL apbuarti : uart_in_type; |
|
227 | SIGNAL apbuarti : uart_in_type; | |
228 | SIGNAL apbuarto : uart_out_type; |
|
228 | SIGNAL apbuarto : uart_out_type; | |
229 | --MEM CTRLR |
|
229 | --MEM CTRLR | |
230 | SIGNAL memi : memory_in_type; |
|
230 | SIGNAL memi : memory_in_type; | |
231 | SIGNAL memo : memory_out_type; |
|
231 | SIGNAL memo : memory_out_type; | |
232 | SIGNAL wpo : wprot_out_type; |
|
232 | SIGNAL wpo : wprot_out_type; | |
233 | SIGNAL sdo : sdram_out_type; |
|
233 | SIGNAL sdo : sdram_out_type; | |
234 | SIGNAl mbe : std_logic; -- enable memory programming |
|
234 | SIGNAl mbe : std_logic; -- enable memory programming | |
235 | SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal |
|
235 | SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal | |
236 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0); |
|
236 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0); | |
|
237 | SIGNAL nSRAM_OE_s : STD_LOGIC; | |||
237 | --IRQ |
|
238 | --IRQ | |
238 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); |
|
239 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); | |
239 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); |
|
240 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); | |
240 | --Timer |
|
241 | --Timer | |
241 | SIGNAL gpti : gptimer_in_type; |
|
242 | SIGNAL gpti : gptimer_in_type; | |
242 | SIGNAL gpto : gptimer_out_type; |
|
243 | SIGNAL gpto : gptimer_out_type; | |
243 | --DSU |
|
244 | --DSU | |
244 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); |
|
245 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); | |
245 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); |
|
246 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); | |
246 | SIGNAL dsui : dsu_in_type; |
|
247 | SIGNAL dsui : dsu_in_type; | |
247 | SIGNAL dsuo : dsu_out_type; |
|
248 | SIGNAL dsuo : dsu_out_type; | |
248 | ----------------------------------------------------------------------------- |
|
249 | ----------------------------------------------------------------------------- | |
249 |
|
250 | |||
250 |
|
251 | |||
251 | BEGIN |
|
252 | BEGIN | |
252 |
|
253 | |||
253 |
|
254 | |||
254 | ---------------------------------------------------------------------- |
|
255 | ---------------------------------------------------------------------- | |
255 | --- Reset and Clock generation ------------------------------------- |
|
256 | --- Reset and Clock generation ------------------------------------- | |
256 | ---------------------------------------------------------------------- |
|
257 | ---------------------------------------------------------------------- | |
257 |
|
258 | |||
258 | cgi.pllctrl <= "00"; |
|
259 | cgi.pllctrl <= "00"; | |
259 | cgi.pllrst <= rstraw; |
|
260 | cgi.pllrst <= rstraw; | |
260 |
|
261 | |||
261 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); |
|
262 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); | |
262 |
|
263 | |||
263 | clkgen0 : clkgen -- clock generator |
|
264 | clkgen0 : clkgen -- clock generator | |
264 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
265 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
265 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) |
|
266 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) | |
266 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); |
|
267 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); | |
267 |
|
268 | |||
268 | ---------------------------------------------------------------------- |
|
269 | ---------------------------------------------------------------------- | |
269 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
270 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
270 | ---------------------------------------------------------------------- |
|
271 | ---------------------------------------------------------------------- | |
271 |
|
272 | |||
272 | l3 : IF CFG_LEON3 = 1 GENERATE |
|
273 | l3 : IF CFG_LEON3 = 1 GENERATE | |
273 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
274 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
274 | u0 : leon3s -- LEON3 processor |
|
275 | u0 : leon3s -- LEON3 processor | |
275 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
276 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
276 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
277 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
277 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
278 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
278 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
279 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
279 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
280 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
280 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
281 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) | |
281 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
282 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, | |
282 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
283 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
283 | END GENERATE; |
|
284 | END GENERATE; | |
284 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); |
|
285 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); | |
285 |
|
286 | |||
286 | dsugen : IF CFG_DSU = 1 GENERATE |
|
287 | dsugen : IF CFG_DSU = 1 GENERATE | |
287 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
288 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
288 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
289 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
289 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
290 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
290 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
291 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
291 | dsui.enable <= '1'; |
|
292 | dsui.enable <= '1'; | |
292 | dsui.break <= '0'; |
|
293 | dsui.break <= '0'; | |
293 | END GENERATE; |
|
294 | END GENERATE; | |
294 | END GENERATE; |
|
295 | END GENERATE; | |
295 |
|
296 | |||
296 | nodsu : IF CFG_DSU = 0 GENERATE |
|
297 | nodsu : IF CFG_DSU = 0 GENERATE | |
297 | ahbso(2) <= ahbs_none; |
|
298 | ahbso(2) <= ahbs_none; | |
298 | dsuo.tstop <= '0'; |
|
299 | dsuo.tstop <= '0'; | |
299 | dsuo.active <= '0'; |
|
300 | dsuo.active <= '0'; | |
300 | END GENERATE; |
|
301 | END GENERATE; | |
301 |
|
302 | |||
302 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE |
|
303 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE | |
303 | irqctrl0 : irqmp -- interrupt controller |
|
304 | irqctrl0 : irqmp -- interrupt controller | |
304 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
305 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
305 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
306 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
306 | END GENERATE; |
|
307 | END GENERATE; | |
307 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE |
|
308 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE | |
308 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
309 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
309 | irqi(i).irl <= "0000"; |
|
310 | irqi(i).irl <= "0000"; | |
310 | END GENERATE; |
|
311 | END GENERATE; | |
311 | apbo(2) <= apb_none; |
|
312 | apbo(2) <= apb_none; | |
312 | END GENERATE; |
|
313 | END GENERATE; | |
313 |
|
314 | |||
314 | ---------------------------------------------------------------------- |
|
315 | ---------------------------------------------------------------------- | |
315 | --- Memory controllers --------------------------------------------- |
|
316 | --- Memory controllers --------------------------------------------- | |
316 | ---------------------------------------------------------------------- |
|
317 | ---------------------------------------------------------------------- | |
317 | ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE |
|
318 | ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE | |
318 | memctrlr : mctrl GENERIC MAP ( |
|
319 | memctrlr : mctrl GENERIC MAP ( | |
319 | hindex => 0, |
|
320 | hindex => 0, | |
320 | pindex => 0, |
|
321 | pindex => 0, | |
321 | paddr => 0, |
|
322 | paddr => 0, | |
322 | srbanks => 1 |
|
323 | srbanks => 1 | |
323 | ) |
|
324 | ) | |
324 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
325 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
325 | memi.bexcn <= '1'; |
|
326 | memi.bexcn <= '1'; | |
326 | memi.brdyn <= '1'; |
|
327 | memi.brdyn <= '1'; | |
|
328 | ||||
|
329 | nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0)); | |||
|
330 | nSRAM_OE_s <= memo.ramoen(0); | |||
327 | END GENERATE; |
|
331 | END GENERATE; | |
328 |
|
332 | |||
329 | IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE |
|
333 | IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE | |
330 | memctrlr : srctrle_0ws |
|
334 | memctrlr : srctrle_0ws | |
331 | GENERIC MAP( |
|
335 | GENERIC MAP( | |
332 | hindex => 0, |
|
336 | hindex => 0, | |
333 | pindex => 0, |
|
337 | pindex => 0, | |
334 | paddr => 0, |
|
338 | paddr => 0, | |
335 | srbanks => 2, |
|
339 | srbanks => 2, | |
336 | banksz => 8, --512k * 32 |
|
340 | banksz => 8, --512k * 32 | |
337 | rmw => 1, |
|
341 | rmw => 1, | |
338 | --Aeroflex memory generics: |
|
342 | --Aeroflex memory generics: | |
339 | mprog => 1, -- program memory by default values after reset |
|
343 | mprog => 1, -- program memory by default values after reset | |
340 | mpsrate => 12, -- default scrub rate period |
|
344 | mpsrate => 12, -- default scrub rate period | |
341 | mpb2s => 4, -- default busy to scrub delay |
|
345 | mpb2s => 4, -- default busy to scrub delay | |
342 | mpapb => 1, -- instantiate apb register |
|
346 | mpapb => 1, -- instantiate apb register | |
343 | mchipcnt => 2, |
|
347 | mchipcnt => 2, | |
344 | mpenall => 1 -- when 0 program only E1 chip, else program all dies |
|
348 | mpenall => 1 -- when 0 program only E1 chip, else program all dies | |
345 | ) |
|
349 | ) | |
346 | PORT MAP ( |
|
350 | PORT MAP ( | |
347 | rst => rstn, |
|
351 | rst => rstn, | |
348 | clk => clkm, |
|
352 | clk => clkm, | |
349 | ahbsi => ahbsi, |
|
353 | ahbsi => ahbsi, | |
350 | ahbso => ahbso(0), |
|
354 | ahbso => ahbso(0), | |
351 | apbi => apbi, |
|
355 | apbi => apbi, | |
352 | apbo => apbo(0), |
|
356 | apbo => apbo(0), | |
353 | sri => memi, |
|
357 | sri => memi, | |
354 | sro => memo, |
|
358 | sro => memo, | |
355 | --Aeroflex memory signals: |
|
359 | --Aeroflex memory signals: | |
356 | ucerr => open, -- uncorrectable error signal |
|
360 | ucerr => open, -- uncorrectable error signal | |
357 | mbe => mbe, -- enable memory programming |
|
361 | mbe => mbe, -- enable memory programming | |
358 | mbe_drive => mbe_drive -- drive the MBE memory signal |
|
362 | mbe_drive => mbe_drive -- drive the MBE memory signal | |
359 | ); |
|
363 | ); | |
360 |
|
364 | |||
361 | memi.brdyn <= nSRAM_READY; |
|
365 | memi.brdyn <= nSRAM_READY; | |
362 |
|
366 | |||
363 | mbe_pad : iopad |
|
367 | mbe_pad : iopad | |
364 | GENERIC MAP(tech => padtech) |
|
368 | GENERIC MAP(tech => padtech) | |
365 | PORT MAP(pad => SRAM_MBE, |
|
369 | PORT MAP(pad => SRAM_MBE, | |
366 | i => mbe, |
|
370 | i => mbe, | |
367 | en => mbe_drive, |
|
371 | en => mbe_drive, | |
368 | o => memi.bexcn ); |
|
372 | o => memi.bexcn ); | |
|
373 | ||||
|
374 | nSRAM_CE_s <= (memo.ramsn(1 downto 0)); | |||
|
375 | nSRAM_OE_s <= memo.oen; | |||
|
376 | ||||
369 | END GENERATE; |
|
377 | END GENERATE; | |
370 |
|
378 | |||
371 |
|
379 | |||
372 | memi.writen <= '1'; |
|
380 | memi.writen <= '1'; | |
373 | memi.wrn <= "1111"; |
|
381 | memi.wrn <= "1111"; | |
374 | memi.bwidth <= "10"; |
|
382 | memi.bwidth <= "10"; | |
375 |
|
383 | |||
376 | bdr : FOR i IN 0 TO 3 GENERATE |
|
384 | bdr : FOR i IN 0 TO 3 GENERATE | |
377 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR) |
|
385 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR) | |
378 | PORT MAP ( |
|
386 | PORT MAP ( | |
379 | data(31-i*8 DOWNTO 24-i*8), |
|
387 | data(31-i*8 DOWNTO 24-i*8), | |
380 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
388 | memo.data(31-i*8 DOWNTO 24-i*8), | |
381 | memo.bdrive(i), |
|
389 | memo.bdrive(i), | |
382 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
390 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
383 | END GENERATE; |
|
391 | END GENERATE; | |
384 |
|
392 | |||
385 | addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech) |
|
393 | addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech) | |
386 | PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2)); |
|
394 | PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2)); | |
387 | nSRAM_CE_s <= (memo.ramsn(1 downto 0)); |
|
|||
388 | rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s); |
|
395 | rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s); | |
389 |
oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, |
|
396 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s); | |
390 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
397 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
391 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
398 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
392 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
399 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
393 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
400 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
394 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
401 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
395 |
|
402 | |||
396 |
|
403 | |||
397 |
|
404 | |||
398 | ---------------------------------------------------------------------- |
|
405 | ---------------------------------------------------------------------- | |
399 | --- AHB CONTROLLER ------------------------------------------------- |
|
406 | --- AHB CONTROLLER ------------------------------------------------- | |
400 | ---------------------------------------------------------------------- |
|
407 | ---------------------------------------------------------------------- | |
401 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
408 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
402 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
409 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
403 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
410 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
404 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) |
|
411 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) | |
405 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
412 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
406 |
|
413 | |||
407 | ---------------------------------------------------------------------- |
|
414 | ---------------------------------------------------------------------- | |
408 | --- AHB UART ------------------------------------------------------- |
|
415 | --- AHB UART ------------------------------------------------------- | |
409 | ---------------------------------------------------------------------- |
|
416 | ---------------------------------------------------------------------- | |
410 | dcomgen : IF CFG_AHB_UART = 1 GENERATE |
|
417 | dcomgen : IF CFG_AHB_UART = 1 GENERATE | |
411 | dcom0 : ahbuart |
|
418 | dcom0 : ahbuart | |
412 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) |
|
419 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) | |
413 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); |
|
420 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); | |
414 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); |
|
421 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); | |
415 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); |
|
422 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); | |
416 | END GENERATE; |
|
423 | END GENERATE; | |
417 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; |
|
424 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; | |
418 |
|
425 | |||
419 | ---------------------------------------------------------------------- |
|
426 | ---------------------------------------------------------------------- | |
420 | --- APB Bridge ----------------------------------------------------- |
|
427 | --- APB Bridge ----------------------------------------------------- | |
421 | ---------------------------------------------------------------------- |
|
428 | ---------------------------------------------------------------------- | |
422 | apb0 : apbctrl -- AHB/APB bridge |
|
429 | apb0 : apbctrl -- AHB/APB bridge | |
423 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) |
|
430 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) | |
424 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); |
|
431 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); | |
425 |
|
432 | |||
426 | ---------------------------------------------------------------------- |
|
433 | ---------------------------------------------------------------------- | |
427 | --- GPT Timer ------------------------------------------------------ |
|
434 | --- GPT Timer ------------------------------------------------------ | |
428 | ---------------------------------------------------------------------- |
|
435 | ---------------------------------------------------------------------- | |
429 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE |
|
436 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE | |
430 | timer0 : gptimer -- timer unit |
|
437 | timer0 : gptimer -- timer unit | |
431 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
438 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
432 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
439 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
433 | nbits => CFG_GPT_TW) |
|
440 | nbits => CFG_GPT_TW) | |
434 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); |
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441 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
435 | gpti.dhalt <= dsuo.tstop; |
|
442 | gpti.dhalt <= dsuo.tstop; | |
436 | gpti.extclk <= '0'; |
|
443 | gpti.extclk <= '0'; | |
437 | END GENERATE; |
|
444 | END GENERATE; | |
438 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; |
|
445 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; | |
439 |
|
446 | |||
440 |
|
447 | |||
441 | ---------------------------------------------------------------------- |
|
448 | ---------------------------------------------------------------------- | |
442 | --- APB UART ------------------------------------------------------- |
|
449 | --- APB UART ------------------------------------------------------- | |
443 | ---------------------------------------------------------------------- |
|
450 | ---------------------------------------------------------------------- | |
444 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE |
|
451 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE | |
445 | uart1 : apbuart -- UART 1 |
|
452 | uart1 : apbuart -- UART 1 | |
446 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
453 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
447 | fifosize => CFG_UART1_FIFO) |
|
454 | fifosize => CFG_UART1_FIFO) | |
448 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); |
|
455 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
449 | apbuarti.rxd <= urxd1; |
|
456 | apbuarti.rxd <= urxd1; | |
450 | apbuarti.extclk <= '0'; |
|
457 | apbuarti.extclk <= '0'; | |
451 | utxd1 <= apbuarto.txd; |
|
458 | utxd1 <= apbuarto.txd; | |
452 | apbuarti.ctsn <= '0'; |
|
459 | apbuarti.ctsn <= '0'; | |
453 | END GENERATE; |
|
460 | END GENERATE; | |
454 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; |
|
461 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; | |
455 |
|
462 | |||
456 | ------------------------------------------------------------------------------- |
|
463 | ------------------------------------------------------------------------------- | |
457 | -- AMBA BUS ------------------------------------------------------------------- |
|
464 | -- AMBA BUS ------------------------------------------------------------------- | |
458 | ------------------------------------------------------------------------------- |
|
465 | ------------------------------------------------------------------------------- | |
459 |
|
466 | |||
460 | -- APB -------------------------------------------------------------------- |
|
467 | -- APB -------------------------------------------------------------------- | |
461 | apbi_ext <= apbi; |
|
468 | apbi_ext <= apbi; | |
462 | all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE |
|
469 | all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE | |
463 | max_16_apb: IF I + 5 < 16 GENERATE |
|
470 | max_16_apb: IF I + 5 < 16 GENERATE | |
464 | apbo(I+5)<= apbo_ext(I+5); |
|
471 | apbo(I+5)<= apbo_ext(I+5); | |
465 | END GENERATE max_16_apb; |
|
472 | END GENERATE max_16_apb; | |
466 | END GENERATE all_apb; |
|
473 | END GENERATE all_apb; | |
467 | -- AHB_Slave -------------------------------------------------------------- |
|
474 | -- AHB_Slave -------------------------------------------------------------- | |
468 | ahbi_s_ext <= ahbsi; |
|
475 | ahbi_s_ext <= ahbsi; | |
469 | all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE |
|
476 | all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE | |
470 | max_16_ahbs: IF I + 3 < 16 GENERATE |
|
477 | max_16_ahbs: IF I + 3 < 16 GENERATE | |
471 | ahbso(I+3) <= ahbo_s_ext(I+3); |
|
478 | ahbso(I+3) <= ahbo_s_ext(I+3); | |
472 | END GENERATE max_16_ahbs; |
|
479 | END GENERATE max_16_ahbs; | |
473 | END GENERATE all_ahbs; |
|
480 | END GENERATE all_ahbs; | |
474 | -- AHB_Master ------------------------------------------------------------- |
|
481 | -- AHB_Master ------------------------------------------------------------- | |
475 | ahbi_m_ext <= ahbmi; |
|
482 | ahbi_m_ext <= ahbmi; | |
476 | all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE |
|
483 | all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE | |
477 | max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE |
|
484 | max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE | |
478 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); |
|
485 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); | |
479 | END GENERATE max_16_ahbm; |
|
486 | END GENERATE max_16_ahbm; | |
480 | END GENERATE all_ahbm; |
|
487 | END GENERATE all_ahbm; | |
481 |
|
488 | |||
482 |
|
489 | |||
483 |
|
490 | |||
484 | END Behavioral; No newline at end of file |
|
491 | END Behavioral; |
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