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correction du leon3_soc suite au merge avec la version incluant le memory_controler IAP
pellion -
r495:0dee9fea5e79 (MINI-LFR) WFP_MS-0-1-41 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 196 --
197 197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 198
199 199 BEGIN -- beh
200 200
201 201 -----------------------------------------------------------------------------
202 202 -- CLK
203 203 -----------------------------------------------------------------------------
204 204
205 205 --PROCESS(clk_50)
206 206 --BEGIN
207 207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
208 208 -- clk_50_s <= NOT clk_50_s;
209 209 -- END IF;
210 210 --END PROCESS;
211 211
212 212 --PROCESS(clk_50_s)
213 213 --BEGIN
214 214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
215 215 -- clk_25 <= NOT clk_25;
216 216 -- END IF;
217 217 --END PROCESS;
218 218
219 219 --PROCESS(clk_49)
220 220 --BEGIN
221 221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
222 222 -- clk_24 <= NOT clk_24;
223 223 -- END IF;
224 224 --END PROCESS;
225 225
226 226 --PROCESS(clk_25)
227 227 --BEGIN
228 228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
229 229 -- rstn_25 <= reset;
230 230 -- END IF;
231 231 --END PROCESS;
232 232
233 233 PROCESS (clk_50, reset)
234 234 BEGIN -- PROCESS
235 235 IF reset = '0' THEN -- asynchronous reset (active low)
236 236 clk_50_s <= '0';
237 237 rstn_50 <= '0';
238 238 rstn_50_d1 <= '0';
239 239 rstn_50_d2 <= '0';
240 240 rstn_50_d3 <= '0';
241 241
242 242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
243 243 clk_50_s <= NOT clk_50_s;
244 244 rstn_50_d1 <= '1';
245 245 rstn_50_d2 <= rstn_50_d1;
246 246 rstn_50_d3 <= rstn_50_d2;
247 247 rstn_50 <= rstn_50_d3;
248 248 END IF;
249 249 END PROCESS;
250 250
251 251 PROCESS (clk_50_s, rstn_50)
252 252 BEGIN -- PROCESS
253 253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
254 254 clk_25 <= '0';
255 255 rstn_25 <= '0';
256 256 rstn_25_d1 <= '0';
257 257 rstn_25_d2 <= '0';
258 258 rstn_25_d3 <= '0';
259 259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
260 260 clk_25 <= NOT clk_25;
261 261 rstn_25_d1 <= '1';
262 262 rstn_25_d2 <= rstn_25_d1;
263 263 rstn_25_d3 <= rstn_25_d2;
264 264 rstn_25 <= rstn_25_d3;
265 265 END IF;
266 266 END PROCESS;
267 267
268 268 PROCESS (clk_49, reset)
269 269 BEGIN -- PROCESS
270 270 IF reset = '0' THEN -- asynchronous reset (active low)
271 271 clk_24 <= '0';
272 272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
273 273 clk_24 <= NOT clk_24;
274 274 END IF;
275 275 END PROCESS;
276 276
277 277 -----------------------------------------------------------------------------
278 278
279 279 PROCESS (clk_25, rstn_25)
280 280 BEGIN -- PROCESS
281 281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
282 282 LED0 <= '0';
283 283 LED1 <= '0';
284 284 LED2 <= '0';
285 285 --IO1 <= '0';
286 286 --IO2 <= '1';
287 287 --IO3 <= '0';
288 288 --IO4 <= '0';
289 289 --IO5 <= '0';
290 290 --IO6 <= '0';
291 291 --IO7 <= '0';
292 292 --IO8 <= '0';
293 293 --IO9 <= '0';
294 294 --IO10 <= '0';
295 295 --IO11 <= '0';
296 296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
297 297 LED0 <= '0';
298 298 LED1 <= '1';
299 299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
300 300 --IO1 <= '1';
301 301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
302 302 --IO3 <= ADC_SDO(0);
303 303 --IO4 <= ADC_SDO(1);
304 304 --IO5 <= ADC_SDO(2);
305 305 --IO6 <= ADC_SDO(3);
306 306 --IO7 <= ADC_SDO(4);
307 307 --IO8 <= ADC_SDO(5);
308 308 --IO9 <= ADC_SDO(6);
309 309 --IO10 <= ADC_SDO(7);
310 310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
311 311 END IF;
312 312 END PROCESS;
313 313
314 314 PROCESS (clk_24, rstn_25)
315 315 BEGIN -- PROCESS
316 316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
317 317 I00_s <= '0';
318 318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
319 319 I00_s <= NOT I00_s;
320 320 END IF;
321 321 END PROCESS;
322 322 -- IO0 <= I00_s;
323 323
324 324 --UARTs
325 325 nCTS1 <= '1';
326 326 nCTS2 <= '1';
327 327 nDCD2 <= '1';
328 328
329 329 --EXT CONNECTOR
330 330
331 331 --SPACE WIRE
332 332
333 333 leon3_soc_1 : leon3_soc
334 334 GENERIC MAP (
335 335 fabtech => apa3e,
336 336 memtech => apa3e,
337 337 padtech => inferred,
338 338 clktech => inferred,
339 339 disas => 0,
340 340 dbguart => 0,
341 341 pclow => 2,
342 342 clk_freq => 25000,
343 343 NB_CPU => 1,
344 344 ENABLE_FPU => 1,
345 345 FPU_NETLIST => 0,
346 346 ENABLE_DSU => 1,
347 347 ENABLE_AHB_UART => 1,
348 348 ENABLE_APB_UART => 1,
349 349 ENABLE_IRQMP => 1,
350 350 ENABLE_GPT => 1,
351 351 NB_AHB_MASTER => NB_AHB_MASTER,
352 352 NB_AHB_SLAVE => NB_AHB_SLAVE,
353 353 NB_APB_SLAVE => NB_APB_SLAVE,
354 354 ADDRESS_SIZE => 20,
355 355 USES_IAP_MEMCTRLR => 0)
356 356 PORT MAP (
357 357 clk => clk_25,
358 358 reset => rstn_25,
359 359 errorn => errorn,
360 360 ahbrxd => TXD1,
361 361 ahbtxd => RXD1,
362 362 urxd1 => TXD2,
363 363 utxd1 => RXD2,
364 364 address => SRAM_A,
365 365 data => SRAM_DQ,
366 366 nSRAM_BE0 => SRAM_nBE(0),
367 367 nSRAM_BE1 => SRAM_nBE(1),
368 368 nSRAM_BE2 => SRAM_nBE(2),
369 369 nSRAM_BE3 => SRAM_nBE(3),
370 370 nSRAM_WE => SRAM_nWE,
371 371 nSRAM_CE => SRAM_CE_s,
372 372 nSRAM_OE => SRAM_nOE,
373 373 nSRAM_READY => '0',
374 374 SRAM_MBE => OPEN,
375 375 apbi_ext => apbi_ext,
376 376 apbo_ext => apbo_ext,
377 377 ahbi_s_ext => ahbi_s_ext,
378 378 ahbo_s_ext => ahbo_s_ext,
379 379 ahbi_m_ext => ahbi_m_ext,
380 380 ahbo_m_ext => ahbo_m_ext);
381 381
382 382 SRAM_CE <= SRAM_CE_s(0);
383 383 -------------------------------------------------------------------------------
384 384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
385 385 -------------------------------------------------------------------------------
386 386 apb_lfr_time_management_1 : apb_lfr_time_management
387 387 GENERIC MAP (
388 388 pindex => 6,
389 389 paddr => 6,
390 390 pmask => 16#fff#,
391 391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
392 392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
393 393 PORT MAP (
394 394 clk25MHz => clk_25,
395 395 clk24_576MHz => clk_24, -- 49.152MHz/2
396 396 resetn => rstn_25,
397 397 grspw_tick => swno.tickout,
398 398 apbi => apbi_ext,
399 399 apbo => apbo_ext(6),
400 400 coarse_time => coarse_time,
401 401 fine_time => fine_time,
402 402 LFR_soft_rstn => LFR_soft_rstn
403 403 );
404 404
405 405 -----------------------------------------------------------------------
406 406 --- SpaceWire --------------------------------------------------------
407 407 -----------------------------------------------------------------------
408 408
409 409 SPW_EN <= '1';
410 410
411 411 spw_clk <= clk_50_s;
412 412 spw_rxtxclk <= spw_clk;
413 413 spw_rxclkn <= NOT spw_rxtxclk;
414 414
415 415 -- PADS for SPW1
416 416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
417 417 PORT MAP (SPW_NOM_DIN, dtmp(0));
418 418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
419 419 PORT MAP (SPW_NOM_SIN, stmp(0));
420 420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
421 421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
422 422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
423 423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
424 424 -- PADS FOR SPW2
425 425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
426 426 PORT MAP (SPW_RED_SIN, dtmp(1));
427 427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 428 PORT MAP (SPW_RED_DIN, stmp(1));
429 429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
430 430 PORT MAP (SPW_RED_DOUT, swno.d(1));
431 431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
432 432 PORT MAP (SPW_RED_SOUT, swno.s(1));
433 433
434 434 -- GRSPW PHY
435 435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
436 436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
437 437 spw_phy0 : grspw_phy
438 438 GENERIC MAP(
439 439 tech => apa3e,
440 440 rxclkbuftype => 1,
441 441 scantest => 0)
442 442 PORT MAP(
443 443 rxrst => swno.rxrst,
444 444 di => dtmp(j),
445 445 si => stmp(j),
446 446 rxclko => spw_rxclk(j),
447 447 do => swni.d(j),
448 448 ndo => swni.nd(j*5+4 DOWNTO j*5),
449 449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
450 450 END GENERATE spw_inputloop;
451 451
452 452 swni.rmapnodeaddr <= (OTHERS => '0');
453 453
454 454 -- SPW core
455 455 sw0 : grspwm GENERIC MAP(
456 456 tech => apa3e,
457 457 hindex => 1,
458 458 pindex => 5,
459 459 paddr => 5,
460 460 pirq => 11,
461 461 sysfreq => 25000, -- CPU_FREQ
462 462 rmap => 1,
463 463 rmapcrc => 1,
464 464 fifosize1 => 16,
465 465 fifosize2 => 16,
466 466 rxclkbuftype => 1,
467 467 rxunaligned => 0,
468 468 rmapbufs => 4,
469 469 ft => 0,
470 470 netlist => 0,
471 471 ports => 2,
472 472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
473 473 memtech => apa3e,
474 474 destkey => 2,
475 475 spwcore => 1
476 476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
477 477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
478 478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
479 479 )
480 480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
481 481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
482 482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
483 483 swni, swno);
484 484
485 485 swni.tickin <= '0';
486 486 swni.rmapen <= '1';
487 487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
488 488 swni.tickinraw <= '0';
489 489 swni.timein <= (OTHERS => '0');
490 490 swni.dcrstval <= (OTHERS => '0');
491 491 swni.timerrstval <= (OTHERS => '0');
492 492
493 493 -------------------------------------------------------------------------------
494 494 -- LFR ------------------------------------------------------------------------
495 495 -------------------------------------------------------------------------------
496 496
497 497
498 498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
499 499 --LFR_rstn <= rstn_25;
500 500
501 501 lpp_lfr_1 : lpp_lfr
502 502 GENERIC MAP (
503 503 Mem_use => use_RAM,
504 504 nb_data_by_buffer_size => 32,
505 505 nb_snapshot_param_size => 32,
506 506 delta_vector_size => 32,
507 507 delta_vector_size_f0_2 => 7, -- log2(96)
508 508 pindex => 15,
509 509 paddr => 15,
510 510 pmask => 16#fff#,
511 511 pirq_ms => 6,
512 512 pirq_wfp => 14,
513 513 hindex => 2,
514 top_lfr_version => X"000128") -- aa.bb.cc version
514 top_lfr_version => X"000129") -- aa.bb.cc version
515 515 PORT MAP (
516 516 clk => clk_25,
517 517 rstn => LFR_rstn,
518 518 sample_B => sample_s(2 DOWNTO 0),
519 519 sample_E => sample_s(7 DOWNTO 3),
520 520 sample_val => sample_val,
521 521 apbi => apbi_ext,
522 522 apbo => apbo_ext(15),
523 523 ahbi => ahbi_m_ext,
524 524 ahbo => ahbo_m_ext(2),
525 525 coarse_time => coarse_time,
526 526 fine_time => fine_time,
527 527 data_shaping_BW => bias_fail_sw_sig,
528 528 debug_vector => lfr_debug_vector,
529 529 debug_vector_ms => lfr_debug_vector_ms
530 530 );
531 531
532 532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
533 533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
534 534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
535 535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
536 536 IO0 <= rstn_25;
537 537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
538 538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
539 539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
540 540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
541 541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
542 542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
543 543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
544 544
545 545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
546 546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
547 547 END GENERATE all_sample;
548 548
549 549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
550 550 GENERIC MAP(
551 551 ChannelCount => 8,
552 552 SampleNbBits => 14,
553 553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
554 554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
555 555 PORT MAP (
556 556 -- CONV
557 557 cnv_clk => clk_24,
558 558 cnv_rstn => rstn_25,
559 559 cnv => ADC_nCS_sig,
560 560 -- DATA
561 561 clk => clk_25,
562 562 rstn => rstn_25,
563 563 sck => ADC_CLK_sig,
564 564 sdo => ADC_SDO_sig,
565 565 -- SAMPLE
566 566 sample => sample,
567 567 sample_val => sample_val);
568 568
569 569 --IO10 <= ADC_SDO_sig(5);
570 570 --IO9 <= ADC_SDO_sig(4);
571 571 --IO8 <= ADC_SDO_sig(3);
572 572
573 573 ADC_nCS <= ADC_nCS_sig;
574 574 ADC_CLK <= ADC_CLK_sig;
575 575 ADC_SDO_sig <= ADC_SDO;
576 576
577 577 ----------------------------------------------------------------------
578 578 --- GPIO -----------------------------------------------------------
579 579 ----------------------------------------------------------------------
580 580
581 581 grgpio0 : grgpio
582 582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
583 583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
584 584
585 585 gpioi.sig_en <= (OTHERS => '0');
586 586 gpioi.sig_in <= (OTHERS => '0');
587 587 gpioi.din <= (OTHERS => '0');
588 588 --pio_pad_0 : iopad
589 589 -- GENERIC MAP (tech => CFG_PADTECH)
590 590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
591 591 --pio_pad_1 : iopad
592 592 -- GENERIC MAP (tech => CFG_PADTECH)
593 593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
594 594 --pio_pad_2 : iopad
595 595 -- GENERIC MAP (tech => CFG_PADTECH)
596 596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
597 597 --pio_pad_3 : iopad
598 598 -- GENERIC MAP (tech => CFG_PADTECH)
599 599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
600 600 --pio_pad_4 : iopad
601 601 -- GENERIC MAP (tech => CFG_PADTECH)
602 602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
603 603 --pio_pad_5 : iopad
604 604 -- GENERIC MAP (tech => CFG_PADTECH)
605 605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
606 606 --pio_pad_6 : iopad
607 607 -- GENERIC MAP (tech => CFG_PADTECH)
608 608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
609 609 --pio_pad_7 : iopad
610 610 -- GENERIC MAP (tech => CFG_PADTECH)
611 611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
612 612
613 613 PROCESS (clk_25, rstn_25)
614 614 BEGIN -- PROCESS
615 615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
616 616 -- --IO0 <= '0';
617 617 -- IO1 <= '0';
618 618 -- IO2 <= '0';
619 619 -- IO3 <= '0';
620 620 -- IO4 <= '0';
621 621 -- IO5 <= '0';
622 622 -- IO6 <= '0';
623 623 -- IO7 <= '0';
624 624 IO8 <= '0';
625 625 IO9 <= '0';
626 626 IO10 <= '0';
627 627 IO11 <= '0';
628 628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
629 629 CASE gpioo.dout(2 DOWNTO 0) IS
630 630 WHEN "011" =>
631 631 -- --IO0 <= observation_reg(0 );
632 632 -- IO1 <= observation_reg(1 );
633 633 -- IO2 <= observation_reg(2 );
634 634 -- IO3 <= observation_reg(3 );
635 635 -- IO4 <= observation_reg(4 );
636 636 -- IO5 <= observation_reg(5 );
637 637 -- IO6 <= observation_reg(6 );
638 638 -- IO7 <= observation_reg(7 );
639 639 IO8 <= observation_reg(8);
640 640 IO9 <= observation_reg(9);
641 641 IO10 <= observation_reg(10);
642 642 IO11 <= observation_reg(11);
643 643 WHEN "001" =>
644 644 -- --IO0 <= observation_reg(0 + 12);
645 645 -- IO1 <= observation_reg(1 + 12);
646 646 -- IO2 <= observation_reg(2 + 12);
647 647 -- IO3 <= observation_reg(3 + 12);
648 648 -- IO4 <= observation_reg(4 + 12);
649 649 -- IO5 <= observation_reg(5 + 12);
650 650 -- IO6 <= observation_reg(6 + 12);
651 651 -- IO7 <= observation_reg(7 + 12);
652 652 IO8 <= observation_reg(8 + 12);
653 653 IO9 <= observation_reg(9 + 12);
654 654 IO10 <= observation_reg(10 + 12);
655 655 IO11 <= observation_reg(11 + 12);
656 656 WHEN "010" =>
657 657 -- --IO0 <= observation_reg(0 + 12 + 12);
658 658 -- IO1 <= observation_reg(1 + 12 + 12);
659 659 -- IO2 <= observation_reg(2 + 12 + 12);
660 660 -- IO3 <= observation_reg(3 + 12 + 12);
661 661 -- IO4 <= observation_reg(4 + 12 + 12);
662 662 -- IO5 <= observation_reg(5 + 12 + 12);
663 663 -- IO6 <= observation_reg(6 + 12 + 12);
664 664 -- IO7 <= observation_reg(7 + 12 + 12);
665 665 IO8 <= '0';
666 666 IO9 <= '0';
667 667 IO10 <= '0';
668 668 IO11 <= '0';
669 669 WHEN "000" =>
670 670 -- --IO0 <= observation_vector_0(0 );
671 671 -- IO1 <= observation_vector_0(1 );
672 672 -- IO2 <= observation_vector_0(2 );
673 673 -- IO3 <= observation_vector_0(3 );
674 674 -- IO4 <= observation_vector_0(4 );
675 675 -- IO5 <= observation_vector_0(5 );
676 676 -- IO6 <= observation_vector_0(6 );
677 677 -- IO7 <= observation_vector_0(7 );
678 678 IO8 <= observation_vector_0(8);
679 679 IO9 <= observation_vector_0(9);
680 680 IO10 <= observation_vector_0(10);
681 681 IO11 <= observation_vector_0(11);
682 682 WHEN "100" =>
683 683 -- --IO0 <= observation_vector_1(0 );
684 684 -- IO1 <= observation_vector_1(1 );
685 685 -- IO2 <= observation_vector_1(2 );
686 686 -- IO3 <= observation_vector_1(3 );
687 687 -- IO4 <= observation_vector_1(4 );
688 688 -- IO5 <= observation_vector_1(5 );
689 689 -- IO6 <= observation_vector_1(6 );
690 690 -- IO7 <= observation_vector_1(7 );
691 691 IO8 <= observation_vector_1(8);
692 692 IO9 <= observation_vector_1(9);
693 693 IO10 <= observation_vector_1(10);
694 694 IO11 <= observation_vector_1(11);
695 695 WHEN OTHERS => NULL;
696 696 END CASE;
697 697
698 698 END IF;
699 699 END PROCESS;
700 700 -----------------------------------------------------------------------------
701 701 --
702 702 -----------------------------------------------------------------------------
703 703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
704 704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
705 705 apbo_ext(I) <= apb_none;
706 706 END GENERATE apbo_ext_not_used;
707 707 END GENERATE all_apbo_ext;
708 708
709 709
710 710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
711 711 ahbo_s_ext(I) <= ahbs_none;
712 712 END GENERATE all_ahbo_ext;
713 713
714 714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
715 715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
716 716 ahbo_m_ext(I) <= ahbm_none;
717 717 END GENERATE ahbo_m_ext_not_used;
718 718 END GENERATE all_ahbo_m_ext;
719 719
720 720 END beh;
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@@ -1,484 +1,491
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_lfr_time_management.ALL;
43 43 USE lpp.lpp_leon3_soc_pkg.ALL;
44 44 LIBRARY iap;
45 45 USE iap.memctrl.all;
46 46
47 47
48 48 ENTITY leon3_soc IS
49 49 GENERIC (
50 50 fabtech : INTEGER := apa3e;
51 51 memtech : INTEGER := apa3e;
52 52 padtech : INTEGER := inferred;
53 53 clktech : INTEGER := inferred;
54 54 disas : INTEGER := 0; -- Enable disassembly to console
55 55 dbguart : INTEGER := 0; -- Print UART on console
56 56 pclow : INTEGER := 2;
57 57 --
58 58 clk_freq : INTEGER := 25000; --kHz
59 59 --
60 60 NB_CPU : INTEGER := 1;
61 61 ENABLE_FPU : INTEGER := 1;
62 62 FPU_NETLIST : INTEGER := 1;
63 63 ENABLE_DSU : INTEGER := 1;
64 64 ENABLE_AHB_UART : INTEGER := 1;
65 65 ENABLE_APB_UART : INTEGER := 1;
66 66 ENABLE_IRQMP : INTEGER := 1;
67 67 ENABLE_GPT : INTEGER := 1;
68 68 --
69 69 NB_AHB_MASTER : INTEGER := 0;
70 70 NB_AHB_SLAVE : INTEGER := 0;
71 71 NB_APB_SLAVE : INTEGER := 0;
72 72 --
73 73 ADDRESS_SIZE : INTEGER := 20;
74 74 USES_IAP_MEMCTRLR : INTEGER := 0
75 75
76 76 );
77 77 PORT (
78 78 clk : IN STD_ULOGIC;
79 79 reset : IN STD_ULOGIC;
80 80
81 81 errorn : OUT STD_ULOGIC;
82 82
83 83 -- UART AHB ---------------------------------------------------------------
84 84 ahbrxd : IN STD_ULOGIC; -- DSU rx data
85 85 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
86 86
87 87 -- UART APB ---------------------------------------------------------------
88 88 urxd1 : IN STD_ULOGIC; -- UART1 rx data
89 89 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
90 90
91 91 -- RAM --------------------------------------------------------------------
92 92 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
93 93 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 nSRAM_BE0 : OUT STD_LOGIC;
95 95 nSRAM_BE1 : OUT STD_LOGIC;
96 96 nSRAM_BE2 : OUT STD_LOGIC;
97 97 nSRAM_BE3 : OUT STD_LOGIC;
98 98 nSRAM_WE : OUT STD_LOGIC;
99 99 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
100 100 nSRAM_OE : OUT STD_LOGIC;
101 101 nSRAM_READY : IN STD_LOGIC;
102 102 SRAM_MBE : INOUT STD_LOGIC;
103 103 -- APB --------------------------------------------------------------------
104 104 apbi_ext : OUT apb_slv_in_type;
105 105 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
106 106 -- AHB_Slave --------------------------------------------------------------
107 107 ahbi_s_ext : OUT ahb_slv_in_type;
108 108 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
109 109 -- AHB_Master -------------------------------------------------------------
110 110 ahbi_m_ext : OUT AHB_Mst_In_Type;
111 111 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
112 112
113 113 );
114 114 END;
115 115
116 116 ARCHITECTURE Behavioral OF leon3_soc IS
117 117
118 118 -----------------------------------------------------------------------------
119 119 -- CONFIG -------------------------------------------------------------------
120 120 -----------------------------------------------------------------------------
121 121
122 122 -- Clock generator
123 123 constant CFG_CLKMUL : integer := (1);
124 124 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
125 125 constant CFG_OCLKDIV : integer := (1);
126 126 constant CFG_CLK_NOFB : integer := 0;
127 127 -- LEON3 processor core
128 128 constant CFG_LEON3 : integer := 1;
129 129 constant CFG_NCPU : integer := NB_CPU;
130 130 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
131 131 constant CFG_V8 : integer := 0;
132 132 constant CFG_MAC : integer := 0;
133 133 constant CFG_SVT : integer := 0;
134 134 constant CFG_RSTADDR : integer := 16#00000#;
135 135 constant CFG_LDDEL : integer := (1);
136 136 constant CFG_NWP : integer := (0);
137 137 constant CFG_PWD : integer := 1*2;
138 138 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
139 139 -- 1*(8 + 16 * 0) => grfpu-light
140 140 -- 1*(8 + 16 * 1) => netlist
141 141 -- 0*(8 + 16 * 0) => No FPU
142 142 -- 0*(8 + 16 * 1) => No FPU;
143 143 constant CFG_ICEN : integer := 1;
144 144 constant CFG_ISETS : integer := 1;
145 145 constant CFG_ISETSZ : integer := 4;
146 146 constant CFG_ILINE : integer := 4;
147 147 constant CFG_IREPL : integer := 0;
148 148 constant CFG_ILOCK : integer := 0;
149 149 constant CFG_ILRAMEN : integer := 0;
150 150 constant CFG_ILRAMADDR: integer := 16#8E#;
151 151 constant CFG_ILRAMSZ : integer := 1;
152 152 constant CFG_DCEN : integer := 1;
153 153 constant CFG_DSETS : integer := 1;
154 154 constant CFG_DSETSZ : integer := 4;
155 155 constant CFG_DLINE : integer := 4;
156 156 constant CFG_DREPL : integer := 0;
157 157 constant CFG_DLOCK : integer := 0;
158 158 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
159 159 constant CFG_DLRAMEN : integer := 0;
160 160 constant CFG_DLRAMADDR: integer := 16#8F#;
161 161 constant CFG_DLRAMSZ : integer := 1;
162 162 constant CFG_MMUEN : integer := 0;
163 163 constant CFG_ITLBNUM : integer := 2;
164 164 constant CFG_DTLBNUM : integer := 2;
165 165 constant CFG_TLB_TYPE : integer := 1 + 0*2;
166 166 constant CFG_TLB_REP : integer := 1;
167 167
168 168 constant CFG_DSU : integer := ENABLE_DSU;
169 169 constant CFG_ITBSZ : integer := 0;
170 170 constant CFG_ATBSZ : integer := 0;
171 171
172 172 -- AMBA settings
173 173 constant CFG_DEFMST : integer := (0);
174 174 constant CFG_RROBIN : integer := 1;
175 175 constant CFG_SPLIT : integer := 0;
176 176 constant CFG_AHBIO : integer := 16#FFF#;
177 177 constant CFG_APBADDR : integer := 16#800#;
178 178
179 179 -- DSU UART
180 180 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
181 181
182 182 -- LEON2 memory controller
183 183 constant CFG_MCTRL_SDEN : integer := 0;
184 184
185 185 -- UART 1
186 186 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
187 187 constant CFG_UART1_FIFO : integer := 1;
188 188
189 189 -- LEON3 interrupt controller
190 190 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
191 191
192 192 -- Modular timer
193 193 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
194 194 constant CFG_GPT_NTIM : integer := (2);
195 195 constant CFG_GPT_SW : integer := (8);
196 196 constant CFG_GPT_TW : integer := (32);
197 197 constant CFG_GPT_IRQ : integer := (8);
198 198 constant CFG_GPT_SEPIRQ : integer := 1;
199 199 constant CFG_GPT_WDOGEN : integer := 0;
200 200 constant CFG_GPT_WDOG : integer := 16#0#;
201 201 -----------------------------------------------------------------------------
202 202
203 203 -----------------------------------------------------------------------------
204 204 -- SIGNALs
205 205 -----------------------------------------------------------------------------
206 206 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
207 207 -- CLK & RST --
208 208 SIGNAL clk2x : STD_ULOGIC;
209 209 SIGNAL clkmn : STD_ULOGIC;
210 210 SIGNAL clkm : STD_ULOGIC;
211 211 SIGNAL rstn : STD_ULOGIC;
212 212 SIGNAL rstraw : STD_ULOGIC;
213 213 SIGNAL pciclk : STD_ULOGIC;
214 214 SIGNAL sdclkl : STD_ULOGIC;
215 215 SIGNAL cgi : clkgen_in_type;
216 216 SIGNAL cgo : clkgen_out_type;
217 217 --- AHB / APB
218 218 SIGNAL apbi : apb_slv_in_type;
219 219 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
220 220 SIGNAL ahbsi : ahb_slv_in_type;
221 221 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
222 222 SIGNAL ahbmi : ahb_mst_in_type;
223 223 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
224 224 --UART
225 225 SIGNAL ahbuarti : uart_in_type;
226 226 SIGNAL ahbuarto : uart_out_type;
227 227 SIGNAL apbuarti : uart_in_type;
228 228 SIGNAL apbuarto : uart_out_type;
229 229 --MEM CTRLR
230 230 SIGNAL memi : memory_in_type;
231 231 SIGNAL memo : memory_out_type;
232 232 SIGNAL wpo : wprot_out_type;
233 233 SIGNAL sdo : sdram_out_type;
234 234 SIGNAl mbe : std_logic; -- enable memory programming
235 235 SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal
236 236 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0);
237 SIGNAL nSRAM_OE_s : STD_LOGIC;
237 238 --IRQ
238 239 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
239 240 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
240 241 --Timer
241 242 SIGNAL gpti : gptimer_in_type;
242 243 SIGNAL gpto : gptimer_out_type;
243 244 --DSU
244 245 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
245 246 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
246 247 SIGNAL dsui : dsu_in_type;
247 248 SIGNAL dsuo : dsu_out_type;
248 249 -----------------------------------------------------------------------------
249 250
250 251
251 252 BEGIN
252 253
253 254
254 255 ----------------------------------------------------------------------
255 256 --- Reset and Clock generation -------------------------------------
256 257 ----------------------------------------------------------------------
257 258
258 259 cgi.pllctrl <= "00";
259 260 cgi.pllrst <= rstraw;
260 261
261 262 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
262 263
263 264 clkgen0 : clkgen -- clock generator
264 265 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
265 266 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
266 267 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
267 268
268 269 ----------------------------------------------------------------------
269 270 --- LEON3 processor / DSU / IRQ ------------------------------------
270 271 ----------------------------------------------------------------------
271 272
272 273 l3 : IF CFG_LEON3 = 1 GENERATE
273 274 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
274 275 u0 : leon3s -- LEON3 processor
275 276 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
276 277 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
277 278 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
278 279 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
279 280 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
280 281 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
281 282 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
282 283 irqi(i), irqo(i), dbgi(i), dbgo(i));
283 284 END GENERATE;
284 285 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
285 286
286 287 dsugen : IF CFG_DSU = 1 GENERATE
287 288 dsu0 : dsu3 -- LEON3 Debug Support Unit
288 289 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
289 290 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
290 291 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
291 292 dsui.enable <= '1';
292 293 dsui.break <= '0';
293 294 END GENERATE;
294 295 END GENERATE;
295 296
296 297 nodsu : IF CFG_DSU = 0 GENERATE
297 298 ahbso(2) <= ahbs_none;
298 299 dsuo.tstop <= '0';
299 300 dsuo.active <= '0';
300 301 END GENERATE;
301 302
302 303 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
303 304 irqctrl0 : irqmp -- interrupt controller
304 305 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
305 306 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
306 307 END GENERATE;
307 308 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
308 309 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
309 310 irqi(i).irl <= "0000";
310 311 END GENERATE;
311 312 apbo(2) <= apb_none;
312 313 END GENERATE;
313 314
314 315 ----------------------------------------------------------------------
315 316 --- Memory controllers ---------------------------------------------
316 317 ----------------------------------------------------------------------
317 318 ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE
318 319 memctrlr : mctrl GENERIC MAP (
319 320 hindex => 0,
320 321 pindex => 0,
321 322 paddr => 0,
322 323 srbanks => 1
323 324 )
324 325 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
325 326 memi.bexcn <= '1';
326 327 memi.brdyn <= '1';
328
329 nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0));
330 nSRAM_OE_s <= memo.ramoen(0);
327 331 END GENERATE;
328 332
329 333 IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE
330 334 memctrlr : srctrle_0ws
331 335 GENERIC MAP(
332 336 hindex => 0,
333 337 pindex => 0,
334 338 paddr => 0,
335 339 srbanks => 2,
336 340 banksz => 8, --512k * 32
337 341 rmw => 1,
338 342 --Aeroflex memory generics:
339 343 mprog => 1, -- program memory by default values after reset
340 344 mpsrate => 12, -- default scrub rate period
341 345 mpb2s => 4, -- default busy to scrub delay
342 346 mpapb => 1, -- instantiate apb register
343 347 mchipcnt => 2,
344 348 mpenall => 1 -- when 0 program only E1 chip, else program all dies
345 349 )
346 350 PORT MAP (
347 351 rst => rstn,
348 352 clk => clkm,
349 353 ahbsi => ahbsi,
350 354 ahbso => ahbso(0),
351 355 apbi => apbi,
352 356 apbo => apbo(0),
353 357 sri => memi,
354 358 sro => memo,
355 359 --Aeroflex memory signals:
356 360 ucerr => open, -- uncorrectable error signal
357 361 mbe => mbe, -- enable memory programming
358 362 mbe_drive => mbe_drive -- drive the MBE memory signal
359 363 );
360 364
361 365 memi.brdyn <= nSRAM_READY;
362 366
363 367 mbe_pad : iopad
364 368 GENERIC MAP(tech => padtech)
365 369 PORT MAP(pad => SRAM_MBE,
366 370 i => mbe,
367 371 en => mbe_drive,
368 372 o => memi.bexcn );
373
374 nSRAM_CE_s <= (memo.ramsn(1 downto 0));
375 nSRAM_OE_s <= memo.oen;
376
369 377 END GENERATE;
370 378
371 379
372 380 memi.writen <= '1';
373 381 memi.wrn <= "1111";
374 382 memi.bwidth <= "10";
375 383
376 384 bdr : FOR i IN 0 TO 3 GENERATE
377 385 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR)
378 386 PORT MAP (
379 387 data(31-i*8 DOWNTO 24-i*8),
380 388 memo.data(31-i*8 DOWNTO 24-i*8),
381 389 memo.bdrive(i),
382 390 memi.data(31-i*8 DOWNTO 24-i*8));
383 391 END GENERATE;
384 392
385 393 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
386 394 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
387 nSRAM_CE_s <= (memo.ramsn(1 downto 0));
388 395 rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
389 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.oen);
396 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
390 397 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
391 398 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
392 399 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
393 400 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
394 401 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
395 402
396 403
397 404
398 405 ----------------------------------------------------------------------
399 406 --- AHB CONTROLLER -------------------------------------------------
400 407 ----------------------------------------------------------------------
401 408 ahb0 : ahbctrl -- AHB arbiter/multiplexer
402 409 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
403 410 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
404 411 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
405 412 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
406 413
407 414 ----------------------------------------------------------------------
408 415 --- AHB UART -------------------------------------------------------
409 416 ----------------------------------------------------------------------
410 417 dcomgen : IF CFG_AHB_UART = 1 GENERATE
411 418 dcom0 : ahbuart
412 419 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
413 420 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
414 421 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
415 422 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
416 423 END GENERATE;
417 424 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
418 425
419 426 ----------------------------------------------------------------------
420 427 --- APB Bridge -----------------------------------------------------
421 428 ----------------------------------------------------------------------
422 429 apb0 : apbctrl -- AHB/APB bridge
423 430 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
424 431 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
425 432
426 433 ----------------------------------------------------------------------
427 434 --- GPT Timer ------------------------------------------------------
428 435 ----------------------------------------------------------------------
429 436 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
430 437 timer0 : gptimer -- timer unit
431 438 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
432 439 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
433 440 nbits => CFG_GPT_TW)
434 441 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
435 442 gpti.dhalt <= dsuo.tstop;
436 443 gpti.extclk <= '0';
437 444 END GENERATE;
438 445 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
439 446
440 447
441 448 ----------------------------------------------------------------------
442 449 --- APB UART -------------------------------------------------------
443 450 ----------------------------------------------------------------------
444 451 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
445 452 uart1 : apbuart -- UART 1
446 453 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
447 454 fifosize => CFG_UART1_FIFO)
448 455 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
449 456 apbuarti.rxd <= urxd1;
450 457 apbuarti.extclk <= '0';
451 458 utxd1 <= apbuarto.txd;
452 459 apbuarti.ctsn <= '0';
453 460 END GENERATE;
454 461 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
455 462
456 463 -------------------------------------------------------------------------------
457 464 -- AMBA BUS -------------------------------------------------------------------
458 465 -------------------------------------------------------------------------------
459 466
460 467 -- APB --------------------------------------------------------------------
461 468 apbi_ext <= apbi;
462 469 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
463 470 max_16_apb: IF I + 5 < 16 GENERATE
464 471 apbo(I+5)<= apbo_ext(I+5);
465 472 END GENERATE max_16_apb;
466 473 END GENERATE all_apb;
467 474 -- AHB_Slave --------------------------------------------------------------
468 475 ahbi_s_ext <= ahbsi;
469 476 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
470 477 max_16_ahbs: IF I + 3 < 16 GENERATE
471 478 ahbso(I+3) <= ahbo_s_ext(I+3);
472 479 END GENERATE max_16_ahbs;
473 480 END GENERATE all_ahbs;
474 481 -- AHB_Master -------------------------------------------------------------
475 482 ahbi_m_ext <= ahbmi;
476 483 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
477 484 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
478 485 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
479 486 END GENERATE max_16_ahbm;
480 487 END GENERATE all_ahbm;
481 488
482 489
483 490
484 END Behavioral; No newline at end of file
491 END Behavioral;
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