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TOP with Leon3 SoC only (no LPP module)
pellion -
r260:083bc4300827 JC
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1 TECHNOLOGY=PROASIC3
2 1 PACKAGE=\"\"
3 2 SPEED=Std
4 3 SYNFREQ=50
5 4
6 PART=A3PE3000L
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
7 11 DESIGNER_PACKAGE=FBGA
8 12 DESIGNER_PINS=324
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11 13
12 14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
13 16 MGCPART=$(PART)
14 MGCTECHNOLOGY=PROASIC3
15 17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
16 LIBERO_DIE=IT14X14M4LDP
17 18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
18 19
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@@ -1,261 +1,286
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL; -- PLE
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 USE work.config.ALL;
39 39 LIBRARY lpp;
40 40 USE lpp.lpp_memory.ALL;
41 41 USE lpp.lpp_ad_conv.ALL;
42 42 USE lpp.lpp_lfr_pkg.ALL;
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46
47 47 ENTITY MINI_LFR_top IS
48 48
49 49 PORT (
50 50 clk_50 : IN STD_LOGIC;
51 51 clk_49 : IN STD_LOGIC;
52 52 reset : IN STD_LOGIC;
53 53 --BPs
54 54 BP0 : IN STD_LOGIC;
55 55 BP1 : IN STD_LOGIC;
56 56 --LEDs
57 57 LED0 : OUT STD_LOGIC;
58 58 LED1 : OUT STD_LOGIC;
59 59 LED2 : OUT STD_LOGIC;
60 60 --UARTs
61 61 TXD1 : IN STD_LOGIC;
62 62 RXD1 : OUT STD_LOGIC;
63 63 nCTS1 : OUT STD_LOGIC;
64 64 nRTS1 : IN STD_LOGIC;
65 65
66 66 TXD2 : IN STD_LOGIC;
67 67 RXD2 : OUT STD_LOGIC;
68 68 nCTS2 : OUT STD_LOGIC;
69 69 nDTR2 : IN STD_LOGIC;
70 70 nRTS2 : IN STD_LOGIC;
71 71 nDCD2 : OUT STD_LOGIC;
72 72
73 73 --EXT CONNECTOR
74 74 IO0 : INOUT STD_LOGIC;
75 75 IO1 : INOUT STD_LOGIC;
76 76 IO2 : INOUT STD_LOGIC;
77 77 IO3 : INOUT STD_LOGIC;
78 78 IO4 : INOUT STD_LOGIC;
79 79 IO5 : INOUT STD_LOGIC;
80 80 IO6 : INOUT STD_LOGIC;
81 81 IO7 : INOUT STD_LOGIC;
82 82 IO8 : INOUT STD_LOGIC;
83 83 IO9 : INOUT STD_LOGIC;
84 84 IO10 : INOUT STD_LOGIC;
85 85 IO11 : INOUT STD_LOGIC;
86 86
87 87 --SPACE WIRE
88 88 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 89 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 90 SPW_NOM_SIN : IN STD_LOGIC;
91 91 SPW_NOM_DOUT : OUT STD_LOGIC;
92 92 SPW_NOM_SOUT : OUT STD_LOGIC;
93 93 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 94 SPW_RED_SIN : IN STD_LOGIC;
95 95 SPW_RED_DOUT : OUT STD_LOGIC;
96 96 SPW_RED_SOUT : OUT STD_LOGIC;
97 97 -- MINI LFR ADC INPUTS
98 98 ADC_nCS : OUT STD_LOGIC;
99 99 ADC_CLK : OUT STD_LOGIC;
100 100 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 101
102 102 -- SRAM
103 103 SRAM_nWE : OUT STD_LOGIC;
104 104 SRAM_CE : OUT STD_LOGIC;
105 105 SRAM_nOE : OUT STD_LOGIC;
106 106 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 107 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 108 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 109 );
110 110
111 111 END MINI_LFR_top;
112 112
113 113
114 114 ARCHITECTURE beh OF MINI_LFR_top IS
115 115
116 116 COMPONENT leon3_soc
117 117 GENERIC (
118 118 fabtech : INTEGER;
119 119 memtech : INTEGER;
120 120 padtech : INTEGER;
121 121 clktech : INTEGER;
122 122 disas : INTEGER;
123 123 dbguart : INTEGER;
124 124 pclow : INTEGER);
125 125 PORT (
126 126 clk100MHz : IN STD_ULOGIC;
127 clk49_152MHz : IN STD_ULOGIC;
128 127 reset : IN STD_ULOGIC;
129 128 errorn : OUT STD_ULOGIC;
130 129 ahbrxd : IN STD_ULOGIC;
131 130 ahbtxd : OUT STD_ULOGIC;
132 131 urxd1 : IN STD_ULOGIC;
133 132 utxd1 : OUT STD_ULOGIC;
134 133 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
135 134 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 135 nSRAM_BE0 : OUT STD_LOGIC;
137 136 nSRAM_BE1 : OUT STD_LOGIC;
138 137 nSRAM_BE2 : OUT STD_LOGIC;
139 138 nSRAM_BE3 : OUT STD_LOGIC;
140 139 nSRAM_WE : OUT STD_LOGIC;
141 140 nSRAM_CE : OUT STD_LOGIC;
142 141 nSRAM_OE : OUT STD_LOGIC;
143 142 spw1_din : IN STD_LOGIC;
144 143 spw1_sin : IN STD_LOGIC;
145 144 spw1_dout : OUT STD_LOGIC;
146 145 spw1_sout : OUT STD_LOGIC;
147 146 spw2_din : IN STD_LOGIC;
148 147 spw2_sin : IN STD_LOGIC;
149 148 spw2_dout : OUT STD_LOGIC;
150 149 spw2_sout : OUT STD_LOGIC;
151 apbi_wfp : OUT apb_slv_in_type;
150 apbi_ext : OUT apb_slv_in_type;
152 151 apbo_wfp : IN apb_slv_out_type;
153 ahbi_wfp : OUT AHB_Mst_In_Type;
154 ahbo_wfp : IN AHB_Mst_Out_Type;
155 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
152 apbo_ltm : IN apb_slv_out_type;
153 ahbi_ext : OUT AHB_Mst_In_Type;
154 ahbo_wfp : IN AHB_Mst_Out_Type);
157 155 END COMPONENT;
156
157 -----------------------------------------------------------------------------
158 SIGNAL apbi : apb_slv_in_type;
159 SIGNAL apbo_wfp : apb_slv_out_type;
160 SIGNAL apbo_ltm : apb_slv_out_type;
161 SIGNAL ahbi : AHB_Mst_In_Type;
162 SIGNAL ahbo_wfp : AHB_Mst_Out_Type;
163 --
164 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
166 --
167 SIGNAL errorn : STD_LOGIC;
168 -- UART AHB ---------------------------------------------------------------
169 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
170 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
171
172 -- UART APB ---------------------------------------------------------------
173 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
174 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
175 --
176 SIGNAL I00_s : STD_LOGIC;
158 177
159 178 BEGIN -- beh
160 179
161 180 PROCESS (clk_50, reset)
162 181 BEGIN -- PROCESS
163 182 IF reset = '0' THEN -- asynchronous reset (active low)
164 183 LED0 <= '0';
165 184 LED1 <= '0';
166 185 LED2 <= '0';
186 IO1 <= '0';
187 IO2 <= '1';
188 IO3 <= '0';
189 IO4 <= '0';
190 IO5 <= '0';
191 IO6 <= '0';
192 IO7 <= '0';
193 IO8 <= '0';
194 IO9 <= '0';
195 IO10 <= '0';
196 IO11 <= '0';
167 197 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
168 198 LED0 <= '0';
169 199 LED1 <= '1';
170 200 LED2 <= BP0;
201 IO1 <= '1';
202 IO2 <= '0';
203 IO3 <= ADC_SDO(0);
204 IO4 <= ADC_SDO(1);
205 IO5 <= ADC_SDO(2);
206 IO6 <= ADC_SDO(3);
207 IO7 <= ADC_SDO(4);
208 IO8 <= ADC_SDO(5);
209 IO9 <= ADC_SDO(6);
210 IO10 <= ADC_SDO(7);
211 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
171 212 END IF;
172 213 END PROCESS;
173 214
215 PROCESS (clk_49, reset)
216 BEGIN -- PROCESS
217 IF reset = '0' THEN -- asynchronous reset (active low)
218 I00_s <= '0';
219 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
220 I00_s <= NOT I00_s;
221 END IF;
222 END PROCESS;
223 IO0 <= I00_s;
224
174 225 --UARTs
175 RXD1 <= '0';
176 nCTS1 <= '0';
177 RXD2 <= '0';
226 nCTS1 <= '0';
178 227 nCTS2 <= '0';
179 228 nDCD2 <= '0';
180 229
181 230 --EXT CONNECTOR
182 IO0 <= clk_49;
183 IO1 <= clk_50;
184
185 IO2 <= SPW_NOM_DIN OR
186 SPW_NOM_SIN OR
187 SPW_RED_DIN OR
188 SPW_RED_SIN;
189
190 IO3 <= ADC_SDO(0);
191 IO4 <= ADC_SDO(1);
192 IO5 <= ADC_SDO(2);
193 IO6 <= ADC_SDO(3);
194 IO7 <= ADC_SDO(4);
195 IO8 <= ADC_SDO(5);
196 IO9 <= ADC_SDO(6);
197 IO10 <= ADC_SDO(7);
198 IO11 <= BP1 OR TXD1 OR TXD2 OR nDTR2 OR nRTS2 OR nRTS1;
199 231
200 232 --SPACE WIRE
201 233 SPW_EN <= '0'; -- 0 => off
202 SPW_NOM_DOUT <= '0';
203 SPW_NOM_SOUT <= '0';
204 SPW_RED_DOUT <= '0';
205 SPW_RED_SOUT <= '0';
234
206 235 ADC_nCS <= '0';
207 236 ADC_CLK <= '0';
208 237
209 -- SRAM
210 SRAM_nWE <= '1';
211 SRAM_CE <= '0';
212 SRAM_nOE <= '1';
213 SRAM_nBE <= (OTHERS => '1');
214 SRAM_A <= (OTHERS => '0');
215 SRAM_DQ <= (OTHERS => '0');
216
217
218 238 leon3mp_1: leon3_soc
219 239 GENERIC MAP (
220 fabtech => fabtech,
221 memtech => memtech,
222 padtech => padtech,
223 clktech => clktech,
224 disas => disas,
225 dbguart => dbguart,
226 pclow => pclow)
240 fabtech => CFG_FABTECH,
241 memtech => CFG_MEMTECH,
242 padtech => CFG_PADTECH,
243 clktech => CFG_CLKTECH,
244 disas => CFG_DISAS,
245 dbguart => CFG_DUART,
246 pclow => CFG_PCLOW)
227 247 PORT MAP (
228 clk100MHz => clk100MHz,
229 clk49_152MHz => clk49_152MHz,
230 reset => reset,
231 errorn => errorn,
232 ahbrxd => ahbrxd,
233 ahbtxd => ahbtxd,
234 urxd1 => urxd1,
235 utxd1 => utxd1,
236 address => address,
237 data => data,
238 nSRAM_BE0 => nSRAM_BE0,
239 nSRAM_BE1 => nSRAM_BE1,
240 nSRAM_BE2 => nSRAM_BE2,
241 nSRAM_BE3 => nSRAM_BE3,
242 nSRAM_WE => nSRAM_WE,
243 nSRAM_CE => nSRAM_CE,
244 nSRAM_OE => nSRAM_OE,
245 spw1_din => spw1_din,
246 spw1_sin => spw1_sin,
247 spw1_dout => spw1_dout,
248 spw1_sout => spw1_sout,
249 spw2_din => spw2_din,
250 spw2_sin => spw2_sin,
251 spw2_dout => spw2_dout,
252 spw2_sout => spw2_sout,
253 apbi_wfp => apbi_wfp,
254 apbo_wfp => apbo_wfp,
255 ahbi_wfp => ahbi_wfp,
256 ahbo_wfp => ahbo_wfp,
257 coarse_time => coarse_time,
258 fine_time => fine_time);
248 clk100MHz => clk_50, --
249 reset => reset, --
250 errorn => errorn, --
251
252 ahbrxd => TXD1, --
253 ahbtxd => RXD1, --
254 urxd1 => TXD2, --
255 utxd1 => RXD2, --
256 --RAM
257 address => SRAM_A, --
258 data => SRAM_DQ, --
259 nSRAM_BE0 => SRAM_nBE(0), --
260 nSRAM_BE1 => SRAM_nBE(1), --
261 nSRAM_BE2 => SRAM_nBE(2), --
262 nSRAM_BE3 => SRAM_nBE(3), --
263 nSRAM_WE => SRAM_nWE, --
264 nSRAM_CE => SRAM_CE, --
265 nSRAM_OE => SRAM_nOE, --
266 --SPW
267 spw1_din => SPW_NOM_DIN, --
268 spw1_sin => SPW_NOM_SIN, --
269 spw1_dout => SPW_NOM_DOUT, --
270 spw1_sout => SPW_NOM_SOUT, --
271 spw2_din => SPW_RED_DIN, --
272 spw2_sin => SPW_RED_SIN, --
273 spw2_dout => SPW_RED_DOUT, --
274 spw2_sout => SPW_RED_SOUT, --
275
276 apbi_ext => apbi, --
277 apbo_wfp => apbo_wfp, --
278 apbo_ltm => apbo_ltm, -- lfr time management
279 ahbi_ext => ahbi, --
280 ahbo_wfp => ahbo_wfp); --
259 281
282 apbo_wfp <= apb_none;
283 apbo_ltm <= apb_none;
284 ahbo_wfp <= ahbm_none;
260 285
261 END beh;
286 END beh; No newline at end of file
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1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=MINI_LFR_top
5 5 BOARD=MINI-LFR
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 10 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd \
14 config.vhd \
13 VHDLSYNFILES= config.vhd \
14 MINI_LFR_top.vhd \
15 15 leon3_soc.vhd
16 16
17 17 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
18 18 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
19 19 CLEAN=soft-clean
20 20
21 21 TECHLIBS = proasic3e
22 22
23 23 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 24 tmtc openchip hynix ihp gleichmann micron usbhc
25 25
26 26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 28 ./amba_lcd_16x2_ctrlr \
29 29 ./general_purpose/lpp_AMR \
30 30 ./general_purpose/lpp_balise \
31 31 ./general_purpose/lpp_delay \
32 32 ./dsp/lpp_fft \
33 33 ./lpp_bootloader \
34 34 ./lpp_cna \
35 35 ./lpp_demux \
36 36 ./lpp_matrix \
37 37 ./lpp_uart \
38 38 ./lpp_usb \
39 39 ./lpp_Header \
40 40
41 FILESKIP = i2cmst.vhd \
41 FILESKIP =lpp_lfr_ms.vhd \
42 i2cmst.vhd \
42 43 APB_MULTI_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd
44 APB_SIMPLE_DIODE.vhd \
45 Top_MatrixSpec.vhd \
46 APB_FFT.vhd
44 47
45 48 include $(GRLIB)/bin/Makefile
46 49 include $(GRLIB)/software/leon3/Makefile
47 50
48 51 ################## project specific targets ##########################
49 52
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@@ -1,473 +1,452
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 USE work.config.ALL;
37 37 LIBRARY lpp;
38 38 USE lpp.lpp_memory.ALL;
39 39 USE lpp.lpp_ad_conv.ALL;
40 40 USE lpp.lpp_lfr_pkg.ALL;
41 41 USE lpp.iir_filter.ALL;
42 42 USE lpp.general_purpose.ALL;
43 43 USE lpp.lpp_lfr_time_management.ALL;
44 44
45 45 ENTITY leon3_soc IS
46 46 GENERIC (
47 47 fabtech : INTEGER := CFG_FABTECH;
48 48 memtech : INTEGER := CFG_MEMTECH;
49 49 padtech : INTEGER := CFG_PADTECH;
50 50 clktech : INTEGER := CFG_CLKTECH;
51 51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 53 pclow : INTEGER := CFG_PCLOW
54 54 );
55 55 PORT (
56 56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 57 reset : IN STD_ULOGIC;
59 58
60 59 errorn : OUT STD_ULOGIC;
61 60
62 61 -- UART AHB ---------------------------------------------------------------
63 62 ahbrxd : IN STD_ULOGIC; -- DSU rx data
64 63 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
65 64
66 65 -- UART APB ---------------------------------------------------------------
67 66 urxd1 : IN STD_ULOGIC; -- UART1 rx data
68 67 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
69 68
70 69 -- RAM --------------------------------------------------------------------
71 70 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
72 71 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 72 nSRAM_BE0 : OUT STD_LOGIC;
74 73 nSRAM_BE1 : OUT STD_LOGIC;
75 74 nSRAM_BE2 : OUT STD_LOGIC;
76 75 nSRAM_BE3 : OUT STD_LOGIC;
77 76 nSRAM_WE : OUT STD_LOGIC;
78 77 nSRAM_CE : OUT STD_LOGIC;
79 78 nSRAM_OE : OUT STD_LOGIC;
80 79
81 80 -- SPW --------------------------------------------------------------------
82 81 spw1_din : IN STD_LOGIC; -- PLE
83 82 spw1_sin : IN STD_LOGIC; -- PLE
84 83 spw1_dout : OUT STD_LOGIC; -- PLE
85 84 spw1_sout : OUT STD_LOGIC; -- PLE
86 85
87 86 spw2_din : IN STD_LOGIC; -- JCPE --TODO
88 87 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
89 88 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
90 89 spw2_sout : OUT STD_LOGIC;
91 90
92 91 -- WAVEFORM PICKER --------------------------------------------------------
93 apbi_wfp : OUT apb_slv_in_type;
92 apbi_ext : OUT apb_slv_in_type;
94 93 apbo_wfp : IN apb_slv_out_type;
95 ahbi_wfp : OUT AHB_Mst_In_Type;
96 ahbo_wfp : IN AHB_Mst_Out_Type;
97 -- TIME -------------------------------------------------------------------
98 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
94 apbo_ltm : IN apb_slv_out_type;
95 ahbi_ext : OUT AHB_Mst_In_Type;
96 ahbo_wfp : IN AHB_Mst_Out_Type
100 97
101 98 );
102 99 END;
103 100
104 101 ARCHITECTURE Behavioral OF leon3_soc IS
105 102
106 103 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
107 104 -- CFG_GRETH+CFG_AHB_JTAG;
108 105 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
109 106 CFG_AHB_UART
110 107 +2;
111 108 -- 1 is for the SpaceWire module grspw, which is a master
112 109 -- 1 is for the LFR
113 110
114 111 CONSTANT maxahbm : INTEGER := maxahbmsp;
115 112
116 113 --Clk & Rst gοΏ½nοΏ½
117 114 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 115 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 116 SIGNAL resetnl : STD_ULOGIC;
120 117 SIGNAL clk2x : STD_ULOGIC;
121 118 SIGNAL lclk2x : STD_ULOGIC;
122 119 SIGNAL lclk25MHz : STD_ULOGIC;
123 120 SIGNAL lclk50MHz : STD_ULOGIC;
124 121 SIGNAL lclk100MHz : STD_ULOGIC;
125 122 SIGNAL clkm : STD_ULOGIC;
126 123 SIGNAL rstn : STD_ULOGIC;
127 124 SIGNAL rstraw : STD_ULOGIC;
128 125 SIGNAL pciclk : STD_ULOGIC;
129 126 SIGNAL sdclkl : STD_ULOGIC;
130 127 SIGNAL cgi : clkgen_in_type;
131 128 SIGNAL cgo : clkgen_out_type;
132 129 --- AHB / APB
133 130 SIGNAL apbi : apb_slv_in_type;
134 131 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
135 132 SIGNAL ahbsi : ahb_slv_in_type;
136 133 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
137 134 SIGNAL ahbmi : ahb_mst_in_type;
138 135 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
139 136 --UART
140 137 SIGNAL ahbuarti : uart_in_type;
141 138 SIGNAL ahbuarto : uart_out_type;
142 139 SIGNAL apbuarti : uart_in_type;
143 140 SIGNAL apbuarto : uart_out_type;
144 141 --MEM CTRLR
145 142 SIGNAL memi : memory_in_type;
146 143 SIGNAL memo : memory_out_type;
147 144 SIGNAL wpo : wprot_out_type;
148 145 SIGNAL sdo : sdram_out_type;
149 146 SIGNAL ramcs : STD_ULOGIC;
150 147 --IRQ
151 148 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
152 149 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
153 150 --Timer
154 151 SIGNAL gpti : gptimer_in_type;
155 152 SIGNAL gpto : gptimer_out_type;
156 153 --GPIO
157 154 SIGNAL gpioi : gpio_in_type;
158 155 SIGNAL gpioo : gpio_out_type;
159 156 --DSU
160 157 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
161 158 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
162 159 SIGNAL dsui : dsu_in_type;
163 160 SIGNAL dsuo : dsu_out_type;
164 161
165 162 ---------------------------------------------------------------------
166 163 --- AJOUT TEST ------------------------Signaux----------------------
167 164 ---------------------------------------------------------------------
168 165
169 166 ---------------------------------------------------------------------
170 167 CONSTANT IOAEN : INTEGER := CFG_CAN;
171 168 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
172 169
173 170 -- Spacewire signals
174 171 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
175 172 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
176 173 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
177 174 SIGNAL spw_rxtxclk : STD_ULOGIC;
178 175 SIGNAL spw_rxclkn : STD_ULOGIC;
179 176 SIGNAL spw_clk : STD_LOGIC;
180 177 SIGNAL swni : grspw_in_type; -- PLE
181 178 SIGNAL swno : grspw_out_type; -- PLE
182 179 SIGNAL clkmn : STD_ULOGIC; -- PLE
183 180 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
184 181 -----------------------------------------------------------------------------
185 182
186 183 BEGIN
187 184
188 185
189 186 ----------------------------------------------------------------------
190 187 --- Reset and Clock generation -------------------------------------
191 188 ----------------------------------------------------------------------
192 189
193 190 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
194 191 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
195 192
196 193 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
197 194
198 195
199 196 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
200 197
201 198 clkgen0 : clkgen -- clock generator
202 199 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
203 200 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
204 201 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
205 202
206 203 PROCESS(lclk100MHz)
207 204 BEGIN
208 205 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
209 206 lclk50MHz <= NOT lclk50MHz;
210 207 END IF;
211 208 END PROCESS;
212 209
213 210 PROCESS(lclk50MHz)
214 211 BEGIN
215 212 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
216 213 lclk25MHz <= NOT lclk25MHz;
217 214 END IF;
218 215 END PROCESS;
219 216
220 217 lclk2x <= lclk50MHz;
221 218 spw_clk <= lclk50MHz;
222 219
223 220 ----------------------------------------------------------------------
224 221 --- LEON3 processor / DSU / IRQ ------------------------------------
225 222 ----------------------------------------------------------------------
226 223
227 224 l3 : IF CFG_LEON3 = 1 GENERATE
228 225 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
229 226 u0 : leon3s -- LEON3 processor
230 227 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
231 228 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
232 229 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
233 230 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
234 231 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
235 232 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
236 233 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
237 234 irqi(i), irqo(i), dbgi(i), dbgo(i));
238 235 END GENERATE;
239 236 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
240 237
241 238 dsugen : IF CFG_DSU = 1 GENERATE
242 239 dsu0 : dsu3 -- LEON3 Debug Support Unit
243 240 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
244 241 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
245 242 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
246 243 dsui.enable <= '1';
247 244 dsui.break <= '0';
248 245 END GENERATE;
249 246 END GENERATE;
250 247
251 248 nodsu : IF CFG_DSU = 0 GENERATE
252 249 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
253 250 END GENERATE;
254 251
255 252 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
256 253 irqctrl0 : irqmp -- interrupt controller
257 254 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
258 255 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
259 256 END GENERATE;
260 257 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
261 258 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
262 259 irqi(i).irl <= "0000";
263 260 END GENERATE;
264 261 apbo(2) <= apb_none;
265 262 END GENERATE;
266 263
267 264 ----------------------------------------------------------------------
268 265 --- Memory controllers ---------------------------------------------
269 266 ----------------------------------------------------------------------
270 267 memctrlr : mctrl GENERIC MAP (
271 268 hindex => 0,
272 269 pindex => 0,
273 270 paddr => 0,
274 271 srbanks => 1
275 272 )
276 273 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
277 274
278 275 memi.brdyn <= '1';
279 276 memi.bexcn <= '1';
280 277 memi.writen <= '1';
281 278 memi.wrn <= "1111";
282 279 memi.bwidth <= "10";
283 280
284 281 bdr : FOR i IN 0 TO 3 GENERATE
285 282 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
286 283 PORT MAP (
287 284 data(31-i*8 DOWNTO 24-i*8),
288 285 memo.data(31-i*8 DOWNTO 24-i*8),
289 286 memo.bdrive(i),
290 287 memi.data(31-i*8 DOWNTO 24-i*8));
291 288 END GENERATE;
292 289
293 290 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
294 291 PORT MAP (address, memo.address(21 DOWNTO 2));
295 292
296 293 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
297 294 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
298 295 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
299 296 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
300 297 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
301 298 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
302 299 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
303 300
304 301 ----------------------------------------------------------------------
305 302 --- AHB CONTROLLER -------------------------------------------------
306 303 ----------------------------------------------------------------------
307 304 ahb0 : ahbctrl -- AHB arbiter/multiplexer
308 305 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
309 306 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
310 307 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
311 308 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
312 309
313 310 ----------------------------------------------------------------------
314 311 --- AHB UART -------------------------------------------------------
315 312 ----------------------------------------------------------------------
316 313 dcomgen : IF CFG_AHB_UART = 1 GENERATE
317 314 dcom0 : ahbuart
318 315 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
319 316 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
320 317 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
321 318 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
322 319 END GENERATE;
323 320 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
324 321
325 322 ----------------------------------------------------------------------
326 323 --- APB Bridge -----------------------------------------------------
327 324 ----------------------------------------------------------------------
328 325 apb0 : apbctrl -- AHB/APB bridge
329 326 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
330 327 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
331 328
332 329 ----------------------------------------------------------------------
333 330 --- GPT Timer ------------------------------------------------------
334 331 ----------------------------------------------------------------------
335 332 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
336 333 timer0 : gptimer -- timer unit
337 334 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
338 335 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
339 336 nbits => CFG_GPT_TW)
340 337 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
341 338 gpti.dhalt <= dsuo.tstop;
342 339 gpti.extclk <= '0';
343 340 END GENERATE;
344 341 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
345 342
346 343
347 344 ----------------------------------------------------------------------
348 345 --- APB UART -------------------------------------------------------
349 346 ----------------------------------------------------------------------
350 347 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
351 348 uart1 : apbuart -- UART 1
352 349 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
353 350 fifosize => CFG_UART1_FIFO)
354 351 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
355 352 apbuarti.rxd <= urxd1;
356 353 apbuarti.extclk <= '0';
357 354 utxd1 <= apbuarto.txd;
358 355 apbuarti.ctsn <= '0';
359 356 END GENERATE;
360 357 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
361
362 -------------------------------------------------------------------------------
363 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
364 -------------------------------------------------------------------------------
365 apb_lfr_time_management_1: apb_lfr_time_management
366 GENERIC MAP (
367 pindex => 6,
368 paddr => 6,
369 pmask => 16#fff#,
370 pirq => 12)
371 PORT MAP (
372 clk25MHz => clkm,
373 clk49_152MHz => clk49_152MHz,
374 resetn => rstn,
375 grspw_tick => swno.tickout,
376 apbi => apbi,
377 apbo => apbo(6),
378 coarse_time => coarse_time,
379 fine_time => fine_time);
380
358
381 359 -----------------------------------------------------------------------
382 360 --- SpaceWire --------------------------------------------------------
383 361 -----------------------------------------------------------------------
384 362
385 363 spw_rxtxclk <= spw_clk;
386 364 spw_rxclkn <= NOT spw_rxtxclk;
387 365
388 366 -- PADS for SPW1
389 367 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
390 368 PORT MAP (spw1_din, dtmp(0));
391 369 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
392 370 PORT MAP (spw1_sin, stmp(0));
393 371 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
394 372 PORT MAP (spw1_dout, swno.d(0));
395 373 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
396 374 PORT MAP (spw1_sout, swno.s(0));
397 375 -- PADS FOR SPW2
398 376 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
399 377 PORT MAP (spw2_din, dtmp(1));
400 378 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
401 379 PORT MAP (spw2_sin, stmp(1));
402 380 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
403 381 PORT MAP (spw2_dout, swno.d(1));
404 382 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
405 383 PORT MAP (spw2_sout, swno.s(1));
406 384
407 385 -- GRSPW PHY
408 386 --spw1_input: if CFG_SPW_GRSPW = 1 generate
409 387 spw_inputloop : FOR j IN 0 TO 1 GENERATE
410 388 spw_phy0 : grspw_phy
411 389 GENERIC MAP(
412 390 tech => fabtech,
413 391 rxclkbuftype => 1,
414 392 scantest => 0)
415 393 PORT MAP(
416 394 rxrst => swno.rxrst,
417 395 di => dtmp(j),
418 396 si => stmp(j),
419 397 rxclko => spw_rxclk(j),
420 398 do => swni.d(j),
421 399 ndo => swni.nd(j*5+4 DOWNTO j*5),
422 400 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
423 401 END GENERATE spw_inputloop;
424 402
425 403 -- SPW core
426 404 sw0 : grspwm
427 405 GENERIC MAP(
428 406 tech => apa3e,
429 407 hindex => 1,
430 408 pindex => 5,
431 409 paddr => 5,
432 410 pirq => 11,
433 411 sysfreq => 25000, -- CPU_FREQ
434 412 rmap => 1,
435 413 rmapcrc => 1,
436 414 fifosize1 => 16,
437 415 fifosize2 => 16,
438 416 rxclkbuftype => 1,
439 417 rxunaligned => 0,
440 418 rmapbufs => 4,
441 419 ft => 0,
442 420 netlist => 0,
443 421 ports => 2,
444 422 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
445 423 memtech => apa3e,
446 424 destkey => 2,
447 425 spwcore => 1
448 426 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
449 427 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
450 428 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
451 429 )
452 430 PORT MAP(rstn, clkm, spw_rxclk(0),
453 431 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
454 432 ahbmi, ahbmo(1), apbi, apbo(5),
455 433 swni, swno);
456 434
457 435 swni.tickin <= '0';
458 436 swni.rmapen <= '1';
459 437 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
460 438 swni.tickinraw <= '0';
461 439 swni.timein <= (OTHERS => '0');
462 440 swni.dcrstval <= (OTHERS => '0');
463 441 swni.timerrstval <= (OTHERS => '0');
464 442
465 443 -------------------------------------------------------------------------------
466 444 -- LFR
467 445 -------------------------------------------------------------------------------
468 apbi_wfp <= apbi;
446 apbi_ext <= apbi;
469 447 apbo(15) <= apbo_wfp;
470 ahbi_wfp <= ahbmi;
448 apbo(6) <= apbo_ltm;
449 ahbi_ext <= ahbmi;
471 450 ahbmo(2) <= ahbo_wfp;
472 451
473 452 END Behavioral;
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