@@ -1,100 +1,121 | |||||
1 | -- FFTamont.vhd |
|
1 | -- FFTamont.vhd | |
2 | library IEEE; |
|
2 | library IEEE; | |
3 | use IEEE.std_logic_1164.all; |
|
3 | use IEEE.std_logic_1164.all; | |
4 | use IEEE.numeric_std.all; |
|
4 | use IEEE.numeric_std.all; | |
5 |
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5 | |||
6 | entity FFTamont is |
|
6 | entity FFTamont is | |
7 | generic( |
|
7 | generic( | |
8 | Data_sz : integer range 1 to 32 := 16; |
|
8 | Data_sz : integer range 1 to 32 := 16; | |
9 | NbData : integer range 1 to 512 := 256 |
|
9 | NbData : integer range 1 to 512 := 256 | |
10 | ); |
|
10 | ); | |
11 | port( |
|
11 | port( | |
12 | clk : in std_logic; |
|
12 | clk : in std_logic; | |
13 | rstn : in std_logic; |
|
13 | rstn : in std_logic; | |
14 | Load : in std_logic; |
|
14 | Load : in std_logic; | |
15 | Empty : in std_logic; |
|
15 | Empty : in std_logic; | |
16 | DATA : in std_logic_vector(Data_sz-1 downto 0); |
|
16 | DATA : in std_logic_vector(Data_sz-1 downto 0); | |
17 | Valid : out std_logic; |
|
17 | Valid : out std_logic; | |
18 | Read : out std_logic; |
|
18 | Read : out std_logic; | |
19 | Data_re : out std_logic_vector(Data_sz-1 downto 0); |
|
19 | Data_re : out std_logic_vector(Data_sz-1 downto 0); | |
20 | Data_im : out std_logic_vector(Data_sz-1 downto 0) |
|
20 | Data_im : out std_logic_vector(Data_sz-1 downto 0) | |
21 | ); |
|
21 | ); | |
22 | end entity; |
|
22 | end entity; | |
23 |
|
23 | |||
24 |
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24 | |||
25 | architecture ar_FFTamont of FFTamont is |
|
25 | architecture ar_FFTamont of FFTamont is | |
26 |
|
26 | |||
27 | type etat is (eX,e0,e1,e2); |
|
27 | type etat is (eX,e0,e1,e2); | |
28 | signal ect : etat; |
|
28 | signal ect : etat; | |
29 |
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29 | |||
30 | signal DataCount : integer; |
|
30 | signal DataCount : integer; | |
31 |
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31 | |||
32 | begin |
|
32 | begin | |
33 |
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33 | |||
34 | process(clk,rstn) |
|
34 | process(clk,rstn) | |
35 | begin |
|
35 | begin | |
36 | if(rstn='0')then |
|
36 | if(rstn='0')then | |
37 | ect <= e0; |
|
37 | ect <= e0; | |
38 | Read <= '1'; |
|
38 | Read <= '1'; | |
39 | Valid <= '0'; |
|
39 | Valid <= '0'; | |
40 | Data_re <= (others => '0'); |
|
40 | Data_re <= (others => '0'); | |
41 | Data_im <= (others => '0'); |
|
41 | Data_im <= (others => '0'); | |
42 | DataCount <= 0; |
|
42 | DataCount <= 0; | |
43 |
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43 | |||
44 | elsif(clk'event and clk='1')then |
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44 | elsif(clk'event and clk='1')then | |
45 |
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46 | case ect is |
|
45 | case ect is | |
47 |
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46 | |||
48 |
when e0 => |
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47 | when e0 => | |
49 | if(Load='1' and Empty='0')then |
|
48 | if(Load='1' and Empty='0')then | |
50 | Read <= '0'; |
|
49 | Read <= '0'; | |
51 |
ect <= e |
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50 | ect <= e1; | |
52 | end if; |
|
51 | end if; | |
53 |
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52 | |||
54 |
when e |
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53 | when e1 => | |
55 |
|
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54 | Valid <= '0'; | |
56 |
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55 | Read <= '1'; | ||
57 | when e1 => |
|
56 | ect <= e2; | |
|
57 | ||||
|
58 | when e2 => | |||
58 | Data_re <= DATA; |
|
59 | Data_re <= DATA; | |
59 | Data_im <= (others => '0'); |
|
60 | Data_im <= (others => '0'); | |
60 | Valid <= '1'; |
|
61 | Valid <= '1'; | |
61 |
if(DataCount=NbData- |
|
62 | if(DataCount=NbData-1)then | |
62 | Read <= '1'; |
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|||
63 | DataCount <= DataCount + 1; |
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|||
64 | elsif(DataCount=NbData)then |
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65 | Valid <= '0'; |
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66 | DataCount <= 0; |
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63 | DataCount <= 0; | |
67 |
ect <= e |
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64 | ect <= eX; | |
68 | else |
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65 | else | |
69 | DataCount <= DataCount + 1; |
|
66 | DataCount <= DataCount + 1; | |
70 | end if; |
|
67 | if(Load='1' and Empty='0')then | |
71 |
|
68 | Read <= '0'; | ||
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69 | ect <= e1; | |||
|
70 | else | |||
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71 | ect <= eX; | |||
|
72 | end if; | |||
|
73 | end if; | |||
|
74 | ||||
|
75 | when eX => | |||
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76 | Valid <= '0'; | |||
|
77 | ect <= e0; | |||
|
78 | ||||
72 | when others => |
|
79 | when others => | |
73 | null; |
|
80 | null; | |
74 |
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81 | |||
75 | end case; |
|
82 | end case; | |
|
83 | ||||
|
84 | --*********************************************************** | |||
|
85 | -- Chargement Rapide (toutes a la suite) | |||
|
86 | --*********************************************************** | |||
|
87 | -- case ect is | |||
|
88 | -- | |||
|
89 | -- when e0 => | |||
|
90 | -- if(Load='1' and Empty='0')then | |||
|
91 | -- Read <= '0'; | |||
|
92 | -- ect <= eX; | |||
|
93 | -- end if; | |||
|
94 | -- | |||
|
95 | -- when eX => | |||
|
96 | -- ect <= e1; | |||
|
97 | -- | |||
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98 | -- when e1 => | |||
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99 | -- Data_re <= DATA; | |||
|
100 | -- Data_im <= (others => '0'); | |||
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101 | -- Valid <= '1'; | |||
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102 | -- if(DataCount=NbData-2)then | |||
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103 | -- Read <= '1'; | |||
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104 | -- DataCount <= DataCount + 1; | |||
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105 | -- elsif(DataCount=NbData)then | |||
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106 | -- Valid <= '0'; | |||
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107 | -- DataCount <= 0; | |||
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108 | -- ect <= e0; | |||
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109 | -- else | |||
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110 | -- DataCount <= DataCount + 1; | |||
|
111 | -- end if; | |||
|
112 | -- | |||
|
113 | -- when others => | |||
|
114 | -- null; | |||
|
115 | -- | |||
|
116 | -- end case; | |||
|
117 | --*********************************************************** | |||
76 | end if; |
|
118 | end if; | |
77 | end process; |
|
119 | end process; | |
78 |
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120 | |||
79 | end architecture; |
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121 | end architecture; | |
80 |
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81 |
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82 |
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83 |
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84 |
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85 |
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86 |
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87 |
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88 |
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90 |
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91 |
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92 |
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93 |
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94 |
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95 |
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96 |
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97 |
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98 |
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99 |
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100 |
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@@ -1,639 +1,638 | |||||
1 | ----------------------------------------------------------------------------- |
|
1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
|
2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 |
|
19 | |||
20 |
|
20 | |||
21 | library ieee; |
|
21 | library ieee; | |
22 | use ieee.std_logic_1164.all; |
|
22 | use ieee.std_logic_1164.all; | |
23 | library grlib; |
|
23 | library grlib; | |
24 | use grlib.amba.all; |
|
24 | use grlib.amba.all; | |
25 | use grlib.stdlib.all; |
|
25 | use grlib.stdlib.all; | |
26 | library techmap; |
|
26 | library techmap; | |
27 | use techmap.gencomp.all; |
|
27 | use techmap.gencomp.all; | |
28 | library gaisler; |
|
28 | library gaisler; | |
29 | use gaisler.memctrl.all; |
|
29 | use gaisler.memctrl.all; | |
30 | use gaisler.leon3.all; |
|
30 | use gaisler.leon3.all; | |
31 | use gaisler.uart.all; |
|
31 | use gaisler.uart.all; | |
32 | use gaisler.misc.all; |
|
32 | use gaisler.misc.all; | |
33 | library esa; |
|
33 | library esa; | |
34 | use esa.memoryctrl.all; |
|
34 | use esa.memoryctrl.all; | |
35 | use work.config.all; |
|
35 | use work.config.all; | |
36 | library lpp; |
|
36 | library lpp; | |
37 | use lpp.lpp_amba.all; |
|
37 | use lpp.lpp_amba.all; | |
38 | use lpp.lpp_memory.all; |
|
38 | use lpp.lpp_memory.all; | |
39 | use lpp.lpp_uart.all; |
|
39 | use lpp.lpp_uart.all; | |
40 | use lpp.lpp_matrix.all; |
|
40 | use lpp.lpp_matrix.all; | |
41 | use lpp.lpp_delay.all; |
|
41 | use lpp.lpp_delay.all; | |
42 | use lpp.lpp_fft.all; |
|
42 | use lpp.lpp_fft.all; | |
43 | use lpp.fft_components.all; |
|
43 | use lpp.fft_components.all; | |
44 | use lpp.lpp_ad_conv.all; |
|
44 | use lpp.lpp_ad_conv.all; | |
45 | use lpp.iir_filter.all; |
|
45 | use lpp.iir_filter.all; | |
46 | use lpp.general_purpose.all; |
|
46 | use lpp.general_purpose.all; | |
47 | use lpp.Filtercfg.all; |
|
47 | use lpp.Filtercfg.all; | |
48 |
|
48 | |||
49 | entity leon3mp is |
|
49 | entity leon3mp is | |
50 | generic ( |
|
50 | generic ( | |
51 | fabtech : integer := CFG_FABTECH; |
|
51 | fabtech : integer := CFG_FABTECH; | |
52 | memtech : integer := CFG_MEMTECH; |
|
52 | memtech : integer := CFG_MEMTECH; | |
53 | padtech : integer := CFG_PADTECH; |
|
53 | padtech : integer := CFG_PADTECH; | |
54 | clktech : integer := CFG_CLKTECH; |
|
54 | clktech : integer := CFG_CLKTECH; | |
55 | disas : integer := CFG_DISAS; -- Enable disassembly to console |
|
55 | disas : integer := CFG_DISAS; -- Enable disassembly to console | |
56 | dbguart : integer := CFG_DUART; -- Print UART on console |
|
56 | dbguart : integer := CFG_DUART; -- Print UART on console | |
57 | pclow : integer := CFG_PCLOW |
|
57 | pclow : integer := CFG_PCLOW | |
58 | ); |
|
58 | ); | |
59 | port ( |
|
59 | port ( | |
60 | clk50MHz : in std_ulogic; |
|
60 | clk50MHz : in std_ulogic; | |
61 | reset : in std_ulogic; |
|
61 | reset : in std_ulogic; | |
62 | ramclk : out std_logic; |
|
62 | ramclk : out std_logic; | |
63 |
|
63 | |||
64 | ahbrxd : in std_ulogic; -- DSU rx data |
|
64 | ahbrxd : in std_ulogic; -- DSU rx data | |
65 | ahbtxd : out std_ulogic; -- DSU tx data |
|
65 | ahbtxd : out std_ulogic; -- DSU tx data | |
66 | dsubre : in std_ulogic; |
|
66 | dsubre : in std_ulogic; | |
67 | dsuact : out std_ulogic; |
|
67 | dsuact : out std_ulogic; | |
68 | urxd1 : in std_ulogic; -- UART1 rx data |
|
68 | urxd1 : in std_ulogic; -- UART1 rx data | |
69 | utxd1 : out std_ulogic; -- UART1 tx data |
|
69 | utxd1 : out std_ulogic; -- UART1 tx data | |
70 | errorn : out std_ulogic; |
|
70 | errorn : out std_ulogic; | |
71 |
|
71 | |||
72 | address : out std_logic_vector(18 downto 0); |
|
72 | address : out std_logic_vector(18 downto 0); | |
73 | data : inout std_logic_vector(31 downto 0); |
|
73 | data : inout std_logic_vector(31 downto 0); | |
74 | gpio : inout std_logic_vector(6 downto 0); -- I/O port |
|
74 | gpio : inout std_logic_vector(6 downto 0); -- I/O port | |
75 |
|
75 | |||
76 | nBWa : out std_logic; |
|
76 | nBWa : out std_logic; | |
77 | nBWb : out std_logic; |
|
77 | nBWb : out std_logic; | |
78 | nBWc : out std_logic; |
|
78 | nBWc : out std_logic; | |
79 | nBWd : out std_logic; |
|
79 | nBWd : out std_logic; | |
80 | nBWE : out std_logic; |
|
80 | nBWE : out std_logic; | |
81 | nADSC : out std_logic; |
|
81 | nADSC : out std_logic; | |
82 | nADSP : out std_logic; |
|
82 | nADSP : out std_logic; | |
83 | nADV : out std_logic; |
|
83 | nADV : out std_logic; | |
84 | nGW : out std_logic; |
|
84 | nGW : out std_logic; | |
85 | nCE1 : out std_logic; |
|
85 | nCE1 : out std_logic; | |
86 | CE2 : out std_logic; |
|
86 | CE2 : out std_logic; | |
87 | nCE3 : out std_logic; |
|
87 | nCE3 : out std_logic; | |
88 | nOE : out std_logic; |
|
88 | nOE : out std_logic; | |
89 | MODE : out std_logic; |
|
89 | MODE : out std_logic; | |
90 | SSRAM_CLK : out std_logic; |
|
90 | SSRAM_CLK : out std_logic; | |
91 | ZZ : out std_logic; |
|
91 | ZZ : out std_logic; | |
92 | --------------------------------------------------------------------- |
|
92 | --------------------------------------------------------------------- | |
93 | --- AJOUT TEST ------------------------In/Out----------------------- |
|
93 | --- AJOUT TEST ------------------------In/Out----------------------- | |
94 | --------------------------------------------------------------------- |
|
94 | --------------------------------------------------------------------- | |
95 | -- UART |
|
95 | -- UART | |
96 | UART_RXD : in std_logic; |
|
96 | UART_RXD : in std_logic; | |
97 | UART_TXD : out std_logic; |
|
97 | UART_TXD : out std_logic; | |
98 | -- ADC |
|
98 | -- ADC | |
99 | -- ADC_in : in AD7688_in(4 downto 0); |
|
99 | -- ADC_in : in AD7688_in(4 downto 0); | |
100 | -- ADC_out : out AD7688_out; |
|
100 | -- ADC_out : out AD7688_out; | |
101 | -- Bias_Fails : out std_logic; |
|
101 | -- Bias_Fails : out std_logic; | |
102 | -- CNA |
|
102 | -- CNA | |
103 | -- DAC_SYNC : out std_logic; |
|
103 | -- DAC_SYNC : out std_logic; | |
104 | -- DAC_SCLK : out std_logic; |
|
104 | -- DAC_SCLK : out std_logic; | |
105 | -- DAC_DATA : out std_logic; |
|
105 | -- DAC_DATA : out std_logic; | |
106 | -- Diver |
|
106 | -- Diver | |
107 | SPW1_EN : out std_logic; |
|
107 | SPW1_EN : out std_logic; | |
108 | SPW2_EN : out std_logic; |
|
108 | SPW2_EN : out std_logic; | |
109 | TEST : out std_logic_vector(3 downto 0); |
|
109 | TEST : out std_logic_vector(3 downto 0); | |
110 |
|
110 | |||
111 | BP : in std_logic; |
|
111 | BP : in std_logic; | |
112 | --------------------------------------------------------------------- |
|
112 | --------------------------------------------------------------------- | |
113 | led : out std_logic_vector(1 downto 0) |
|
113 | led : out std_logic_vector(1 downto 0) | |
114 | ); |
|
114 | ); | |
115 | end; |
|
115 | end; | |
116 |
|
116 | |||
117 | architecture Behavioral of leon3mp is |
|
117 | architecture Behavioral of leon3mp is | |
118 |
|
118 | |||
119 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
|
119 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ | |
120 | CFG_GRETH+CFG_AHB_JTAG; |
|
120 | CFG_GRETH+CFG_AHB_JTAG; | |
121 | constant maxahbm : integer := maxahbmsp; |
|
121 | constant maxahbm : integer := maxahbmsp; | |
122 |
|
122 | |||
123 | --Clk & Rst g�n� |
|
123 | --Clk & Rst g�n� | |
124 | signal vcc : std_logic_vector(4 downto 0); |
|
124 | signal vcc : std_logic_vector(4 downto 0); | |
125 | signal gnd : std_logic_vector(4 downto 0); |
|
125 | signal gnd : std_logic_vector(4 downto 0); | |
126 | signal resetnl : std_ulogic; |
|
126 | signal resetnl : std_ulogic; | |
127 | signal clk2x : std_ulogic; |
|
127 | signal clk2x : std_ulogic; | |
128 | signal lclk : std_ulogic; |
|
128 | signal lclk : std_ulogic; | |
129 | signal lclk2x : std_ulogic; |
|
129 | signal lclk2x : std_ulogic; | |
130 | signal clkm : std_ulogic; |
|
130 | signal clkm : std_ulogic; | |
131 | signal rstn : std_ulogic; |
|
131 | signal rstn : std_ulogic; | |
132 | signal rstraw : std_ulogic; |
|
132 | signal rstraw : std_ulogic; | |
133 | signal pciclk : std_ulogic; |
|
133 | signal pciclk : std_ulogic; | |
134 | signal sdclkl : std_ulogic; |
|
134 | signal sdclkl : std_ulogic; | |
135 | signal cgi : clkgen_in_type; |
|
135 | signal cgi : clkgen_in_type; | |
136 | signal cgo : clkgen_out_type; |
|
136 | signal cgo : clkgen_out_type; | |
137 | --- AHB / APB |
|
137 | --- AHB / APB | |
138 | signal apbi : apb_slv_in_type; |
|
138 | signal apbi : apb_slv_in_type; | |
139 | signal apbo : apb_slv_out_vector := (others => apb_none); |
|
139 | signal apbo : apb_slv_out_vector := (others => apb_none); | |
140 | signal ahbsi : ahb_slv_in_type; |
|
140 | signal ahbsi : ahb_slv_in_type; | |
141 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); |
|
141 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); | |
142 | signal ahbmi : ahb_mst_in_type; |
|
142 | signal ahbmi : ahb_mst_in_type; | |
143 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); |
|
143 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); | |
144 | --UART |
|
144 | --UART | |
145 | signal ahbuarti : uart_in_type; |
|
145 | signal ahbuarti : uart_in_type; | |
146 | signal ahbuarto : uart_out_type; |
|
146 | signal ahbuarto : uart_out_type; | |
147 | signal apbuarti : uart_in_type; |
|
147 | signal apbuarti : uart_in_type; | |
148 | signal apbuarto : uart_out_type; |
|
148 | signal apbuarto : uart_out_type; | |
149 | --MEM CTRLR |
|
149 | --MEM CTRLR | |
150 | signal memi : memory_in_type; |
|
150 | signal memi : memory_in_type; | |
151 | signal memo : memory_out_type; |
|
151 | signal memo : memory_out_type; | |
152 | signal wpo : wprot_out_type; |
|
152 | signal wpo : wprot_out_type; | |
153 | signal sdo : sdram_out_type; |
|
153 | signal sdo : sdram_out_type; | |
154 | --IRQ |
|
154 | --IRQ | |
155 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); |
|
155 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); | |
156 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); |
|
156 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); | |
157 | --Timer |
|
157 | --Timer | |
158 | signal gpti : gptimer_in_type; |
|
158 | signal gpti : gptimer_in_type; | |
159 | signal gpto : gptimer_out_type; |
|
159 | signal gpto : gptimer_out_type; | |
160 | --GPIO |
|
160 | --GPIO | |
161 | signal gpioi : gpio_in_type; |
|
161 | signal gpioi : gpio_in_type; | |
162 | signal gpioo : gpio_out_type; |
|
162 | signal gpioo : gpio_out_type; | |
163 | --DSU |
|
163 | --DSU | |
164 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); |
|
164 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); | |
165 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); |
|
165 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); | |
166 | signal dsui : dsu_in_type; |
|
166 | signal dsui : dsu_in_type; | |
167 | signal dsuo : dsu_out_type; |
|
167 | signal dsuo : dsu_out_type; | |
168 |
|
168 | |||
169 | --------------------------------------------------------------------- |
|
169 | --------------------------------------------------------------------- | |
170 | --- AJOUT TEST ------------------------Signaux---------------------- |
|
170 | --- AJOUT TEST ------------------------Signaux---------------------- | |
171 | --------------------------------------------------------------------- |
|
171 | --------------------------------------------------------------------- | |
172 | -- FIFOs |
|
172 | -- FIFOs | |
173 | signal FifoIN_Full : std_logic_vector(0 downto 0);-- |
|
173 | signal FifoIN_Full : std_logic_vector(0 downto 0);-- | |
174 | signal FifoIN_Empty : std_logic_vector(0 downto 0);-- |
|
174 | signal FifoIN_Empty : std_logic_vector(0 downto 0);-- | |
175 | signal FifoIN_Data : std_logic_vector(15 downto 0);-- |
|
175 | signal FifoIN_Data : std_logic_vector(15 downto 0);-- | |
176 |
|
176 | |||
177 | signal FifoINT_Full : std_logic_vector(4 downto 0); |
|
177 | signal FifoINT_Full : std_logic_vector(4 downto 0); | |
178 | signal FifoINT_Data : std_logic_vector(79 downto 0); |
|
178 | signal FifoINT_Data : std_logic_vector(79 downto 0); | |
179 |
|
179 | |||
180 | signal FifoOUT_FullV : std_logic; |
|
180 | signal FifoOUT_FullV : std_logic; | |
181 | signal FifoOUT_Full : std_logic_vector(0 downto 0);-- |
|
181 | signal FifoOUT_Full : std_logic_vector(0 downto 0);-- | |
182 | signal Matrix_WriteV : std_logic_vector(0 downto 0); |
|
182 | signal Matrix_WriteV : std_logic_vector(0 downto 0); | |
183 |
|
183 | |||
184 | -- MATRICE SPECTRALE |
|
184 | -- MATRICE SPECTRALE | |
185 | signal Matrix_Write : std_logic; |
|
185 | signal Matrix_Write : std_logic; | |
186 | signal Matrix_Read : std_logic_vector(1 downto 0); |
|
186 | signal Matrix_Read : std_logic_vector(1 downto 0); | |
187 | signal Matrix_Result : std_logic_vector(31 downto 0); |
|
187 | signal Matrix_Result : std_logic_vector(31 downto 0); | |
188 |
|
188 | |||
189 | signal TopSM_Start : std_logic; |
|
189 | signal TopSM_Start : std_logic; | |
190 | signal TopSM_Statu : std_logic_vector(3 downto 0); |
|
190 | signal TopSM_Statu : std_logic_vector(3 downto 0); | |
191 | signal TopSM_Read : std_logic_vector(4 downto 0); |
|
191 | signal TopSM_Read : std_logic_vector(4 downto 0); | |
192 | signal TopSM_Data1 : std_logic_vector(15 downto 0); |
|
192 | signal TopSM_Data1 : std_logic_vector(15 downto 0); | |
193 | signal TopSM_Data2 : std_logic_vector(15 downto 0); |
|
193 | signal TopSM_Data2 : std_logic_vector(15 downto 0); | |
194 |
|
194 | |||
195 | signal Disp_FlagError : std_logic; |
|
195 | signal Disp_FlagError : std_logic; | |
196 | signal Disp_Pong : std_logic; |
|
196 | signal Disp_Pong : std_logic; | |
197 | signal Disp_Write : std_logic_vector(1 downto 0); |
|
197 | signal Disp_Write : std_logic_vector(1 downto 0); | |
198 | signal Disp_Data : std_logic_vector(63 downto 0); |
|
198 | signal Disp_Data : std_logic_vector(63 downto 0); | |
199 | signal Dma_acq : std_logic; |
|
199 | signal Dma_acq : std_logic; | |
200 |
|
200 | |||
201 | -- FFT |
|
201 | -- FFT | |
202 | signal Drive_Write : std_logic; |
|
202 | signal Drive_Write : std_logic; | |
203 | signal Drive_Read : std_logic_vector(0 downto 0);-- |
|
203 | signal Drive_Read : std_logic_vector(0 downto 0);-- | |
204 | signal Drive_DataRE : std_logic_vector(15 downto 0); |
|
204 | signal Drive_DataRE : std_logic_vector(15 downto 0); | |
205 | signal Drive_DataIM : std_logic_vector(15 downto 0); |
|
205 | signal Drive_DataIM : std_logic_vector(15 downto 0); | |
206 |
|
206 | |||
207 | signal Start : std_logic; |
|
207 | signal Start : std_logic; | |
208 | signal RstnFFT : std_logic; |
|
208 | signal RstnFFT : std_logic; | |
209 | signal FFT_Load : std_logic; |
|
209 | signal FFT_Load : std_logic; | |
210 | signal FFT_Ready : std_logic; |
|
210 | signal FFT_Ready : std_logic; | |
211 | signal FFT_Valid : std_logic; |
|
211 | signal FFT_Valid : std_logic; | |
212 | signal FFT_DataRE : std_logic_vector(15 downto 0); |
|
212 | signal FFT_DataRE : std_logic_vector(15 downto 0); | |
213 | signal FFT_DataIM : std_logic_vector(15 downto 0); |
|
213 | signal FFT_DataIM : std_logic_vector(15 downto 0); | |
214 |
|
214 | |||
215 | signal Link_Read : std_logic; |
|
215 | signal Link_Read : std_logic; | |
216 | signal Link_Write : std_logic_vector(0 downto 0);-- |
|
216 | signal Link_Write : std_logic_vector(0 downto 0);-- | |
217 | signal Link_ReUse : std_logic_vector(0 downto 0);-- |
|
217 | signal Link_ReUse : std_logic_vector(0 downto 0);-- | |
218 | signal Link_Data : std_logic_vector(15 downto 0);-- |
|
218 | signal Link_Data : std_logic_vector(15 downto 0);-- | |
219 |
|
219 | |||
220 | -- ADC |
|
220 | -- ADC | |
221 | signal SmplClk : std_logic; |
|
221 | signal SmplClk : std_logic; | |
222 | signal ADC_DataReady : std_logic; |
|
222 | signal ADC_DataReady : std_logic; | |
223 | signal ADC_SmplOut : Samples_out(4 downto 0); |
|
223 | signal ADC_SmplOut : Samples_out(4 downto 0); | |
224 | signal enableADC : std_logic; |
|
224 | signal enableADC : std_logic; | |
225 |
|
225 | |||
226 | signal WG_Write : std_logic_vector(4 downto 0); |
|
226 | signal WG_Write : std_logic_vector(4 downto 0); | |
227 | signal WG_ReUse : std_logic_vector(4 downto 0); |
|
227 | signal WG_ReUse : std_logic_vector(4 downto 0); | |
228 | signal WG_DATA : std_logic_vector(79 downto 0); |
|
228 | signal WG_DATA : std_logic_vector(79 downto 0); | |
229 | signal s_out : std_logic_vector(79 downto 0); |
|
229 | signal s_out : std_logic_vector(79 downto 0); | |
230 |
|
230 | |||
231 | signal fuller : std_logic_vector(4 downto 0); |
|
231 | signal fuller : std_logic_vector(4 downto 0); | |
232 | signal reader : std_logic_vector(4 downto 0); |
|
232 | signal reader : std_logic_vector(4 downto 0); | |
233 | signal try : std_logic_vector(1 downto 0); |
|
233 | signal try : std_logic_vector(1 downto 0); | |
234 | signal TXDint : std_logic; |
|
234 | signal TXDint : std_logic; | |
235 |
|
235 | |||
236 | -- IIR Filter |
|
236 | -- IIR Filter | |
237 | signal sample_clk_out : std_logic; |
|
237 | signal sample_clk_out : std_logic; | |
238 |
|
238 | |||
239 | signal Rd : std_logic_vector(0 downto 0);-- |
|
239 | signal Rd : std_logic_vector(0 downto 0);-- | |
240 | signal Ept : std_logic_vector(0 downto 0);-- |
|
240 | signal Ept : std_logic_vector(0 downto 0);-- | |
241 |
|
241 | |||
242 | signal Bwr : std_logic_vector(0 downto 0); |
|
242 | signal Bwr : std_logic_vector(0 downto 0); | |
243 | signal Bre : std_logic_vector(0 downto 0); |
|
243 | signal Bre : std_logic_vector(0 downto 0); | |
244 | signal DataTMP : std_logic_vector(15 downto 0); |
|
244 | signal DataTMP : std_logic_vector(15 downto 0); | |
245 | signal FullUp : std_logic_vector(0 downto 0); |
|
245 | signal FullUp : std_logic_vector(0 downto 0); | |
246 | signal EmptyUp : std_logic_vector(0 downto 0); |
|
246 | signal EmptyUp : std_logic_vector(0 downto 0); | |
247 | signal FullDown : std_logic_vector(0 downto 0); |
|
247 | signal FullDown : std_logic_vector(0 downto 0); | |
248 | signal EmptyDown : std_logic_vector(0 downto 0); |
|
248 | signal EmptyDown : std_logic_vector(0 downto 0); | |
249 | --------------------------------------------------------------------- |
|
249 | --------------------------------------------------------------------- | |
250 | constant IOAEN : integer := CFG_CAN; |
|
250 | constant IOAEN : integer := CFG_CAN; | |
251 | constant boardfreq : integer := 50000; |
|
251 | constant boardfreq : integer := 50000; | |
252 |
|
252 | |||
253 | begin |
|
253 | begin | |
254 |
|
254 | |||
255 | --------------------------------------------------------------------- |
|
255 | --------------------------------------------------------------------- | |
256 | --- AJOUT TEST -------------------------------------IPs------------- |
|
256 | --- AJOUT TEST -------------------------------------IPs------------- | |
257 | --------------------------------------------------------------------- |
|
257 | --------------------------------------------------------------------- | |
258 | led(1 downto 0) <= gpio(1 downto 0); |
|
258 | led(1 downto 0) <= gpio(1 downto 0); | |
259 |
|
259 | |||
260 | --- COM USB --------------------------------------------------------- |
|
260 | --- COM USB --------------------------------------------------------- | |
261 | -- MemIn0 : APB_FifoWrite |
|
261 | -- MemIn0 : APB_FifoWrite | |
262 | -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
|
262 | -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) | |
263 | -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); |
|
263 | -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); | |
264 | -- |
|
264 | -- | |
265 | -- BUF0 : APB_USB |
|
265 | -- BUF0 : APB_USB | |
266 | -- generic map (6,6,DataMax => 1024) |
|
266 | -- generic map (6,6,DataMax => 1024) | |
267 | -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); |
|
267 | -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); | |
268 | -- |
|
268 | -- | |
269 | -- MemOut0 : APB_FifoRead |
|
269 | -- MemOut0 : APB_FifoRead | |
270 | -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
|
270 | -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) | |
271 | -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); |
|
271 | -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); | |
272 | -- |
|
272 | -- | |
273 | --slrd <= usb_Read; |
|
273 | --slrd <= usb_Read; | |
274 | --slwr <= usb_Write; |
|
274 | --slwr <= usb_Write; | |
275 |
|
275 | |||
276 | --- CNA ------------------------------------------------------------- |
|
276 | --- CNA ------------------------------------------------------------- | |
277 |
|
277 | |||
278 | -- CONV : APB_CNA |
|
278 | -- CONV : APB_CNA | |
279 | -- generic map (5,5) |
|
279 | -- generic map (5,5) | |
280 | -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); |
|
280 | -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); | |
281 |
|
281 | |||
282 | --TEST(0) <= SmplClk; |
|
282 | --TEST(0) <= SmplClk; | |
283 | --TEST(1) <= WG_Write(0); |
|
283 | --TEST(1) <= WG_Write(0); | |
284 | --TEST(2) <= Fuller(0); |
|
284 | --TEST(2) <= Fuller(0); | |
285 | --TEST(3) <= s_out(s_out'length-1); |
|
285 | --TEST(3) <= s_out(s_out'length-1); | |
286 |
|
286 | |||
287 |
|
287 | |||
288 | SPW1_EN <= '1'; |
|
288 | SPW1_EN <= '1'; | |
289 | SPW2_EN <= '0'; |
|
289 | SPW2_EN <= '0'; | |
290 |
|
290 | |||
291 | --- CAN ------------------------------------------------------------- |
|
291 | --- CAN ------------------------------------------------------------- | |
292 |
|
292 | |||
293 | -- Divider : Clk_divider |
|
293 | -- Divider : Clk_divider | |
294 | -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) |
|
294 | -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) | |
295 | -- Port map(clkm,rstn,SmplClk); |
|
295 | -- Port map(clkm,rstn,SmplClk); | |
296 | -- |
|
296 | -- | |
297 | -- ADC : AD7688_drvr |
|
297 | -- ADC : AD7688_drvr | |
298 | -- generic map (ChanelCount => 5, clkkHz => 24_576) |
|
298 | -- generic map (ChanelCount => 5, clkkHz => 24_576) | |
299 | -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); |
|
299 | -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); | |
300 | -- |
|
300 | -- | |
301 | -- WG : WriteGen_ADC |
|
301 | -- WG : WriteGen_ADC | |
302 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); |
|
302 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); | |
303 | -- |
|
303 | -- | |
304 | --enableADC <= gpio(0); |
|
304 | --enableADC <= gpio(0); | |
305 | --Bias_Fails <= '0'; |
|
305 | --Bias_Fails <= '0'; | |
306 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); |
|
306 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); | |
307 | -- |
|
307 | -- | |
308 | -- |
|
308 | -- | |
309 | -- MemIn1 : APB_FIFO |
|
309 | -- MemIn1 : APB_FIFO | |
310 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
310 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
311 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); |
|
311 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); | |
312 |
|
312 | |||
313 | --- FFT ------------------------------------------------------------- |
|
313 | --- FFT ------------------------------------------------------------- | |
314 |
|
314 | |||
315 | MemIn : APB_FIFO |
|
315 | MemIn : APB_FIFO | |
316 | generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) |
|
316 | generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) | |
317 | port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); |
|
317 | port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); | |
318 | -- MemIn : APB_FIFO |
|
318 | -- MemIn : APB_FIFO | |
319 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
|
319 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) | |
320 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others =>'1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); |
|
320 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others =>'1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); | |
321 | -- |
|
321 | -- | |
322 | test(0) <= gpio(1); |
|
322 | ||
323 | Start <= '0'; |
|
323 | Start <= '0'; | |
324 | rstnFFT <= gpio(0); |
|
324 | ||
325 | -- |
|
|||
326 | DRIVE : FFTamont |
|
325 | DRIVE : FFTamont | |
327 | generic map(Data_sz => 16,NbData => 256) |
|
326 | generic map(Data_sz => 16,NbData => 256) | |
328 | port map(clkm,rstn,FFT_Load,FifoIN_Empty(0),FifoIN_Data,Drive_Write,Drive_Read(0),Drive_DataRE,Drive_DataIM); |
|
327 | port map(clkm,rstn,FFT_Load,FifoIN_Empty(0),FifoIN_Data,Drive_Write,Drive_Read(0),Drive_DataRE,Drive_DataIM); | |
329 | -- DRIVE : Driver_FFT |
|
328 | -- DRIVE : Driver_FFT | |
330 | -- generic map(Data_sz => 16) |
|
329 | -- generic map(Data_sz => 16) | |
331 | -- port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Full,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM); |
|
330 | -- port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Full,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM); | |
332 | -- |
|
331 | -- | |
333 | FFT : CoreFFT |
|
332 | FFT : CoreFFT | |
334 | generic map( |
|
333 | generic map( | |
335 | LOGPTS => gLOGPTS, |
|
334 | LOGPTS => gLOGPTS, | |
336 | LOGLOGPTS => gLOGLOGPTS, |
|
335 | LOGLOGPTS => gLOGLOGPTS, | |
337 | WSIZE => gWSIZE, |
|
336 | WSIZE => gWSIZE, | |
338 | TWIDTH => gTWIDTH, |
|
337 | TWIDTH => gTWIDTH, | |
339 | DWIDTH => gDWIDTH, |
|
338 | DWIDTH => gDWIDTH, | |
340 | TDWIDTH => gTDWIDTH, |
|
339 | TDWIDTH => gTDWIDTH, | |
341 | RND_MODE => gRND_MODE, |
|
340 | RND_MODE => gRND_MODE, | |
342 | SCALE_MODE => gSCALE_MODE, |
|
341 | SCALE_MODE => gSCALE_MODE, | |
343 | PTS => gPTS, |
|
342 | PTS => gPTS, | |
344 | HALFPTS => gHALFPTS, |
|
343 | HALFPTS => gHALFPTS, | |
345 | inBuf_RWDLY => gInBuf_RWDLY) |
|
344 | inBuf_RWDLY => gInBuf_RWDLY) | |
346 |
port map(clkm,start,rstn |
|
345 | port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); | |
347 | -- |
|
346 | -- | |
348 | -- LINK : Linker_FFT |
|
347 | -- LINK : Linker_FFT | |
349 | -- generic map(Data_sz => 16) |
|
348 | -- generic map(Data_sz => 16) | |
350 | -- port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);--FifoOUT_Full/FifoINT_Full |
|
349 | -- port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);--FifoOUT_Full/FifoINT_Full | |
351 | LINK : FFTaval |
|
350 | LINK : FFTaval | |
352 | generic map(Data_sz => 16,NbData => 256) |
|
351 | generic map(Data_sz => 16,NbData => 256) | |
353 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full(0),FFT_DataRE,FFT_DataIM,Link_Read,Link_Write(0),Link_ReUse(0),Link_Data); |
|
352 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full(0),FFT_DataRE,FFT_DataIM,Link_Read,Link_Write(0),Link_ReUse(0),Link_Data); | |
354 | -- |
|
353 | -- | |
355 | ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- |
|
354 | ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- | |
356 | -- |
|
355 | -- | |
357 | MemOut : APB_FIFO |
|
356 | MemOut : APB_FIFO | |
358 | generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
357 | generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
359 | port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9)); |
|
358 | port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9)); | |
360 |
|
359 | |||
361 |
|
360 | |||
362 | --TEST(0) <= FifoOUT_Full(0); |
|
361 | --TEST(0) <= FifoOUT_Full(0); | |
363 | --TEST(1) <= Link_Write(0); |
|
362 | --TEST(1) <= Link_Write(0); | |
364 |
|
363 | |||
365 | -- MemInt : lppFIFOx5 |
|
364 | -- MemInt : lppFIFOx5 | |
366 | -- generic map(Data_sz => 16, Enable_ReUse => '1') |
|
365 | -- generic map(Data_sz => 16, Enable_ReUse => '1') | |
367 | -- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); |
|
366 | -- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); | |
368 | -- |
|
367 | -- | |
369 | --Matrix_WriteV(0) <= not Matrix_Write; |
|
368 | --Matrix_WriteV(0) <= not Matrix_Write; | |
370 | --FifoOUT_FullV <= FifoOUT_Full(0); |
|
369 | --FifoOUT_FullV <= FifoOUT_Full(0); | |
371 | -- |
|
370 | -- | |
372 | ---- MemInt : lppFIFOxN |
|
371 | ---- MemInt : lppFIFOxN | |
373 | ---- generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') |
|
372 | ---- generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') | |
374 | ---- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); |
|
373 | ---- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); | |
375 | -- |
|
374 | -- | |
376 | -- TopSM : TopMatrix_PDR |
|
375 | -- TopSM : TopMatrix_PDR | |
377 | -- generic map (Input_SZ => 16) |
|
376 | -- generic map (Input_SZ => 16) | |
378 | -- port map (clkm,rstn,FifoINT_Data,FifoINT_Full,Matrix_Read,Matrix_Write,TopSM_Data1,TopSM_Data2,TopSM_Start,TopSM_Read,TopSM_Statu); |
|
377 | -- port map (clkm,rstn,FifoINT_Data,FifoINT_Full,Matrix_Read,Matrix_Write,TopSM_Data1,TopSM_Data2,TopSM_Start,TopSM_Read,TopSM_Statu); | |
379 | -- |
|
378 | -- | |
380 | -- SM : SpectralMatrix |
|
379 | -- SM : SpectralMatrix | |
381 | -- generic map (Input_SZ => 16, Result_SZ => 32) |
|
380 | -- generic map (Input_SZ => 16, Result_SZ => 32) | |
382 | -- port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); |
|
381 | -- port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); | |
383 |
|
382 | |||
384 |
|
383 | |||
385 | --***************************************TEST DEMI-FIFO******************************************************************************** |
|
384 | --***************************************TEST DEMI-FIFO******************************************************************************** | |
386 | -- MemIn : APB_FIFO |
|
385 | -- MemIn : APB_FIFO | |
387 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
|
386 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) | |
388 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); |
|
387 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); | |
389 | -- |
|
388 | -- | |
390 | -- Pont : Bridge |
|
389 | -- Pont : Bridge | |
391 | -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); |
|
390 | -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); | |
392 | -- |
|
391 | -- | |
393 | -- MemOut : APB_FIFO |
|
392 | -- MemOut : APB_FIFO | |
394 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
393 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
395 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); |
|
394 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); | |
396 | --************************************************************************************************************************************* |
|
395 | --************************************************************************************************************************************* | |
397 |
|
396 | |||
398 |
|
397 | |||
399 |
|
398 | |||
400 |
|
399 | |||
401 |
|
400 | |||
402 |
|
401 | |||
403 |
|
402 | |||
404 |
|
403 | |||
405 |
|
404 | |||
406 |
|
405 | |||
407 |
|
406 | |||
408 | --Dma_acq <= '1'; |
|
407 | --Dma_acq <= '1'; | |
409 | -- |
|
408 | -- | |
410 | -- DISP : Dispatch |
|
409 | -- DISP : Dispatch | |
411 | -- generic map(Data_SZ => 32) |
|
410 | -- generic map(Data_SZ => 32) | |
412 | -- port map(clkm,reset,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError); |
|
411 | -- port map(clkm,reset,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError); | |
413 | -- |
|
412 | -- | |
414 | ----- FIFO ------------------------------------------------------------- |
|
413 | ----- FIFO ------------------------------------------------------------- | |
415 | -- |
|
414 | -- | |
416 | -- MemOut : APB_FIFO |
|
415 | -- MemOut : APB_FIFO | |
417 | -- generic map (pindex => 15, paddr => 15, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
416 | -- generic map (pindex => 15, paddr => 15, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
418 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(15)); |
|
417 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(15)); | |
419 | -- |
|
418 | -- | |
420 | Memtest : APB_FIFO |
|
419 | Memtest : APB_FIFO | |
421 | generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) |
|
420 | generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) | |
422 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); |
|
421 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); | |
423 |
|
422 | |||
424 | --- UART ------------------------------------------------------------- |
|
423 | --- UART ------------------------------------------------------------- | |
425 |
|
424 | |||
426 | COM0 : APB_UART |
|
425 | COM0 : APB_UART | |
427 | generic map (pindex => 4, paddr => 4) |
|
426 | generic map (pindex => 4, paddr => 4) | |
428 | port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD); |
|
427 | port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD); | |
429 |
|
428 | |||
430 | --- DELAY ------------------------------------------------------------ |
|
429 | --- DELAY ------------------------------------------------------------ | |
431 |
|
430 | |||
432 | -- Delay0 : APB_Delay |
|
431 | -- Delay0 : APB_Delay | |
433 | -- generic map (pindex => 4, paddr => 4) |
|
432 | -- generic map (pindex => 4, paddr => 4) | |
434 | -- port map (clkm,rstn,apbi,apbo(4)); |
|
433 | -- port map (clkm,rstn,apbi,apbo(4)); | |
435 |
|
434 | |||
436 | --- IIR Filter ------------------------------------------------------- |
|
435 | --- IIR Filter ------------------------------------------------------- | |
437 | --Test(0) <= sample_clk_out; |
|
436 | --Test(0) <= sample_clk_out; | |
438 | -- |
|
437 | -- | |
439 | -- |
|
438 | -- | |
440 | -- IIR1: APB_IIR_Filter |
|
439 | -- IIR1: APB_IIR_Filter | |
441 | -- generic map( |
|
440 | -- generic map( | |
442 | -- tech => CFG_MEMTECH, |
|
441 | -- tech => CFG_MEMTECH, | |
443 | -- pindex => 8, |
|
442 | -- pindex => 8, | |
444 | -- paddr => 8, |
|
443 | -- paddr => 8, | |
445 | -- Sample_SZ => Sample_SZ, |
|
444 | -- Sample_SZ => Sample_SZ, | |
446 | -- ChanelsCount => ChanelsCount, |
|
445 | -- ChanelsCount => ChanelsCount, | |
447 | -- Coef_SZ => Coef_SZ, |
|
446 | -- Coef_SZ => Coef_SZ, | |
448 | -- CoefCntPerCel => CoefCntPerCel, |
|
447 | -- CoefCntPerCel => CoefCntPerCel, | |
449 | -- Cels_count => Cels_count, |
|
448 | -- Cels_count => Cels_count, | |
450 | -- virgPos => virgPos |
|
449 | -- virgPos => virgPos | |
451 | -- ) |
|
450 | -- ) | |
452 | -- port map( |
|
451 | -- port map( | |
453 | -- rst => rstn, |
|
452 | -- rst => rstn, | |
454 | -- clk => clkm, |
|
453 | -- clk => clkm, | |
455 | -- apbi => apbi, |
|
454 | -- apbi => apbi, | |
456 | -- apbo => apbo(8), |
|
455 | -- apbo => apbo(8), | |
457 | -- sample_clk_out => sample_clk_out, |
|
456 | -- sample_clk_out => sample_clk_out, | |
458 | -- GOtest => Test(1), |
|
457 | -- GOtest => Test(1), | |
459 | -- CoefsInitVal => (others => '1') |
|
458 | -- CoefsInitVal => (others => '1') | |
460 | -- ); |
|
459 | -- ); | |
461 | ---------------------------------------------------------------------- |
|
460 | ---------------------------------------------------------------------- | |
462 |
|
461 | |||
463 | ---------------------------------------------------------------------- |
|
462 | ---------------------------------------------------------------------- | |
464 | --- Reset and Clock generation ------------------------------------- |
|
463 | --- Reset and Clock generation ------------------------------------- | |
465 | ---------------------------------------------------------------------- |
|
464 | ---------------------------------------------------------------------- | |
466 |
|
465 | |||
467 | vcc <= (others => '1'); gnd <= (others => '0'); |
|
466 | vcc <= (others => '1'); gnd <= (others => '0'); | |
468 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
|
467 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; | |
469 |
|
468 | |||
470 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); |
|
469 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); | |
471 |
|
470 | |||
472 |
|
471 | |||
473 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); |
|
472 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); | |
474 |
|
473 | |||
475 | clkgen0 : clkgen -- clock generator |
|
474 | clkgen0 : clkgen -- clock generator | |
476 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
475 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
477 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
|
476 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) | |
478 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); |
|
477 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); | |
479 |
|
478 | |||
480 | ramclk <= clkm; |
|
479 | ramclk <= clkm; | |
481 | process(lclk2x) |
|
480 | process(lclk2x) | |
482 | begin |
|
481 | begin | |
483 | if lclk2x'event and lclk2x = '1' then |
|
482 | if lclk2x'event and lclk2x = '1' then | |
484 | lclk <= not lclk; |
|
483 | lclk <= not lclk; | |
485 | end if; |
|
484 | end if; | |
486 | end process; |
|
485 | end process; | |
487 |
|
486 | |||
488 | ---------------------------------------------------------------------- |
|
487 | ---------------------------------------------------------------------- | |
489 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
488 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
490 | ---------------------------------------------------------------------- |
|
489 | ---------------------------------------------------------------------- | |
491 |
|
490 | |||
492 | l3 : if CFG_LEON3 = 1 generate |
|
491 | l3 : if CFG_LEON3 = 1 generate | |
493 | cpu : for i in 0 to CFG_NCPU-1 generate |
|
492 | cpu : for i in 0 to CFG_NCPU-1 generate | |
494 | u0 : leon3s -- LEON3 processor |
|
493 | u0 : leon3s -- LEON3 processor | |
495 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
494 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
496 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
495 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
497 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
496 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
498 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
497 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
499 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
498 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
500 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
499 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) | |
501 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
500 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, | |
502 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
501 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
503 | end generate; |
|
502 | end generate; | |
504 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); |
|
503 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); | |
505 |
|
504 | |||
506 | dsugen : if CFG_DSU = 1 generate |
|
505 | dsugen : if CFG_DSU = 1 generate | |
507 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
506 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
508 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
507 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
509 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
508 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
510 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
509 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
511 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); |
|
510 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); | |
512 | dsui.enable <= '1'; |
|
511 | dsui.enable <= '1'; | |
513 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); |
|
512 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); | |
514 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); |
|
513 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); | |
515 | end generate; |
|
514 | end generate; | |
516 | end generate; |
|
515 | end generate; | |
517 |
|
516 | |||
518 | nodsu : if CFG_DSU = 0 generate |
|
517 | nodsu : if CFG_DSU = 0 generate | |
519 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
|
518 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; | |
520 | end generate; |
|
519 | end generate; | |
521 |
|
520 | |||
522 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate |
|
521 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate | |
523 | irqctrl0 : irqmp -- interrupt controller |
|
522 | irqctrl0 : irqmp -- interrupt controller | |
524 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
523 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
525 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
524 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
526 | end generate; |
|
525 | end generate; | |
527 | irq3 : if CFG_IRQ3_ENABLE = 0 generate |
|
526 | irq3 : if CFG_IRQ3_ENABLE = 0 generate | |
528 | x : for i in 0 to CFG_NCPU-1 generate |
|
527 | x : for i in 0 to CFG_NCPU-1 generate | |
529 | irqi(i).irl <= "0000"; |
|
528 | irqi(i).irl <= "0000"; | |
530 | end generate; |
|
529 | end generate; | |
531 | apbo(2) <= apb_none; |
|
530 | apbo(2) <= apb_none; | |
532 | end generate; |
|
531 | end generate; | |
533 |
|
532 | |||
534 | ---------------------------------------------------------------------- |
|
533 | ---------------------------------------------------------------------- | |
535 | --- Memory controllers --------------------------------------------- |
|
534 | --- Memory controllers --------------------------------------------- | |
536 | ---------------------------------------------------------------------- |
|
535 | ---------------------------------------------------------------------- | |
537 |
|
536 | |||
538 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) |
|
537 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) | |
539 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); |
|
538 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); | |
540 |
|
539 | |||
541 | memi.brdyn <= '1'; memi.bexcn <= '1'; |
|
540 | memi.brdyn <= '1'; memi.bexcn <= '1'; | |
542 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; |
|
541 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; | |
543 |
|
542 | |||
544 | bdr : for i in 0 to 3 generate |
|
543 | bdr : for i in 0 to 3 generate | |
545 | data_pad : iopadv generic map (tech => padtech, width => 8) |
|
544 | data_pad : iopadv generic map (tech => padtech, width => 8) | |
546 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), |
|
545 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), | |
547 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); |
|
546 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); | |
548 | end generate; |
|
547 | end generate; | |
549 |
|
548 | |||
550 |
|
549 | |||
551 | addr_pad : outpadv generic map (width => 19, tech => padtech) |
|
550 | addr_pad : outpadv generic map (width => 19, tech => padtech) | |
552 | port map (address, memo.address(20 downto 2)); |
|
551 | port map (address, memo.address(20 downto 2)); | |
553 |
|
552 | |||
554 |
|
553 | |||
555 | SSRAM_0:entity ssram_plugin |
|
554 | SSRAM_0:entity ssram_plugin | |
556 | generic map (tech => padtech) |
|
555 | generic map (tech => padtech) | |
557 | port map |
|
556 | port map | |
558 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); |
|
557 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); | |
559 |
|
558 | |||
560 | ---------------------------------------------------------------------- |
|
559 | ---------------------------------------------------------------------- | |
561 | --- AHB CONTROLLER ------------------------------------------------- |
|
560 | --- AHB CONTROLLER ------------------------------------------------- | |
562 | ---------------------------------------------------------------------- |
|
561 | ---------------------------------------------------------------------- | |
563 |
|
562 | |||
564 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
563 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
565 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
564 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
566 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
565 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
567 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
|
566 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | |
568 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
567 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
569 |
|
568 | |||
570 | ---------------------------------------------------------------------- |
|
569 | ---------------------------------------------------------------------- | |
571 | --- AHB UART ------------------------------------------------------- |
|
570 | --- AHB UART ------------------------------------------------------- | |
572 | ---------------------------------------------------------------------- |
|
571 | ---------------------------------------------------------------------- | |
573 |
|
572 | |||
574 | dcomgen : if CFG_AHB_UART = 1 generate |
|
573 | dcomgen : if CFG_AHB_UART = 1 generate | |
575 | dcom0: ahbuart -- Debug UART |
|
574 | dcom0: ahbuart -- Debug UART | |
576 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) |
|
575 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) | |
577 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); |
|
576 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); | |
578 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); |
|
577 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); | |
579 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); |
|
578 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); | |
580 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; |
|
579 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; | |
581 | end generate; |
|
580 | end generate; | |
582 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; |
|
581 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; | |
583 |
|
582 | |||
584 | ---------------------------------------------------------------------- |
|
583 | ---------------------------------------------------------------------- | |
585 | --- APB Bridge ----------------------------------------------------- |
|
584 | --- APB Bridge ----------------------------------------------------- | |
586 | ---------------------------------------------------------------------- |
|
585 | ---------------------------------------------------------------------- | |
587 |
|
586 | |||
588 | apb0 : apbctrl -- AHB/APB bridge |
|
587 | apb0 : apbctrl -- AHB/APB bridge | |
589 | generic map (hindex => 1, haddr => CFG_APBADDR) |
|
588 | generic map (hindex => 1, haddr => CFG_APBADDR) | |
590 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); |
|
589 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); | |
591 |
|
590 | |||
592 | ---------------------------------------------------------------------- |
|
591 | ---------------------------------------------------------------------- | |
593 | --- GPT Timer ------------------------------------------------------ |
|
592 | --- GPT Timer ------------------------------------------------------ | |
594 | ---------------------------------------------------------------------- |
|
593 | ---------------------------------------------------------------------- | |
595 |
|
594 | |||
596 | gpt : if CFG_GPT_ENABLE /= 0 generate |
|
595 | gpt : if CFG_GPT_ENABLE /= 0 generate | |
597 | timer0 : gptimer -- timer unit |
|
596 | timer0 : gptimer -- timer unit | |
598 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
597 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
599 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
598 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
600 | nbits => CFG_GPT_TW) |
|
599 | nbits => CFG_GPT_TW) | |
601 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
600 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
602 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; |
|
601 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; | |
603 | -- led(4) <= gpto.wdog; |
|
602 | -- led(4) <= gpto.wdog; | |
604 | end generate; |
|
603 | end generate; | |
605 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; |
|
604 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; | |
606 |
|
605 | |||
607 |
|
606 | |||
608 | ---------------------------------------------------------------------- |
|
607 | ---------------------------------------------------------------------- | |
609 | --- APB UART ------------------------------------------------------- |
|
608 | --- APB UART ------------------------------------------------------- | |
610 | ---------------------------------------------------------------------- |
|
609 | ---------------------------------------------------------------------- | |
611 |
|
610 | |||
612 | ua1 : if CFG_UART1_ENABLE /= 0 generate |
|
611 | ua1 : if CFG_UART1_ENABLE /= 0 generate | |
613 | uart1 : apbuart -- UART 1 |
|
612 | uart1 : apbuart -- UART 1 | |
614 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
613 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
615 | fifosize => CFG_UART1_FIFO) |
|
614 | fifosize => CFG_UART1_FIFO) | |
616 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); |
|
615 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); | |
617 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; |
|
616 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; | |
618 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; |
|
617 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; | |
619 | -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; |
|
618 | -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; | |
620 | end generate; |
|
619 | end generate; | |
621 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; |
|
620 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; | |
622 |
|
621 | |||
623 | ---------------------------------------------------------------------- |
|
622 | ---------------------------------------------------------------------- | |
624 | --- GPIO ----------------------------------------------------------- |
|
623 | --- GPIO ----------------------------------------------------------- | |
625 | ---------------------------------------------------------------------- |
|
624 | ---------------------------------------------------------------------- | |
626 |
|
625 | |||
627 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit |
|
626 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit | |
628 | grgpio0: grgpio |
|
627 | grgpio0: grgpio | |
629 | generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) |
|
628 | generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) | |
630 | port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); |
|
629 | port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); | |
631 |
|
630 | |||
632 | pio_pads : for i in 0 to 6 generate |
|
631 | pio_pads : for i in 0 to 6 generate | |
633 | pio_pad : iopad generic map (tech => padtech) |
|
632 | pio_pad : iopad generic map (tech => padtech) | |
634 | port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); |
|
633 | port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); | |
635 | end generate; |
|
634 | end generate; | |
636 | end generate; |
|
635 | end generate; | |
637 |
|
636 | |||
638 |
|
637 | |||
639 | end Behavioral; No newline at end of file |
|
638 | end Behavioral; |
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