@@ -428,7 +428,7 BEGIN -- beh | |||||
428 | pirq_ms => 6, |
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428 | pirq_ms => 6, | |
429 | pirq_wfp => 14, |
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429 | pirq_wfp => 14, | |
430 | hindex => 2, |
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430 | hindex => 2, | |
431 |
top_lfr_version => X"00011 |
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431 | top_lfr_version => X"00011D") -- aa.bb.cc version | |
432 | PORT MAP ( |
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432 | PORT MAP ( | |
433 | clk => clk_25, |
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433 | clk => clk_25, | |
434 | rstn => reset, |
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434 | rstn => reset, |
@@ -58,6 +58,8 ARCHITECTURE beh OF cic_lfr_control IS | |||||
58 |
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58 | |||
59 | TYPE STATE_CIC_LFR_TYPE IS (IDLE,INT_0, INT_1, INT_2); |
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59 | TYPE STATE_CIC_LFR_TYPE IS (IDLE,INT_0, INT_1, INT_2); | |
60 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; |
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60 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; | |
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61 | ||||
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62 | SIGNAL nb_data_receipt : INTEGER; | |||
61 |
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63 | |||
62 | BEGIN |
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64 | BEGIN | |
63 |
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65 | |||
@@ -81,6 +83,8 BEGIN | |||||
81 | w_addr_init <= '0'; |
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83 | w_addr_init <= '0'; | |
82 | w_addr_base <= (OTHERS => '0'); |
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84 | w_addr_base <= (OTHERS => '0'); | |
83 | w_addr_add1 <= '0'; |
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85 | w_addr_add1 <= '0'; | |
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86 | -- | |||
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87 | nb_data_receipt <= 0; | |||
84 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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88 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
85 | IF run = '0' THEN |
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89 | IF run = '0' THEN | |
86 | STATE_CIC_LFR <= IDLE; |
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90 | STATE_CIC_LFR <= IDLE; | |
@@ -100,6 +104,8 BEGIN | |||||
100 | w_addr_init <= '0'; |
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104 | w_addr_init <= '0'; | |
101 | w_addr_base <= (OTHERS => '0'); |
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105 | w_addr_base <= (OTHERS => '0'); | |
102 | w_addr_add1 <= '0'; |
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106 | w_addr_add1 <= '0'; | |
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107 | -- | |||
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108 | nb_data_receipt <= 0; | |||
103 | ELSE |
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109 | ELSE | |
104 | CASE STATE_CIC_LFR IS |
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110 | CASE STATE_CIC_LFR IS | |
105 | WHEN IDLE => |
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111 | WHEN IDLE => | |
@@ -118,6 +124,12 BEGIN | |||||
118 | w_addr_init <= '0'; |
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124 | w_addr_init <= '0'; | |
119 | w_addr_base <= (OTHERS => '0'); |
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125 | w_addr_base <= (OTHERS => '0'); | |
120 | w_addr_add1 <= '0'; |
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126 | w_addr_add1 <= '0'; | |
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127 | IF data_in_valid = '1' THEN | |||
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128 | nb_data_receipt <= 0; | |||
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129 | STATE_CIC_LFR <= INT_0; | |||
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130 | END IF; | |||
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131 | WHEN INT_0 => | |||
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132 | ||||
121 |
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133 | WHEN OTHERS => NULL; | |
122 | END CASE; |
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134 | END CASE; | |
123 | END IF; |
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135 | END IF; |
@@ -608,7 +608,7 BEGIN -- beh | |||||
608 | --26 |
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608 | --26 | |
609 | WHEN "011111" => |
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609 | WHEN "011111" => | |
610 | all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP |
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610 | all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP | |
611 |
reg_wp.status_ready_buffer_f(I) |
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611 | reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2); | |
612 | reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); |
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612 | reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); | |
613 | reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I); |
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613 | reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I); | |
614 | reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I); |
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614 | reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I); |
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