@@ -0,0 +1,74 | |||||
|
1 | #include <stdio.h> | |||
|
2 | #include "lpp_apb_functions.h" | |||
|
3 | #include "apb_fifo_Driver.h" | |||
|
4 | #include "apb_uart_Driver.h" | |||
|
5 | ||||
|
6 | ||||
|
7 | int main() | |||
|
8 | { | |||
|
9 | int i=0; | |||
|
10 | int data; | |||
|
11 | char temp[256]; | |||
|
12 | ||||
|
13 | int TblSinA[256] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255} ; | |||
|
14 | int TblSinAB[256] = {255,254,253,252,251,250,249,248,247,246,245,244,243,242,241,240,239,238,237,236,235,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,218,217,216,215,214,213,212,211,210,209,208,207,206,205,204,203,202,201,200,199,198,197,196,195,194,193,192,191,190,189,188,187,186,185,184,183,182,181,180,179,178,177,176,175,174,173,172,171,170,169,168,167,166,165,164,163,162,161,160,159,158,157,156,155,154,153,152,151,150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135,134,133,132,131,130,129,128,127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112,111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96,95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80,79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0} ; | |||
|
15 | int TblSinB[256] = {100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100} ; | |||
|
16 | int TblSinBC[256] = {128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,255,254,253,252,251,250,249,248,247,246,245,244,243,242,241,240,239,238,237,236,235,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,218,217,216,215,214,213,212,211,210,209,208,207,206,205,204,203,202,201,200,199,198,197,196,195,194,193,192,191,190,189,188,187,186,185,184,183,182,181,180,179,178,177,176,175,174,173,172,171,170,169,168,167,166,165,164,163,162,161,160,159,158,157,156,155,154,153,152,151,150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135,134,133,132,131,130,129} ; | |||
|
17 | int TblSinC[256] = {128,127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112,111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96,95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80,79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127} ; | |||
|
18 | ||||
|
19 | UART_Device* uart0 = openUART(0); | |||
|
20 | FIFO_Device* fifotry = openFIFO(0); | |||
|
21 | FIFO_Device* fifoIn = openFIFO(1); | |||
|
22 | FIFO_Device* fifoOut = openFIFO(2); | |||
|
23 | ||||
|
24 | printf("\nDebut Main\n\n"); | |||
|
25 | ||||
|
26 | FillFifo(fifoIn,0,TblSinA,256); | |||
|
27 | fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); | |||
|
28 | ||||
|
29 | FillFifo(fifoIn,1,TblSinAB,256); | |||
|
30 | fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); | |||
|
31 | ||||
|
32 | FillFifo(fifoIn,2,TblSinB,256); | |||
|
33 | fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); | |||
|
34 | ||||
|
35 | FillFifo(fifoIn,3,TblSinBC,256); | |||
|
36 | fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); | |||
|
37 | ||||
|
38 | FillFifo(fifoIn,4,TblSinC,256); | |||
|
39 | fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); | |||
|
40 | ||||
|
41 | ||||
|
42 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |||
|
43 | printf("\nFull 1\n"); | |||
|
44 | while((fifoOut->FIFOreg[(2*1)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |||
|
45 | printf("\nFull 2\n"); | |||
|
46 | ||||
|
47 | while(1){ | |||
|
48 | ||||
|
49 | sprintf(temp,"PONG A\n\r"); | |||
|
50 | uartputs(uart0,temp); | |||
|
51 | ||||
|
52 | while(i<257){ | |||
|
53 | data = (fifoOut->FIFOreg[(2*0)+FIFO_RWdata]); | |||
|
54 | i++; | |||
|
55 | sprintf(temp,"%d\n\r",data); | |||
|
56 | uartputs(uart0,temp); | |||
|
57 | } | |||
|
58 | ||||
|
59 | i=0; | |||
|
60 | sprintf(temp,"PONG B\n\r"); | |||
|
61 | uartputs(uart0,temp); | |||
|
62 | ||||
|
63 | while(i<257){ | |||
|
64 | data = (fifoOut->FIFOreg[(2*1)+FIFO_RWdata]); | |||
|
65 | i++; | |||
|
66 | sprintf(temp,"%d\n\r",data); | |||
|
67 | uartputs(uart0,temp); | |||
|
68 | } | |||
|
69 | ||||
|
70 | i=0; | |||
|
71 | } | |||
|
72 | printf("\nFin Main\n\n"); | |||
|
73 | return 0; | |||
|
74 | } |
@@ -0,0 +1,198 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | ||||
|
26 | entity TopSpecMatrix is | |||
|
27 | generic( | |||
|
28 | Input_SZ : integer := 16); | |||
|
29 | port( | |||
|
30 | clk : in std_logic; | |||
|
31 | rstn : in std_logic; | |||
|
32 | Write : in std_logic; | |||
|
33 | ReadIn : in std_logic_vector(1 downto 0); | |||
|
34 | Full : in std_logic_vector(4 downto 0); | |||
|
35 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); | |||
|
36 | Start : out std_logic; | |||
|
37 | ReadOut : out std_logic_vector(4 downto 0); | |||
|
38 | Statu : out std_logic_vector(3 downto 0); | |||
|
39 | DATA1 : out std_logic_vector(Input_SZ-1 downto 0); | |||
|
40 | DATA2 : out std_logic_vector(Input_SZ-1 downto 0) | |||
|
41 | ); | |||
|
42 | end entity; | |||
|
43 | ||||
|
44 | architecture ar_TopSpecMatrix of TopSpecMatrix is | |||
|
45 | ||||
|
46 | type etat is (eX,e0,e1,e2); | |||
|
47 | signal ect : etat; | |||
|
48 | ||||
|
49 | signal DataCount : integer range 0 to 256 := 0; | |||
|
50 | signal StatuINT : integer range 1 to 15 := 1; | |||
|
51 | ||||
|
52 | signal Write_reg : std_logic; | |||
|
53 | signal Full_int : std_logic_vector(1 downto 0); | |||
|
54 | ||||
|
55 | begin | |||
|
56 | process(clk,rstn) | |||
|
57 | begin | |||
|
58 | ||||
|
59 | if(rstn='0')then | |||
|
60 | DataCount <= 0; | |||
|
61 | StatuINT <= 1; | |||
|
62 | Write_reg <= '0'; | |||
|
63 | Start <= '0'; | |||
|
64 | ect <= e0; | |||
|
65 | ||||
|
66 | elsif(clk'event and clk='1')then | |||
|
67 | Write_reg <= Write; | |||
|
68 | ||||
|
69 | if(Write_reg='1' and Write='0')then | |||
|
70 | if(DataCount=256)then | |||
|
71 | DataCount <= 0; | |||
|
72 | else | |||
|
73 | DataCount <= DataCount + 1; | |||
|
74 | end if; | |||
|
75 | end if; | |||
|
76 | ||||
|
77 | ||||
|
78 | case ect is | |||
|
79 | ||||
|
80 | when e0 => | |||
|
81 | if(Full_int = "11")then | |||
|
82 | Start <= '1'; | |||
|
83 | if(StatuINT=1 or StatuINT=3 or StatuINT=6 or StatuINT=10 or StatuINT=15)then | |||
|
84 | ect <= e1; | |||
|
85 | else | |||
|
86 | ect <= e2; | |||
|
87 | end if; | |||
|
88 | end if; | |||
|
89 | ||||
|
90 | when e1 => | |||
|
91 | if(DataCount=128)then | |||
|
92 | if(StatuINT=15)then | |||
|
93 | StatuINT <= 1; | |||
|
94 | else | |||
|
95 | StatuINT <= StatuINT + 1; | |||
|
96 | end if; | |||
|
97 | DataCount <= 0; | |||
|
98 | Start <= '0'; | |||
|
99 | ect <= e0; | |||
|
100 | end if; | |||
|
101 | ||||
|
102 | when e2 => | |||
|
103 | if(DataCount=256)then | |||
|
104 | DataCount <= 0; | |||
|
105 | StatuINT <= StatuINT + 1; | |||
|
106 | Start <= '0'; | |||
|
107 | ect <= e0; | |||
|
108 | end if; | |||
|
109 | ||||
|
110 | when others => | |||
|
111 | null; | |||
|
112 | ||||
|
113 | end case; | |||
|
114 | end if; | |||
|
115 | end process; | |||
|
116 | ||||
|
117 | Statu <= std_logic_vector(to_unsigned(StatuINT,4)); | |||
|
118 | ||||
|
119 | with StatuINT select | |||
|
120 | DATA1 <= Data(15 downto 0) when 1, | |||
|
121 | Data(15 downto 0) when 2, | |||
|
122 | Data(31 downto 16) when 3, | |||
|
123 | Data(15 downto 0) when 4, | |||
|
124 | Data(31 downto 16) when 5, | |||
|
125 | Data(47 downto 32) when 6, | |||
|
126 | Data(15 downto 0) when 7, | |||
|
127 | Data(31 downto 16) when 8, | |||
|
128 | Data(47 downto 32) when 9, | |||
|
129 | Data(63 downto 48) when 10, | |||
|
130 | Data(15 downto 0) when 11, | |||
|
131 | Data(31 downto 16) when 12, | |||
|
132 | Data(47 downto 32) when 13, | |||
|
133 | Data(63 downto 48) when 14, | |||
|
134 | Data(79 downto 64) when 15, | |||
|
135 | X"0000" when others; | |||
|
136 | ||||
|
137 | ||||
|
138 | with StatuINT select | |||
|
139 | DATA2 <= (others => '0') when 1, | |||
|
140 | Data(31 downto 16) when 2, | |||
|
141 | (others => '0') when 3, | |||
|
142 | Data(47 downto 32) when 4, | |||
|
143 | Data(47 downto 32) when 5, | |||
|
144 | (others => '0') when 6, | |||
|
145 | Data(63 downto 48) when 7, | |||
|
146 | Data(63 downto 48) when 8, | |||
|
147 | Data(63 downto 48) when 9, | |||
|
148 | (others => '0') when 10, | |||
|
149 | Data(79 downto 64) when 11, | |||
|
150 | Data(79 downto 64) when 12, | |||
|
151 | Data(79 downto 64) when 13, | |||
|
152 | Data(79 downto 64) when 14, | |||
|
153 | (others => '0') when 15, | |||
|
154 | X"0000" when others; | |||
|
155 | ||||
|
156 | with StatuINT select | |||
|
157 | ReadOut <= "1111" & not READin(0) when 1, | |||
|
158 | "111" & not READin(1) & not READin(0) when 2, | |||
|
159 | "111" & not READin(0) & '1' when 3, | |||
|
160 | "11" & not READin(1) & '1' & not READin(0) when 4, | |||
|
161 | "11" & not READin(1) & not READin(0) & '1' when 5, | |||
|
162 | "11" & not READin(0) & "11" when 6, | |||
|
163 | "1" & not READin(1) & "11" & not READin(0) when 7, | |||
|
164 | '1' & not READin(1) & '1' & not READin(0) & '1' when 8, | |||
|
165 | '1' & not READin(1) & not READin(0) & "11" when 9, | |||
|
166 | '1' & not READin(0) & "111" when 10, | |||
|
167 | not READin(1) & "111" & not READin(0) when 11, | |||
|
168 | not READin(1) & "11" & not READin(0) & '1' when 12, | |||
|
169 | not READin(1) & '1' & not READin(0) & "11" when 13, | |||
|
170 | not READin(1) & not READin(0) & "111" when 14, | |||
|
171 | not READin(0) & "1111" when 15, | |||
|
172 | "11111" when others; | |||
|
173 | ||||
|
174 | with StatuINT select | |||
|
175 | Full_int <= Full(0) & Full(0) when 1, | |||
|
176 | Full(1) & Full(0) when 2, | |||
|
177 | Full(1) & Full(1) when 3, | |||
|
178 | Full(2) & Full(0) when 4, | |||
|
179 | Full(2) & Full(1) when 5, | |||
|
180 | Full(2) & Full(2) when 6, | |||
|
181 | Full(3) & Full(0) when 7, | |||
|
182 | Full(3) & Full(1) when 8, | |||
|
183 | Full(3) & Full(2) when 9, | |||
|
184 | Full(3) & Full(3) when 10, | |||
|
185 | Full(4) & Full(0) when 11, | |||
|
186 | Full(4) & Full(1) when 12, | |||
|
187 | Full(4) & Full(2) when 13, | |||
|
188 | Full(4) & Full(3) when 14, | |||
|
189 | Full(4) & Full(4) when 15, | |||
|
190 | "00" when others; | |||
|
191 | ||||
|
192 | end architecture; | |||
|
193 | ||||
|
194 | ||||
|
195 | ||||
|
196 | ||||
|
197 | ||||
|
198 |
@@ -1,80 +1,73 | |||||
1 | #include <stdio.h> |
|
1 | #include <stdio.h> | |
2 | #include "lpp_apb_functions.h" |
|
2 | #include "lpp_apb_functions.h" | |
3 | #include "apb_fifo_Driver.h" |
|
3 | #include "apb_fifo_Driver.h" | |
4 | #include "apb_uart_Driver.h" |
|
4 | #include "apb_uart_Driver.h" | |
5 | #include "apb_delay_Driver.h" |
|
|||
6 | #include "apb_fft_Driver.h" |
|
|||
7 |
|
||||
8 |
|
5 | |||
9 | int main() |
|
6 | int main() | |
10 | { |
|
7 | { | |
11 | int i; |
|
8 | int i=0; | |
12 |
int data |
|
9 | int data; | |
13 | char temp[256]; |
|
10 | char temp[256]; | |
14 | int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; |
|
|||
15 | int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; |
|
|||
16 | int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD} ; |
|
|||
17 |
|
11 | |||
18 | /* int TblSin5K[256] = {0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872,0xD0E1,0xC980,0xC256,0xBB6A,0xB4C3,0xAE69,0xA861,0xA2B1,0x9D60,0x9872,0x93ED,0x8FD5,0x8C2F,0x88FD,0x8644,0x8405,0x8244,0x8102,0x8041,0x8000,0x8041,0x8102,0x8244,0x8405,0x8644,0x88FD,0x8C2F,0x8FD5,0x93ED,0x9872,0x9D60,0xA2B1,0xA861,0xAE69,0xB4C3,0xBB6A,0xC256,0xC980,0xD0E1,0xD872,0xE02B,0xE804,0xEFF5,0xF7F6,0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872,0xD0E1,0xC980,0xC256,0xBB6A,0xB4C3,0xAE69,0xA861,0xA2B1,0x9D60,0x9872,0x93ED,0x8FD5,0x8C2F,0x88FD,0x8644,0x8405,0x8244,0x8102,0x8041,0x8000,0x8041,0x8102,0x8244,0x8405,0x8644,0x88FD,0x8C2F,0x8FD5,0x93ED,0x9872,0x9D60,0xA2B1,0xA861,0xAE69,0xB4C3,0xBB6A,0xC256,0xC980,0xD0E1,0xD872,0xE02B,0xE804,0xEFF5,0xF7F6,0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872}; |
|
12 | int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; | |
19 | int TblSin8K[256] = {0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA,0x489C,0x52D3,0x5C33,0x64A5,0x6C13,0x7269,0x7798,0x7B92,0x7E4C,0x7FBF,0x7FE9,0x7EC7,0x7C5E,0x78B4,0x73D1,0x6DC3,0x669A,0x5E67,0x5540,0x4B3D,0x4077,0x350A,0x2915,0x1CB5,0x100B,0x0337,0xF65C,0xE999,0xDD10,0xD0E1,0xC52C,0xBA10,0xAFA8,0xA610,0x9D60,0x95AF,0x8F11,0x8997,0x854F,0x8244,0x807F,0x8003,0x80D1,0x82E9,0x8644,0x8AD9,0x909E,0x9782,0x9F75,0xA861,0xB22F,0xBCC7,0xC80D,0xD3E3,0xE02B,0xECC5,0xF992,0x066E,0x133B,0x1FD5,0x2C1D,0x37F3,0x4339,0x4DD1,0x579F,0x608B,0x687E,0x6F62,0x7527,0x79BC,0x7D17,0x7F2F,0x7FFD,0x7F81,0x7DBC,0x7AB1,0x7669,0x70EF,0x6A51,0x62A0,0x59F0,0x5058,0x45F0,0x3AD4,0x2F1F,0x22F0,0x1667,0x09A4,0xFCC9,0xEFF5,0xE34B,0xD6EB,0xCAF6,0xBF89,0xB4C3,0xAAC0,0xA199,0x9966,0x923D,0x8C2F,0x874C,0x83A2,0x8139,0x8017,0x8041,0x81B4,0x846E,0x8868,0x8D97,0x93ED,0x9B5B,0xA3CD,0xAD2D,0xB764,0xC256,0xCDE7,0xD9FB,0xE670,0xF327,0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA,0x489C,0x52D3,0x5C33,0x64A5,0x6C13,0x7269,0x7798,0x7B92,0x7E4C,0x7FBF,0x7FE9,0x7EC7,0x7C5E,0x78B4,0x73D1,0x6DC3,0x669A,0x5E67,0x5540,0x4B3D,0x4077,0x350A,0x2915,0x1CB5,0x100B,0x0337,0xF65C,0xE999,0xDD10,0xD0E1,0xC52C,0xBA10,0xAFA8,0xA610,0x9D60,0x95AF,0x8F11,0x8997,0x854F,0x8244,0x807F,0x8003,0x80D1,0x82E9,0x8644,0x8AD9,0x909E,0x9782,0x9F75,0xA861,0xB22F,0xBCC7,0xC80D,0xD3E3,0xE02B,0xECC5,0xF992,0x066E,0x133B,0x1FD5,0x2C1D,0x37F3,0x4339,0x4DD1,0x579F,0x608B,0x687E,0x6F62,0x7527,0x79BC,0x7D17,0x7F2F,0x7FFD,0x7F81,0x7DBC,0x7AB1,0x7669,0x70EF,0x6A51,0x62A0,0x59F0,0x5058,0x45F0,0x3AD4,0x2F1F,0x22F0,0x1667,0x09A4,0xFCC9,0xEFF5,0xE34B,0xD6EB,0xCAF6,0xBF89,0xB4C3,0xAAC0,0xA199,0x9966,0x923D,0x8C2F,0x874C,0x83A2,0x8139,0x8017,0x8041,0x81B4,0x846E,0x8868,0x8D97,0x93ED,0x9B5B,0xA3CD,0xAD2D,0xB764,0xC256,0xCDE7,0xD9FB,0xE670,0xF327,0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA}; |
|
13 | int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD}; | |
20 | int TblSin11K[256] = {0x0000,0x11A3,0x22F0,0x3392,0x4339,0x5197,0x5E67,0x696A,0x7269,0x793B,0x7DBC,0x7FD7,0x7F81,0x7CBD,0x7798,0x702B,0x669A,0x5B14,0x4DD1,0x3F12,0x2F1F,0x1E46,0x0CD9,0xFB2D,0xE999,0xD872,0xC80D,0xB8B8,0xAAC0,0x9E68,0x93ED,0x8B82,0x854F,0x8174,0x8003,0x8102,0x846E,0x8A36,0x923D,0x9C5B,0xA861,0xB612,0xC52C,0xD566,0xE670,0xF7F6,0x09A4,0x1B23,0x2C1D,0x3C40,0x4B3D,0x58CA,0x64A5,0x6E95,0x7669,0x7BFB,0x7F2F,0x7FF6,0x7E4C,0x7A39,0x73D1,0x6B34,0x608B,0x540B,0x45F0,0x3680,0x2605,0x14D1,0x0337,0xF18E,0xE02B,0xCF63,0xBF89,0xB0EA,0xA3CD,0x9872,0x8F11,0x87D8,0x82E9,0x805D,0x8041,0x8294,0x874C,0x8E52,0x9782,0xA2B1,0xAFA8,0xBE27,0xCDE7,0xDE9D,0xEFF5,0x019C,0x133B,0x247C,0x350A,0x4496,0x52D3,0x5F7B,0x6A51,0x7320,0x79BC,0x7E06,0x7FE9,0x7F5B,0x7C5E,0x7703,0x6F62,0x65A1,0x59F0,0x4C88,0x3DAA,0x2D9F,0x1CB5,0x0B3F,0xF992,0xE804,0xD6EB,0xC69B,0xB764,0xA98F,0x9D60,0x9313,0x8AD9,0x84DC,0x8139,0x8000,0x8139,0x84DC,0x8AD9,0x9313,0x9D60,0xA98F,0xB764,0xC69B,0xD6EB,0xE804,0xF992,0x0B3F,0x1CB5,0x2D9F,0x3DAA,0x4C88,0x59F0,0x65A1,0x6F62,0x7703,0x7C5E,0x7F5B,0x7FE9,0x7E06,0x79BC,0x7320,0x6A51,0x5F7B,0x52D3,0x4496,0x350A,0x247C,0x133B,0x019C,0xEFF5,0xDE9D,0xCDE7,0xBE27,0xAFA8,0xA2B1,0x9782,0x8E52,0x874C,0x8294,0x8041,0x805D,0x82E9,0x87D8,0x8F11,0x9872,0xA3CD,0xB0EA,0xBF89,0xCF63,0xE02B,0xF18E,0x0337,0x14D1,0x2605,0x3680,0x45F0,0x540B,0x608B,0x6B34,0x73D1,0x7A39,0x7E4C,0x7FF6,0x7F2F,0x7BFB,0x7669,0x6E95,0x64A5,0x58CA,0x4B3D,0x3C40,0x2C1D,0x1B23,0x09A4,0xF7F6,0xE670,0xD566,0xC52C,0xB612,0xA861,0x9C5B,0x923D,0x8A36,0x846E,0x8102,0x8003,0x8174,0x854F,0x8B82,0x93ED,0x9E68,0xAAC0,0xB8B8,0xC80D,0xD872,0xE999,0xFB2D,0x0CD9,0x1E46,0x2F1F,0x3F12,0x4DD1,0x5B14,0x669A,0x702B,0x7798,0x7CBD,0x7F81,0x7FD7,0x7DBC,0x793B,0x7269,0x696A,0x5E67,0x5197,0x4339,0x3392,0x22F0,0x11A3,0x0000,0xEE5D,0xDD10,0xCC6E,0xBCC7,0xAE69}; |
|
14 | int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; | |
21 | */ int TblSin15K[256] = {0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872,0x8C2F,0x8405,0x8041,0x8102,0x8644,0x8FD5,0x9D60,0xAE69,0xC256,0xD872,0xEFF5,0x080A,0x1FD5,0x3680,0x4B3D,0x5D4F,0x6C13,0x7703,0x7DBC,0x8000,0x7DBC,0x7703,0x6C13,0x5D4F,0x4B3D,0x3680,0x1FD5,0x080A,0xEFF5,0xD872,0xC256,0xAE69,0x9D60,0x8FD5,0x8644,0x8102,0x8041,0x8405,0x8C2F,0x9872,0xA861,0xBB6A,0xD0E1,0xE804,0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872,0x8C2F,0x8405,0x8041,0x8102,0x8644,0x8FD5,0x9D60,0xAE69,0xC256,0xD872,0xEFF5,0x080A,0x1FD5,0x3680,0x4B3D,0x5D4F,0x6C13,0x7703,0x7DBC,0x8000,0x7DBC,0x7703,0x6C13,0x5D4F,0x4B3D,0x3680,0x1FD5,0x080A,0xEFF5,0xD872,0xC256,0xAE69,0x9D60,0x8FD5,0x8644,0x8102,0x8041,0x8405,0x8C2F,0x9872,0xA861,0xBB6A,0xD0E1,0xE804,0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872}; |
|
15 | int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C}; | |
22 | int TblSin19K[256] = {0x0000,0x1E46,0x3AD4,0x540B,0x687E,0x7703,0x7EC7,0x7F5B,0x78B4,0x6B34,0x579F,0x3F12,0x22F0,0x04D3,0xE670,0xC980,0xAFA8,0x9A5F,0x8AD9,0x81FA,0x8041,0x85C7,0x923D,0xA4EC,0xBCC7,0xD872,0xF65C,0x14D1,0x3219,0x4C88,0x62A0,0x7320,0x7D17,0x7FF6,0x7B92,0x702B,0x5E67,0x4748,0x2C1D,0x0E72,0xEFF5,0xD261,0xB764,0xA085,0x8F11,0x8405,0x8003,0x8343,0x8D97,0x9E68,0xB4C3,0xCF63,0xECC5,0x0B3F,0x2915,0x4496,0x5C33,0x6E95,0x7AB1,0x7FD7,0x7DBC,0x747E,0x64A5,0x4F16,0x350A,0x17FC,0xF992,0xDB84,0xBF89,0xA736,0x93ED,0x86C5,0x807F,0x8174,0x8997,0x9872,0xAD2D,0xC69B,0xE34B,0x019C,0x1FD5,0x3C40,0x5540,0x696A,0x7798,0x7EFE,0x7F2F,0x7828,0x6A51,0x5671,0x3DAA,0x2163,0x0337,0xE4DD,0xC80D,0xAE69,0x9966,0x8A36,0x81B4,0x805D,0x8644,0x9313,0xA610,0xBE27,0xD9FB,0xF7F6,0x1667,0x3392,0x4DD1,0x63A5,0x73D1,0x7D6C,0x7FE9,0x7B24,0x6F62,0x5D4F,0x45F0,0x2A9A,0x0CD9,0xEE5D,0xD0E1,0xB612,0x9F75,0x8E52,0x83A2,0x8000,0x83A2,0x8E52,0x9F75,0xB612,0xD0E1,0xEE5D,0x0CD9,0x2A9A,0x45F0,0x5D4F,0x6F62,0x7B24,0x7FE9,0x7D6C,0x73D1,0x63A5,0x4DD1,0x3392,0x1667,0xF7F6,0xD9FB,0xBE27,0xA610,0x9313,0x8644,0x805D,0x81B4,0x8A36,0x9966,0xAE69,0xC80D,0xE4DD,0x0337,0x2163,0x3DAA,0x5671,0x6A51,0x7828,0x7F2F,0x7EFE,0x7798,0x696A,0x5540,0x3C40,0x1FD5,0x019C,0xE34B,0xC69B,0xAD2D,0x9872,0x8997,0x8174,0x807F,0x86C5,0x93ED,0xA736,0xBF89,0xDB84,0xF992,0x17FC,0x350A,0x4F16,0x64A5,0x747E,0x7DBC,0x7FD7,0x7AB1,0x6E95,0x5C33,0x4496,0x2915,0x0B3F,0xECC5,0xCF63,0xB4C3,0x9E68,0x8D97,0x8343,0x8003,0x8405,0x8F11,0xA085,0xB764,0xD261,0xEFF5,0x0E72,0x2C1D,0x4748,0x5E67,0x702B,0x7B92,0x7FF6,0x7D17,0x7320,0x62A0,0x4C88,0x3219,0x14D1,0xF65C,0xD872,0xBCC7,0xA4EC,0x923D,0x85C7,0x8041,0x81FA,0x8AD9,0x9A5F,0xAFA8,0xC980,0xE670,0x04D3,0x22F0,0x3F12,0x579F,0x6B34,0x78B4,0x7F5B,0x7EC7,0x7703,0x687E,0x540B,0x3AD4,0x1E46,0x0000,0xE1BA,0xC52C,0xABF5,0x9782,0x88FD}; |
|
16 | int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E}; | |
23 | int Table[256]; |
|
|||
24 |
|
17 | |||
25 | FFT_Device* fft0 = openFFT(0); |
|
|||
26 | DELAY_Device* delay = openDELAY(0); |
|
|||
27 |
UART_Device* uart0 |
|
18 | UART_Device* uart0 = openUART(0); | |
28 |
FIFO_Device* fifo |
|
19 | FIFO_Device* fifotry = openFIFO(0); | |
29 |
FIFO_Device* fifo |
|
20 | FIFO_Device* fifoIn = openFIFO(1); | |
|
21 | FIFO_Device* fifoOut = openFIFO(2); | |||
30 |
|
22 | |||
31 | printf("\nDebut Main\n\n"); |
|
23 | printf("\nDebut Main\n\n"); | |
32 |
|
24 | |||
33 | Setup(delay,30000000); |
|
25 | FillFifo(fifoIn,0,TblSinA,256); | |
34 |
|
||||
35 | FftInput(TblSinA,fft0,delay); |
|
|||
36 | FftOutput(Table,fft0); |
|
|||
37 | /*for (i = 0 ; i < 256 ; i=i+2) |
|
|||
38 | { |
|
|||
39 | sprintf(temp,"%x\t%x\n\r",Table[i],Table[i+1]); |
|
|||
40 | uartputs(uart0,temp); |
|
|||
41 | }*/ |
|
|||
42 | FillFifo(fifoIn,0,Table); |
|
|||
43 | fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); |
|
26 | fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); | |
44 |
|
27 | |||
45 | FftInput(TblSinAB,fft0,delay); |
|
28 | FillFifo(fifoIn,1,TblSinAB,256); | |
46 | FftOutput(Table,fft0); |
|
|||
47 | FillFifo(fifoIn,1,Table); |
|
|||
48 | fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); |
|
29 | fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); | |
49 |
|
30 | |||
50 | FftInput(TblSinB,fft0,delay); |
|
31 | FillFifo(fifoIn,2,TblSinB,256); | |
51 | FftOutput(Table,fft0); |
|
|||
52 | FillFifo(fifoIn,2,Table); |
|
|||
53 | fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); |
|
32 | fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); | |
54 |
|
33 | |||
55 | FftInput(TblSin15K,fft0,delay); |
|
34 | FillFifo(fifoIn,3,TblSinBC,256); | |
56 | FftOutput(Table,fft0); |
|
|||
57 | FillFifo(fifoIn,3,Table); |
|
|||
58 | fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); |
|
35 | fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); | |
59 |
|
36 | |||
60 | FftInput(TblSin19K,fft0,delay); |
|
37 | FillFifo(fifoIn,4,TblSinC,256); | |
61 | FftOutput(Table,fft0); |
|
|||
62 | FillFifo(fifoIn,4,Table); |
|
|||
63 | fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); |
|
38 | fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); | |
64 | printf("ok"); |
|
39 | ||
|
40 | ||||
|
41 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |||
|
42 | printf("\nFull 1\n"); | |||
|
43 | while((fifoOut->FIFOreg[(2*1)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |||
|
44 | printf("\nFull 2\n"); | |||
|
45 | ||||
65 | while(1){ |
|
46 | while(1){ | |
66 |
|
47 | |||
67 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN |
|
48 | sprintf(temp,"PONG A\n\r"); | |
|
49 | uartputs(uart0,temp); | |||
|
50 | ||||
|
51 | while(i<257){ | |||
|
52 | data = (fifoOut->FIFOreg[(2*0)+FIFO_RWdata]); | |||
|
53 | i++; | |||
|
54 | sprintf(temp,"%d\n\r",data); | |||
|
55 | uartputs(uart0,temp); | |||
|
56 | } | |||
68 |
|
57 | |||
69 | data1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
|
58 | i=0; | |
70 | data2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
|
59 | sprintf(temp,"PONG B\n\r"); | |
|
60 | uartputs(uart0,temp); | |||
71 |
|
61 | |||
72 | sprintf(temp,"%d\t%d\n\r",data1,data2); |
|
62 | while(i<257){ | |
|
63 | data = (fifoOut->FIFOreg[(2*1)+FIFO_RWdata]); | |||
|
64 | i++; | |||
|
65 | sprintf(temp,"%d\n\r",data); | |||
73 | uartputs(uart0,temp); |
|
66 | uartputs(uart0,temp); | |
74 | } |
|
67 | } | |
|
68 | ||||
|
69 | i=0; | |||
|
70 | } | |||
75 | printf("\nFin Main\n\n"); |
|
71 | printf("\nFin Main\n\n"); | |
76 | return 0; |
|
72 | return 0; | |
77 | } |
|
73 | } | |
78 |
|
||||
79 |
|
||||
80 |
|
@@ -1,44 +1,44 | |||||
1 | #------------------------------------------------------------------------------ |
|
1 | #------------------------------------------------------------------------------ | |
2 | #-- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | #-- This file is a part of the LPP VHDL IP LIBRARY | |
3 | #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS | |
4 | #-- |
|
4 | #-- | |
5 | #-- This program is free software; you can redistribute it and/or modify |
|
5 | #-- This program is free software; you can redistribute it and/or modify | |
6 | #-- it under the terms of the GNU General Public License as published by |
|
6 | #-- it under the terms of the GNU General Public License as published by | |
7 | #-- the Free Software Foundation; either version 3 of the License, or |
|
7 | #-- the Free Software Foundation; either version 3 of the License, or | |
8 | #-- (at your option) any later version. |
|
8 | #-- (at your option) any later version. | |
9 | #-- |
|
9 | #-- | |
10 | #-- This program is distributed in the hope that it will be useful, |
|
10 | #-- This program is distributed in the hope that it will be useful, | |
11 | #-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | #-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | #-- GNU General Public License for more details. |
|
13 | #-- GNU General Public License for more details. | |
14 | #-- |
|
14 | #-- | |
15 | #-- You should have received a copy of the GNU General Public License |
|
15 | #-- You should have received a copy of the GNU General Public License | |
16 | #-- along with this program; if not, write to the Free Software |
|
16 | #-- along with this program; if not, write to the Free Software | |
17 | #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | #------------------------------------------------------------------------------ |
|
18 | #------------------------------------------------------------------------------ | |
19 |
|
19 | |||
20 | include ../../rules.mk |
|
20 | include ../../rules.mk | |
21 | LIBDIR = ../../lib |
|
21 | LIBDIR = ../../lib | |
22 | INCPATH = ../../includes |
|
22 | INCPATH = ../../includes | |
23 | SCRIPTDIR=../../scripts/ |
|
23 | SCRIPTDIR=../../scripts/ | |
24 |
LIBS=-lapb_fft_Driver -llpp_apb_functions |
|
24 | LIBS=-lapb_fifo_Driver -lapb_uart_Driver -llpp_apb_functions | |
25 | INPUTFILE=main.c |
|
25 | INPUTFILE=main.c | |
26 | EXEC=BenchFFT.bin |
|
26 | EXEC=BenchFFT.bin | |
27 | OUTBINDIR=bin/ |
|
27 | OUTBINDIR=bin/ | |
28 |
|
28 | |||
29 |
|
29 | |||
30 | .PHONY:bin |
|
30 | .PHONY:bin | |
31 |
|
31 | |||
32 | all:bin |
|
32 | all:bin | |
33 | @echo $(EXEC)" file created" |
|
33 | @echo $(EXEC)" file created" | |
34 |
|
34 | |||
35 | clean: |
|
35 | clean: | |
36 | rm -f *.{o,a} |
|
36 | rm -f *.{o,a} | |
37 |
|
37 | |||
38 |
|
38 | |||
39 |
|
39 | |||
40 | help:ruleshelp |
|
40 | help:ruleshelp | |
41 | @echo " all : makes an executable file called "$(EXEC) |
|
41 | @echo " all : makes an executable file called "$(EXEC) | |
42 | @echo " in "$(OUTBINDIR) |
|
42 | @echo " in "$(OUTBINDIR) | |
43 | @echo " clean : removes temporary files" |
|
43 | @echo " clean : removes temporary files" | |
44 |
|
44 |
@@ -1,51 +1,51 | |||||
1 | #include <stdio.h> |
|
1 | #include <stdio.h> | |
2 | #include "lpp_apb_functions.h" |
|
2 | #include "lpp_apb_functions.h" | |
3 | #include "apb_fifo_Driver.h" |
|
3 | #include "apb_fifo_Driver.h" | |
4 | #include "apb_uart_Driver.h" |
|
4 | #include "apb_uart_Driver.h" | |
5 | #include "TableTest.h" |
|
5 | //#include "TableTest.h" | |
6 |
|
6 | |||
7 |
|
7 | |||
8 | int main() |
|
8 | int main() | |
9 | { |
|
9 | { | |
10 | int i=0,j=0; |
|
10 | int i=0,j=0; | |
11 | int data1,data2; |
|
11 | int data1,data2; | |
12 | char temp[256]; |
|
12 | char temp[256]; | |
13 |
|
13 | |||
14 | int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; |
|
14 | int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; | |
15 | int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD}; |
|
15 | int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD}; | |
16 | int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; |
|
16 | int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; | |
17 | int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C}; |
|
17 | int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C}; | |
18 | int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E}; |
|
18 | int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E}; | |
19 |
|
19 | |||
20 | UART_Device* uart0 = openUART(0); |
|
20 | UART_Device* uart0 = openUART(0); | |
21 | FIFO_Device* fifotry = openFIFO(0); |
|
21 | FIFO_Device* fifotry = openFIFO(0); | |
22 | FIFO_Device* fifoIn = openFIFO(1); |
|
22 | FIFO_Device* fifoIn = openFIFO(1); | |
23 | FIFO_Device* fifoOut = openFIFO(2); |
|
23 | FIFO_Device* fifoOut = openFIFO(2); | |
24 |
|
24 | |||
25 | printf("\nDebut Main\n\n"); |
|
25 | printf("\nDebut Main\n\n"); | |
26 |
|
26 | |||
27 | FillFifo(fifoIn,0,TblSinA,256); |
|
27 | FillFifo(fifoIn,0,TblSinA,256); | |
28 | FillFifo(fifoIn,1,TblSinAB,256); |
|
28 | FillFifo(fifoIn,1,TblSinAB,256); | |
29 | FillFifo(fifoIn,2,TblSinB,256); |
|
29 | FillFifo(fifoIn,2,TblSinB,256); | |
30 | FillFifo(fifoIn,3,TblSinBC,256); |
|
30 | FillFifo(fifoIn,3,TblSinBC,256); | |
31 | FillFifo(fifoIn,4,TblSinC,256); |
|
31 | FillFifo(fifoIn,4,TblSinC,256); | |
32 |
|
32 | |||
33 | while(j<5){ |
|
33 | while(j<5){ | |
34 | while((fifoOut->FIFOreg[(2*j)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN |
|
34 | while((fifoOut->FIFOreg[(2*j)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |
35 |
|
35 | |||
36 | sprintf(temp,"FIFO %d\n\r",j); |
|
36 | sprintf(temp,"FIFO %d\n\r",j); | |
37 | uartputs(uart0,temp); |
|
37 | uartputs(uart0,temp); | |
38 | //while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty){ // TANT QUE empty a 0 ALORS |
|
38 | //while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty){ // TANT QUE empty a 0 ALORS | |
39 | while(i < 128){ |
|
39 | while(i < 128){ | |
40 | data1 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex; |
|
40 | data1 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex; | |
41 | data2 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex; |
|
41 | data2 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex; | |
42 | i++; |
|
42 | i++; | |
43 | sprintf(temp,"%d\t%d\n\r",data1,data2); |
|
43 | sprintf(temp,"%d\t%d\n\r",data1,data2); | |
44 | uartputs(uart0,temp); |
|
44 | uartputs(uart0,temp); | |
45 | } |
|
45 | } | |
46 | i=0; |
|
46 | i=0; | |
47 | j++; |
|
47 | j++; | |
48 | } |
|
48 | } | |
49 | printf("\nFin Main\n\n"); |
|
49 | printf("\nFin Main\n\n"); | |
50 | return 0; |
|
50 | return 0; | |
51 | } |
|
51 | } |
@@ -1,174 +1,174 | |||||
1 | #include <stdio.h> |
|
1 | #include <stdio.h> | |
2 | #include "lpp_apb_functions.h" |
|
2 | #include "lpp_apb_functions.h" | |
3 | #include "apb_fifo_Driver.h" |
|
3 | #include "apb_fifo_Driver.h" | |
4 | #include "apb_Matrix_Driver.h" |
|
4 | #include "apb_Matrix_Driver.h" | |
5 | #include "apb_uart_Driver.h" |
|
5 | #include "apb_uart_Driver.h" | |
6 | #include "apb_gpio_Driver.h" |
|
6 | #include "apb_gpio_Driver.h" | |
7 |
|
7 | |||
8 | ///////////// Matrix With 2 FIFO Input ///////////////////////////////////////////// |
|
8 | ///////////// Matrix With 2 FIFO Input ///////////////////////////////////////////// | |
9 | int main() |
|
9 | int main() | |
10 | { |
|
10 | { | |
11 | int i=0,save; |
|
11 | int i=0,save; | |
12 | char temp[256]; |
|
12 | char temp[256]; | |
13 | int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; |
|
13 | int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; | |
14 | int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; |
|
14 | int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; | |
15 | int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; |
|
15 | int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; | |
16 | // int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; |
|
16 | // int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; | |
17 | // int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; |
|
17 | // int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; | |
18 | int Table[256]; |
|
18 | int Table[256]; | |
19 |
|
19 | |||
20 |
|
20 | |||
21 | FIFO_Device* fifoX = openFIFO(0); |
|
21 | FIFO_Device* fifoX = openFIFO(0); | |
22 | UART_Device* uart0 = openUART(0); |
|
22 | UART_Device* uart0 = openUART(0); | |
23 | FIFO_Device* fifoIn = openFIFO(1); |
|
23 | FIFO_Device* fifoIn = openFIFO(1); | |
24 | MATRIX_Device* mspec = openMatrix(0); |
|
24 | MATRIX_Device* mspec = openMatrix(0); | |
25 | FIFO_Device* fifoOut = openFIFO(2); |
|
25 | FIFO_Device* fifoOut = openFIFO(2); | |
26 | GPIO_Device* gpio0 = openGPIO(0); |
|
26 | GPIO_Device* gpio0 = openGPIO(0); | |
27 |
|
27 | |||
28 | printf("\nDebut Main\n\n"); |
|
28 | printf("\nDebut Main\n\n"); | |
29 |
|
29 | |||
30 | gpio0->oen = 0x3; |
|
30 | gpio0->oen = 0x3; | |
31 | gpio0->Dout = 0x0; |
|
31 | gpio0->Dout = 0x0; | |
32 |
|
32 | |||
33 | /////////////////////////////////////////////////////////////////////////// |
|
33 | /////////////////////////////////////////////////////////////////////////// | |
34 | mspec->Statu = 2; |
|
34 | mspec->Statu = 2; | |
35 | FillFifo(fifoIn,0,TblB1); |
|
35 | FillFifo(fifoIn,0,TblB1,256); | |
36 | FillFifo(fifoIn,1,TblB2); |
|
36 | FillFifo(fifoIn,1,TblB2,256); | |
37 | gpio0->Dout = 0x1; |
|
37 | gpio0->Dout = 0x1; | |
38 |
|
38 | |||
39 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS |
|
39 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS | |
40 | { |
|
40 | { | |
41 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
|
41 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |
42 | i++; |
|
42 | i++; | |
43 | } |
|
43 | } | |
44 | save = i; |
|
44 | save = i; | |
45 | gpio0->Dout = 0x2; |
|
45 | gpio0->Dout = 0x2; | |
46 |
|
46 | |||
47 | sprintf(temp,"\nReels\tImaginaires\n\r"); |
|
47 | sprintf(temp,"\nReels\tImaginaires\n\r"); | |
48 | uartputs(uart0,temp); |
|
48 | uartputs(uart0,temp); | |
49 | for (i = 0 ; i < save ; i+=2) |
|
49 | for (i = 0 ; i < save ; i+=2) | |
50 | { |
|
50 | { | |
51 | sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); |
|
51 | sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); | |
52 | uartputs(uart0,temp); |
|
52 | uartputs(uart0,temp); | |
53 | } |
|
53 | } | |
54 | i = 0; |
|
54 | i = 0; | |
55 | gpio0->Dout = 0x0; |
|
55 | gpio0->Dout = 0x0; | |
56 |
|
56 | |||
57 | /////////////////////////////////////////////////////////////////////////// |
|
57 | /////////////////////////////////////////////////////////////////////////// | |
58 | mspec->Statu = 1; |
|
58 | mspec->Statu = 1; | |
59 | FillFifo(fifoIn,0,TblB1); |
|
59 | FillFifo(fifoIn,0,TblB1,256); | |
60 | gpio0->Dout = 0x1; |
|
60 | gpio0->Dout = 0x1; | |
61 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS |
|
61 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS | |
62 | { |
|
62 | { | |
63 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
|
63 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |
64 | i++; |
|
64 | i++; | |
65 | } |
|
65 | } | |
66 | save = i; |
|
66 | save = i; | |
67 | gpio0->Dout = 0x2; |
|
67 | gpio0->Dout = 0x2; | |
68 |
|
68 | |||
69 | sprintf(temp,"\nReels\n\r"); |
|
69 | sprintf(temp,"\nReels\n\r"); | |
70 | uartputs(uart0,temp); |
|
70 | uartputs(uart0,temp); | |
71 | for (i = 0 ; i < save ; i++) |
|
71 | for (i = 0 ; i < save ; i++) | |
72 | { |
|
72 | { | |
73 | sprintf(temp,"%d\n\r",Table[i]); |
|
73 | sprintf(temp,"%d\n\r",Table[i]); | |
74 | uartputs(uart0,temp); |
|
74 | uartputs(uart0,temp); | |
75 | } |
|
75 | } | |
76 | i = 0; |
|
76 | i = 0; | |
77 | gpio0->Dout = 0x0; |
|
77 | gpio0->Dout = 0x0; | |
78 |
|
78 | |||
79 | /////////////////////////////////////////////////////////////////////////// |
|
79 | /////////////////////////////////////////////////////////////////////////// | |
80 | mspec->Statu = 4; |
|
80 | mspec->Statu = 4; | |
81 | FillFifo(fifoIn,0,TblB1); |
|
81 | FillFifo(fifoIn,0,TblB1,256); | |
82 | FillFifo(fifoIn,1,TblB3); |
|
82 | FillFifo(fifoIn,1,TblB3,256); | |
83 | gpio0->Dout = 0x1; |
|
83 | gpio0->Dout = 0x1; | |
84 |
|
84 | |||
85 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS |
|
85 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS | |
86 | { |
|
86 | { | |
87 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
|
87 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |
88 | i++; |
|
88 | i++; | |
89 | } |
|
89 | } | |
90 | save = i; |
|
90 | save = i; | |
91 | gpio0->Dout = 0x2; |
|
91 | gpio0->Dout = 0x2; | |
92 |
|
92 | |||
93 | sprintf(temp,"\nReels\tImaginaires\n\r"); |
|
93 | sprintf(temp,"\nReels\tImaginaires\n\r"); | |
94 | uartputs(uart0,temp); |
|
94 | uartputs(uart0,temp); | |
95 | for (i = 0 ; i < save ; i+=2) |
|
95 | for (i = 0 ; i < save ; i+=2) | |
96 | { |
|
96 | { | |
97 | sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); |
|
97 | sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); | |
98 | uartputs(uart0,temp); |
|
98 | uartputs(uart0,temp); | |
99 | } |
|
99 | } | |
100 | i = 0; |
|
100 | i = 0; | |
101 | gpio0->Dout = 0x0; |
|
101 | gpio0->Dout = 0x0; | |
102 |
|
102 | |||
103 | printf("\nFin Main\n\n"); |
|
103 | printf("\nFin Main\n\n"); | |
104 | return 0; |
|
104 | return 0; | |
105 | } |
|
105 | } | |
106 |
|
106 | |||
107 |
|
107 | |||
108 | ///////////// Matrix With 5 FIFO Input ///////////////////////////////////////////// |
|
108 | ///////////// Matrix With 5 FIFO Input ///////////////////////////////////////////// | |
109 | int main2() |
|
109 | int main2() | |
110 | { |
|
110 | { | |
111 | int save1,save2; |
|
111 | int save1,save2; | |
112 | char temp[256]; |
|
112 | char temp[256]; | |
113 | int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; |
|
113 | int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; | |
114 | int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; |
|
114 | int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; | |
115 | int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; |
|
115 | int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; | |
116 | int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; |
|
116 | int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; | |
117 | int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; |
|
117 | int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; | |
118 |
|
118 | |||
119 | FIFO_Device* fifoX = openFIFO(0); |
|
119 | FIFO_Device* fifoX = openFIFO(0); | |
120 | UART_Device* uart0 = openUART(0); |
|
120 | UART_Device* uart0 = openUART(0); | |
121 | FIFO_Device* fifoIn = openFIFO(1); |
|
121 | FIFO_Device* fifoIn = openFIFO(1); | |
122 | FIFO_Device* fifoOut = openFIFO(2); |
|
122 | FIFO_Device* fifoOut = openFIFO(2); | |
123 |
|
123 | |||
124 | printf("\nDebut Main\n\n"); |
|
124 | printf("\nDebut Main\n\n"); | |
125 |
|
125 | |||
126 | FillFifo(fifoIn,0,TblB1); |
|
126 | FillFifo(fifoIn,0,TblB1,256); | |
127 | fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); |
|
127 | fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); | |
128 |
|
128 | |||
129 | FillFifo(fifoIn,1,TblB2); |
|
129 | FillFifo(fifoIn,1,TblB2,256); | |
130 | fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); |
|
130 | fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); | |
131 |
|
131 | |||
132 | FillFifo(fifoIn,2,TblB3); |
|
132 | FillFifo(fifoIn,2,TblB3,256); | |
133 | fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); |
|
133 | fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); | |
134 |
|
134 | |||
135 | FillFifo(fifoIn,3,TblE1); |
|
135 | FillFifo(fifoIn,3,TblE1,256); | |
136 | fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); |
|
136 | fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); | |
137 |
|
137 | |||
138 | FillFifo(fifoIn,4,TblE2); |
|
138 | FillFifo(fifoIn,4,TblE2,256); | |
139 |
|
139 | |||
140 | fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); |
|
140 | fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); | |
141 |
|
141 | |||
142 | while(1){ |
|
142 | while(1){ | |
143 |
|
143 | |||
144 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN |
|
144 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN | |
145 |
|
145 | |||
146 | save1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
|
146 | save1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |
147 | save2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
|
147 | save2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |
148 |
|
148 | |||
149 | sprintf(temp,"%d\t%d\n\r",save1,save2); |
|
149 | sprintf(temp,"%d\t%d\n\r",save1,save2); | |
150 | uartputs(uart0,temp); |
|
150 | uartputs(uart0,temp); | |
151 | } |
|
151 | } | |
152 | printf("\nFin Main\n\n"); |
|
152 | printf("\nFin Main\n\n"); | |
153 | return 0; |
|
153 | return 0; | |
154 | } |
|
154 | } | |
155 |
|
155 | |||
156 |
|
156 | |||
157 |
|
157 | |||
158 |
|
158 | |||
159 | /////////////////// Test R/W Fifo OKAI /////////////////////////////////// |
|
159 | /////////////////// Test R/W Fifo OKAI /////////////////////////////////// | |
160 |
|
160 | |||
161 | /*fifoX->FIFOreg[(2*0)+FIFO_RWdata] = 0x11; |
|
161 | /*fifoX->FIFOreg[(2*0)+FIFO_RWdata] = 0x11; | |
162 | Table[1] = fifoX->FIFOreg[(2*0)+FIFO_RWdata]; |
|
162 | Table[1] = fifoX->FIFOreg[(2*0)+FIFO_RWdata]; | |
163 | printf("data: %x\n",Table[1]); |
|
163 | printf("data: %x\n",Table[1]); | |
164 |
|
164 | |||
165 | FillFifo(fifoX,0,TblX); |
|
165 | FillFifo(fifoX,0,TblX); | |
166 | for (i = 1 ; i < 8 ; i++) |
|
166 | for (i = 1 ; i < 8 ; i++) | |
167 | { |
|
167 | { | |
168 | Table[i] = fifoX->FIFOreg[(2*0)+FIFO_RWdata] & Mask_2hex; |
|
168 | Table[i] = fifoX->FIFOreg[(2*0)+FIFO_RWdata] & Mask_2hex; | |
169 | } |
|
169 | } | |
170 | printf("data: %x\n",Table[1]); |
|
170 | printf("data: %x\n",Table[1]); | |
171 | printf("data: %x\n",Table[2]); |
|
171 | printf("data: %x\n",Table[2]); | |
172 | printf("data: %x\n",Table[3]); |
|
172 | printf("data: %x\n",Table[3]); | |
173 | printf("data: %x\n",Table[4]);*/ |
|
173 | printf("data: %x\n",Table[4]);*/ | |
174 |
|
174 |
@@ -1,76 +1,76 | |||||
1 | /*------------------------------------------------------------------------------ |
|
1 | /*------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | -----------------------------------------------------------------------------*/ |
|
21 | -----------------------------------------------------------------------------*/ | |
22 | #ifndef APB_FIFO_DRIVER_H |
|
22 | #ifndef APB_FIFO_DRIVER_H | |
23 | #define APB_FIFO_DRIVER_H |
|
23 | #define APB_FIFO_DRIVER_H | |
24 |
|
24 | |||
25 | /*! \file apb_fifo_Driver.h |
|
25 | /*! \file apb_fifo_Driver.h | |
26 | \brief LPP FIFO driver. |
|
26 | \brief LPP FIFO driver. | |
27 |
|
27 | |||
28 | This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, |
|
28 | This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, | |
29 | used in many type of application. |
|
29 | used in many type of application. | |
30 |
|
30 | |||
31 | \todo Check "DEVICE1 => count = 2" function Open |
|
31 | \todo Check "DEVICE1 => count = 2" function Open | |
32 | \author Martin Morlot martin.morlot@lpp.polytechnique.fr |
|
32 | \author Martin Morlot martin.morlot@lpp.polytechnique.fr | |
33 | */ |
|
33 | */ | |
34 | #define FIFO_Ctrl 0 |
|
34 | #define FIFO_Ctrl 0 | |
35 | #define FIFO_RWdata 1 |
|
35 | #define FIFO_RWdata 1 | |
36 |
|
36 | |||
37 | #define FIFO_Full 0x00010000 |
|
37 | #define FIFO_Full 0x00010000 | |
38 | #define FIFO_Empty 0x00000001 |
|
38 | #define FIFO_Empty 0x00000001 | |
39 | #define FIFO_ReUse 0x00000002 |
|
39 | #define FIFO_ReUse 0x00000002 | |
40 |
|
40 | |||
41 | #define Mask_2hex 0x000000FF |
|
41 | #define Mask_2hex 0x000000FF | |
42 | #define Mask_4hex 0x0000FFFF |
|
42 | #define Mask_4hex 0x0000FFFF | |
43 |
|
43 | |||
44 |
|
44 | |||
45 | /*=================================================== |
|
45 | /*=================================================== | |
46 | T Y P E S D E F |
|
46 | T Y P E S D E F | |
47 | ====================================================*/ |
|
47 | ====================================================*/ | |
48 |
|
48 | |||
49 | /*! \struct APB_FIFO_REG |
|
49 | /*! \struct APB_FIFO_REG | |
50 | \brief Sturcture representing the fifo registers |
|
50 | \brief Sturcture representing the fifo registers | |
51 | */ |
|
51 | */ | |
52 | struct APB_FIFO_REG |
|
52 | struct APB_FIFO_REG | |
53 | { |
|
53 | { | |
54 | int IDreg; |
|
54 | volatile int IDreg; | |
55 | int FIFOreg[2*8]; |
|
55 | volatile int FIFOreg[2*8]; | |
56 | }; |
|
56 | }; | |
57 |
|
57 | |||
58 | typedef volatile struct APB_FIFO_REG FIFO_Device; |
|
58 | typedef volatile struct APB_FIFO_REG FIFO_Device; | |
59 |
|
59 | |||
60 | /*=================================================== |
|
60 | /*=================================================== | |
61 | F U N C T I O N S |
|
61 | F U N C T I O N S | |
62 | ====================================================*/ |
|
62 | ====================================================*/ | |
63 |
|
63 | |||
64 | /*! \fn APB_FIFO_Device* apbfifoOpen(int count); |
|
64 | /*! \fn APB_FIFO_Device* apbfifoOpen(int count); | |
65 | \brief Return count FIFO. |
|
65 | \brief Return count FIFO. | |
66 |
|
66 | |||
67 | This Function scans APB devices table and returns count FIFO. |
|
67 | This Function scans APB devices table and returns count FIFO. | |
68 |
|
68 | |||
69 | \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want |
|
69 | \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want | |
70 | to use FIFO1 so count = 1. |
|
70 | to use FIFO1 so count = 1. | |
71 | \return The pointer to the device. |
|
71 | \return The pointer to the device. | |
72 | */ |
|
72 | */ | |
73 | FIFO_Device* openFIFO(int count); |
|
73 | FIFO_Device* openFIFO(int count); | |
74 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[]); |
|
74 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count); | |
75 |
|
75 | |||
76 | #endif |
|
76 | #endif |
@@ -1,44 +1,53 | |||||
1 | /*------------------------------------------------------------------------------ |
|
1 | /*------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | -----------------------------------------------------------------------------*/ |
|
21 | -----------------------------------------------------------------------------*/ | |
22 | #include "lpp_apb_functions.h" |
|
22 | #include "lpp_apb_functions.h" | |
23 | #include "apb_fifo_Driver.h" |
|
23 | #include "apb_fifo_Driver.h" | |
24 | #include <stdio.h> |
|
24 | #include <stdio.h> | |
25 |
|
25 | |||
26 |
|
26 | |||
27 | FIFO_Device* openFIFO(int count) |
|
27 | FIFO_Device* openFIFO(int count) | |
28 | { |
|
28 | { | |
29 | FIFO_Device* fifo0; |
|
29 | FIFO_Device* fifo0; | |
30 | fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count); |
|
30 | fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count); | |
31 | return fifo0; |
|
31 | return fifo0; | |
32 | } |
|
32 | } | |
33 |
|
33 | |||
34 |
|
34 | |||
35 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[]) |
|
35 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count) | |
36 | { |
|
36 | { | |
37 | int i=0; |
|
37 | int i=0; | |
38 | while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full) // TANT QUE full a 0 ALORS |
|
38 | //int poub; | |
|
39 | //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]); | |||
|
40 | while(i<count) | |||
|
41 | //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE full a 0 ALORS | |||
39 | { |
|
42 | { | |
|
43 | //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]); | |||
|
44 | //printf("%d\n",i); | |||
40 | dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[i]; |
|
45 | dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[i]; | |
41 | i++; |
|
46 | i++; | |
42 | } |
|
47 | } | |
|
48 | //poub = dev->FIFOreg[(2*ID)+FIFO_RWdata]; | |||
|
49 | //dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[0]; | |||
|
50 | //printf("END:%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]); | |||
|
51 | //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |||
43 | return 0; |
|
52 | return 0; | |
44 | } |
|
53 | } |
@@ -1,76 +1,76 | |||||
1 | /*------------------------------------------------------------------------------ |
|
1 | /*------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | -----------------------------------------------------------------------------*/ |
|
21 | -----------------------------------------------------------------------------*/ | |
22 | #ifndef APB_FIFO_DRIVER_H |
|
22 | #ifndef APB_FIFO_DRIVER_H | |
23 | #define APB_FIFO_DRIVER_H |
|
23 | #define APB_FIFO_DRIVER_H | |
24 |
|
24 | |||
25 | /*! \file apb_fifo_Driver.h |
|
25 | /*! \file apb_fifo_Driver.h | |
26 | \brief LPP FIFO driver. |
|
26 | \brief LPP FIFO driver. | |
27 |
|
27 | |||
28 | This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, |
|
28 | This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, | |
29 | used in many type of application. |
|
29 | used in many type of application. | |
30 |
|
30 | |||
31 | \todo Check "DEVICE1 => count = 2" function Open |
|
31 | \todo Check "DEVICE1 => count = 2" function Open | |
32 | \author Martin Morlot martin.morlot@lpp.polytechnique.fr |
|
32 | \author Martin Morlot martin.morlot@lpp.polytechnique.fr | |
33 | */ |
|
33 | */ | |
34 | #define FIFO_Ctrl 0 |
|
34 | #define FIFO_Ctrl 0 | |
35 | #define FIFO_RWdata 1 |
|
35 | #define FIFO_RWdata 1 | |
36 |
|
36 | |||
37 | #define FIFO_Full 0x00010000 |
|
37 | #define FIFO_Full 0x00010000 | |
38 | #define FIFO_Empty 0x00000001 |
|
38 | #define FIFO_Empty 0x00000001 | |
39 | #define FIFO_ReUse 0x00000002 |
|
39 | #define FIFO_ReUse 0x00000002 | |
40 |
|
40 | |||
41 | #define Mask_2hex 0x000000FF |
|
41 | #define Mask_2hex 0x000000FF | |
42 | #define Mask_4hex 0x0000FFFF |
|
42 | #define Mask_4hex 0x0000FFFF | |
43 |
|
43 | |||
44 |
|
44 | |||
45 | /*=================================================== |
|
45 | /*=================================================== | |
46 | T Y P E S D E F |
|
46 | T Y P E S D E F | |
47 | ====================================================*/ |
|
47 | ====================================================*/ | |
48 |
|
48 | |||
49 | /*! \struct APB_FIFO_REG |
|
49 | /*! \struct APB_FIFO_REG | |
50 | \brief Sturcture representing the fifo registers |
|
50 | \brief Sturcture representing the fifo registers | |
51 | */ |
|
51 | */ | |
52 | struct APB_FIFO_REG |
|
52 | struct APB_FIFO_REG | |
53 | { |
|
53 | { | |
54 | int IDreg; |
|
54 | volatile int IDreg; | |
55 | int FIFOreg[2*8]; |
|
55 | volatile int FIFOreg[2*8]; | |
56 | }; |
|
56 | }; | |
57 |
|
57 | |||
58 | typedef volatile struct APB_FIFO_REG FIFO_Device; |
|
58 | typedef volatile struct APB_FIFO_REG FIFO_Device; | |
59 |
|
59 | |||
60 | /*=================================================== |
|
60 | /*=================================================== | |
61 | F U N C T I O N S |
|
61 | F U N C T I O N S | |
62 | ====================================================*/ |
|
62 | ====================================================*/ | |
63 |
|
63 | |||
64 | /*! \fn APB_FIFO_Device* apbfifoOpen(int count); |
|
64 | /*! \fn APB_FIFO_Device* apbfifoOpen(int count); | |
65 | \brief Return count FIFO. |
|
65 | \brief Return count FIFO. | |
66 |
|
66 | |||
67 | This Function scans APB devices table and returns count FIFO. |
|
67 | This Function scans APB devices table and returns count FIFO. | |
68 |
|
68 | |||
69 | \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want |
|
69 | \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want | |
70 | to use FIFO1 so count = 1. |
|
70 | to use FIFO1 so count = 1. | |
71 | \return The pointer to the device. |
|
71 | \return The pointer to the device. | |
72 | */ |
|
72 | */ | |
73 | FIFO_Device* openFIFO(int count); |
|
73 | FIFO_Device* openFIFO(int count); | |
74 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[]); |
|
74 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count); | |
75 |
|
75 | |||
76 | #endif |
|
76 | #endif |
@@ -1,638 +1,612 | |||||
1 | ----------------------------------------------------------------------------- |
|
1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
|
2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 |
|
19 | |||
20 |
|
20 | |||
21 | library ieee; |
|
21 | library ieee; | |
22 | use ieee.std_logic_1164.all; |
|
22 | use ieee.std_logic_1164.all; | |
23 | library grlib; |
|
23 | library grlib; | |
24 | use grlib.amba.all; |
|
24 | use grlib.amba.all; | |
25 | use grlib.stdlib.all; |
|
25 | use grlib.stdlib.all; | |
26 | library techmap; |
|
26 | library techmap; | |
27 | use techmap.gencomp.all; |
|
27 | use techmap.gencomp.all; | |
28 | library gaisler; |
|
28 | library gaisler; | |
29 | use gaisler.memctrl.all; |
|
29 | use gaisler.memctrl.all; | |
30 | use gaisler.leon3.all; |
|
30 | use gaisler.leon3.all; | |
31 | use gaisler.uart.all; |
|
31 | use gaisler.uart.all; | |
32 | use gaisler.misc.all; |
|
32 | use gaisler.misc.all; | |
33 | library esa; |
|
33 | library esa; | |
34 | use esa.memoryctrl.all; |
|
34 | use esa.memoryctrl.all; | |
35 | use work.config.all; |
|
35 | use work.config.all; | |
36 | library lpp; |
|
36 | library lpp; | |
37 | use lpp.lpp_amba.all; |
|
37 | use lpp.lpp_amba.all; | |
38 | use lpp.lpp_memory.all; |
|
38 | use lpp.lpp_memory.all; | |
39 | use lpp.lpp_uart.all; |
|
39 | use lpp.lpp_uart.all; | |
40 | use lpp.lpp_matrix.all; |
|
40 | use lpp.lpp_matrix.all; | |
41 | use lpp.lpp_delay.all; |
|
41 | use lpp.lpp_delay.all; | |
42 | use lpp.lpp_fft.all; |
|
42 | use lpp.lpp_fft.all; | |
43 | use lpp.fft_components.all; |
|
43 | use lpp.fft_components.all; | |
44 | use lpp.lpp_ad_conv.all; |
|
44 | use lpp.lpp_ad_conv.all; | |
45 | use lpp.iir_filter.all; |
|
45 | use lpp.iir_filter.all; | |
46 | use lpp.general_purpose.all; |
|
46 | use lpp.general_purpose.all; | |
47 | use lpp.Filtercfg.all; |
|
47 | use lpp.Filtercfg.all; | |
48 |
|
48 | |||
49 | entity leon3mp is |
|
49 | entity leon3mp is | |
50 | generic ( |
|
50 | generic ( | |
51 | fabtech : integer := CFG_FABTECH; |
|
51 | fabtech : integer := CFG_FABTECH; | |
52 | memtech : integer := CFG_MEMTECH; |
|
52 | memtech : integer := CFG_MEMTECH; | |
53 | padtech : integer := CFG_PADTECH; |
|
53 | padtech : integer := CFG_PADTECH; | |
54 | clktech : integer := CFG_CLKTECH; |
|
54 | clktech : integer := CFG_CLKTECH; | |
55 | disas : integer := CFG_DISAS; -- Enable disassembly to console |
|
55 | disas : integer := CFG_DISAS; -- Enable disassembly to console | |
56 | dbguart : integer := CFG_DUART; -- Print UART on console |
|
56 | dbguart : integer := CFG_DUART; -- Print UART on console | |
57 | pclow : integer := CFG_PCLOW |
|
57 | pclow : integer := CFG_PCLOW | |
58 | ); |
|
58 | ); | |
59 | port ( |
|
59 | port ( | |
60 | clk50MHz : in std_ulogic; |
|
60 | clk50MHz : in std_ulogic; | |
61 | reset : in std_ulogic; |
|
61 | reset : in std_ulogic; | |
62 | ramclk : out std_logic; |
|
62 | ramclk : out std_logic; | |
63 |
|
63 | |||
64 | ahbrxd : in std_ulogic; -- DSU rx data |
|
64 | ahbrxd : in std_ulogic; -- DSU rx data | |
65 | ahbtxd : out std_ulogic; -- DSU tx data |
|
65 | ahbtxd : out std_ulogic; -- DSU tx data | |
66 | dsubre : in std_ulogic; |
|
66 | dsubre : in std_ulogic; | |
67 | dsuact : out std_ulogic; |
|
67 | dsuact : out std_ulogic; | |
68 | urxd1 : in std_ulogic; -- UART1 rx data |
|
68 | urxd1 : in std_ulogic; -- UART1 rx data | |
69 | utxd1 : out std_ulogic; -- UART1 tx data |
|
69 | utxd1 : out std_ulogic; -- UART1 tx data | |
70 | errorn : out std_ulogic; |
|
70 | errorn : out std_ulogic; | |
71 |
|
71 | |||
72 | address : out std_logic_vector(18 downto 0); |
|
72 | address : out std_logic_vector(18 downto 0); | |
73 | data : inout std_logic_vector(31 downto 0); |
|
73 | data : inout std_logic_vector(31 downto 0); | |
74 | gpio : inout std_logic_vector(6 downto 0); -- I/O port |
|
74 | gpio : inout std_logic_vector(6 downto 0); -- I/O port | |
75 |
|
75 | |||
76 | nBWa : out std_logic; |
|
76 | nBWa : out std_logic; | |
77 | nBWb : out std_logic; |
|
77 | nBWb : out std_logic; | |
78 | nBWc : out std_logic; |
|
78 | nBWc : out std_logic; | |
79 | nBWd : out std_logic; |
|
79 | nBWd : out std_logic; | |
80 | nBWE : out std_logic; |
|
80 | nBWE : out std_logic; | |
81 | nADSC : out std_logic; |
|
81 | nADSC : out std_logic; | |
82 | nADSP : out std_logic; |
|
82 | nADSP : out std_logic; | |
83 | nADV : out std_logic; |
|
83 | nADV : out std_logic; | |
84 | nGW : out std_logic; |
|
84 | nGW : out std_logic; | |
85 | nCE1 : out std_logic; |
|
85 | nCE1 : out std_logic; | |
86 | CE2 : out std_logic; |
|
86 | CE2 : out std_logic; | |
87 | nCE3 : out std_logic; |
|
87 | nCE3 : out std_logic; | |
88 | nOE : out std_logic; |
|
88 | nOE : out std_logic; | |
89 | MODE : out std_logic; |
|
89 | MODE : out std_logic; | |
90 | SSRAM_CLK : out std_logic; |
|
90 | SSRAM_CLK : out std_logic; | |
91 | ZZ : out std_logic; |
|
91 | ZZ : out std_logic; | |
92 | --------------------------------------------------------------------- |
|
92 | --------------------------------------------------------------------- | |
93 | --- AJOUT TEST ------------------------In/Out----------------------- |
|
93 | --- AJOUT TEST ------------------------In/Out----------------------- | |
94 | --------------------------------------------------------------------- |
|
94 | --------------------------------------------------------------------- | |
95 | -- UART |
|
95 | -- UART | |
96 | UART_RXD : in std_logic; |
|
96 | UART_RXD : in std_logic; | |
97 | UART_TXD : out std_logic; |
|
97 | UART_TXD : out std_logic; | |
98 | -- ADC |
|
98 | -- ADC | |
99 | -- ADC_in : in AD7688_in(4 downto 0); |
|
99 | -- ADC_in : in AD7688_in(4 downto 0); | |
100 | -- ADC_out : out AD7688_out; |
|
100 | -- ADC_out : out AD7688_out; | |
101 | -- Bias_Fails : out std_logic; |
|
101 | -- Bias_Fails : out std_logic; | |
102 | -- CNA |
|
102 | -- CNA | |
103 | -- DAC_SYNC : out std_logic; |
|
103 | -- DAC_SYNC : out std_logic; | |
104 | -- DAC_SCLK : out std_logic; |
|
104 | -- DAC_SCLK : out std_logic; | |
105 | -- DAC_DATA : out std_logic; |
|
105 | -- DAC_DATA : out std_logic; | |
106 | -- Diver |
|
106 | -- Diver | |
107 | SPW1_EN : out std_logic; |
|
107 | SPW1_EN : out std_logic; | |
108 | SPW2_EN : out std_logic; |
|
108 | SPW2_EN : out std_logic; | |
109 | TEST : out std_logic_vector(3 downto 0); |
|
109 | TEST : out std_logic_vector(3 downto 0); | |
110 |
|
110 | |||
111 | BP : in std_logic; |
|
111 | BP : in std_logic; | |
112 | --------------------------------------------------------------------- |
|
112 | --------------------------------------------------------------------- | |
113 | led : out std_logic_vector(1 downto 0) |
|
113 | led : out std_logic_vector(1 downto 0) | |
114 | ); |
|
114 | ); | |
115 | end; |
|
115 | end; | |
116 |
|
116 | |||
117 | architecture Behavioral of leon3mp is |
|
117 | architecture Behavioral of leon3mp is | |
118 |
|
118 | |||
119 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
|
119 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ | |
120 | CFG_GRETH+CFG_AHB_JTAG; |
|
120 | CFG_GRETH+CFG_AHB_JTAG; | |
121 | constant maxahbm : integer := maxahbmsp; |
|
121 | constant maxahbm : integer := maxahbmsp; | |
122 |
|
122 | |||
123 | --Clk & Rst gοΏ½nοΏ½ |
|
123 | --Clk & Rst gοΏ½nοΏ½ | |
124 | signal vcc : std_logic_vector(4 downto 0); |
|
124 | signal vcc : std_logic_vector(4 downto 0); | |
125 | signal gnd : std_logic_vector(4 downto 0); |
|
125 | signal gnd : std_logic_vector(4 downto 0); | |
126 | signal resetnl : std_ulogic; |
|
126 | signal resetnl : std_ulogic; | |
127 | signal clk2x : std_ulogic; |
|
127 | signal clk2x : std_ulogic; | |
128 | signal lclk : std_ulogic; |
|
128 | signal lclk : std_ulogic; | |
129 | signal lclk2x : std_ulogic; |
|
129 | signal lclk2x : std_ulogic; | |
130 | signal clkm : std_ulogic; |
|
130 | signal clkm : std_ulogic; | |
131 | signal rstn : std_ulogic; |
|
131 | signal rstn : std_ulogic; | |
132 | signal rstraw : std_ulogic; |
|
132 | signal rstraw : std_ulogic; | |
133 | signal pciclk : std_ulogic; |
|
133 | signal pciclk : std_ulogic; | |
134 | signal sdclkl : std_ulogic; |
|
134 | signal sdclkl : std_ulogic; | |
135 | signal cgi : clkgen_in_type; |
|
135 | signal cgi : clkgen_in_type; | |
136 | signal cgo : clkgen_out_type; |
|
136 | signal cgo : clkgen_out_type; | |
137 | --- AHB / APB |
|
137 | --- AHB / APB | |
138 | signal apbi : apb_slv_in_type; |
|
138 | signal apbi : apb_slv_in_type; | |
139 | signal apbo : apb_slv_out_vector := (others => apb_none); |
|
139 | signal apbo : apb_slv_out_vector := (others => apb_none); | |
140 | signal ahbsi : ahb_slv_in_type; |
|
140 | signal ahbsi : ahb_slv_in_type; | |
141 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); |
|
141 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); | |
142 | signal ahbmi : ahb_mst_in_type; |
|
142 | signal ahbmi : ahb_mst_in_type; | |
143 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); |
|
143 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); | |
144 | --UART |
|
144 | --UART | |
145 | signal ahbuarti : uart_in_type; |
|
145 | signal ahbuarti : uart_in_type; | |
146 | signal ahbuarto : uart_out_type; |
|
146 | signal ahbuarto : uart_out_type; | |
147 | signal apbuarti : uart_in_type; |
|
147 | signal apbuarti : uart_in_type; | |
148 | signal apbuarto : uart_out_type; |
|
148 | signal apbuarto : uart_out_type; | |
149 | --MEM CTRLR |
|
149 | --MEM CTRLR | |
150 | signal memi : memory_in_type; |
|
150 | signal memi : memory_in_type; | |
151 | signal memo : memory_out_type; |
|
151 | signal memo : memory_out_type; | |
152 | signal wpo : wprot_out_type; |
|
152 | signal wpo : wprot_out_type; | |
153 | signal sdo : sdram_out_type; |
|
153 | signal sdo : sdram_out_type; | |
154 | --IRQ |
|
154 | --IRQ | |
155 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); |
|
155 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); | |
156 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); |
|
156 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); | |
157 | --Timer |
|
157 | --Timer | |
158 | signal gpti : gptimer_in_type; |
|
158 | signal gpti : gptimer_in_type; | |
159 | signal gpto : gptimer_out_type; |
|
159 | signal gpto : gptimer_out_type; | |
160 | --GPIO |
|
160 | --GPIO | |
161 | signal gpioi : gpio_in_type; |
|
161 | signal gpioi : gpio_in_type; | |
162 | signal gpioo : gpio_out_type; |
|
162 | signal gpioo : gpio_out_type; | |
163 | --DSU |
|
163 | --DSU | |
164 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); |
|
164 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); | |
165 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); |
|
165 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); | |
166 | signal dsui : dsu_in_type; |
|
166 | signal dsui : dsu_in_type; | |
167 | signal dsuo : dsu_out_type; |
|
167 | signal dsuo : dsu_out_type; | |
168 |
|
168 | |||
169 | --------------------------------------------------------------------- |
|
169 | --------------------------------------------------------------------- | |
170 | --- AJOUT TEST ------------------------Signaux---------------------- |
|
170 | --- AJOUT TEST ------------------------Signaux---------------------- | |
171 | --------------------------------------------------------------------- |
|
171 | --------------------------------------------------------------------- | |
172 | -- FIFOs |
|
172 | -- FIFOs | |
173 |
signal FifoIN_Full : std_logic_vector(4 downto 0); |
|
173 | signal FifoIN_Full : std_logic_vector(4 downto 0); | |
174 |
signal FifoIN_Empty : std_logic_vector(4 downto 0); |
|
174 | signal FifoIN_Empty : std_logic_vector(4 downto 0); | |
175 |
signal FifoIN_Data : std_logic_vector(79 downto 0); |
|
175 | signal FifoIN_Data : std_logic_vector(79 downto 0); | |
176 |
|
176 | |||
177 | signal FifoINT_Full : std_logic_vector(4 downto 0); |
|
177 | signal FifoINT_Full : std_logic_vector(4 downto 0); | |
178 | signal FifoINT_Data : std_logic_vector(79 downto 0); |
|
178 | signal FifoINT_Data : std_logic_vector(79 downto 0); | |
179 |
|
179 | |||
180 | signal FifoOUT_FullV : std_logic; |
|
180 | signal FifoOUT_FullV : std_logic; | |
181 |
signal FifoOUT_Full : std_logic_vector( |
|
181 | signal FifoOUT_Full : std_logic_vector(1 downto 0); | |
182 | signal Matrix_WriteV : std_logic_vector(0 downto 0); |
|
182 | signal Matrix_WriteV : std_logic_vector(0 downto 0); | |
183 |
|
183 | |||
184 | -- MATRICE SPECTRALE |
|
184 | -- MATRICE SPECTRALE | |
185 | signal Matrix_Write : std_logic; |
|
185 | signal Matrix_Write : std_logic; | |
186 | signal Matrix_Read : std_logic_vector(1 downto 0); |
|
186 | signal Matrix_Read : std_logic_vector(1 downto 0); | |
187 | signal Matrix_Result : std_logic_vector(31 downto 0); |
|
187 | signal Matrix_Result : std_logic_vector(31 downto 0); | |
188 |
|
188 | |||
189 | signal TopSM_Start : std_logic; |
|
189 | signal TopSM_Start : std_logic; | |
190 | signal TopSM_Statu : std_logic_vector(3 downto 0); |
|
190 | signal TopSM_Statu : std_logic_vector(3 downto 0); | |
191 | signal TopSM_Read : std_logic_vector(4 downto 0); |
|
191 | signal TopSM_Read : std_logic_vector(4 downto 0); | |
192 | signal TopSM_Data1 : std_logic_vector(15 downto 0); |
|
192 | signal TopSM_Data1 : std_logic_vector(15 downto 0); | |
193 | signal TopSM_Data2 : std_logic_vector(15 downto 0); |
|
193 | signal TopSM_Data2 : std_logic_vector(15 downto 0); | |
194 |
|
194 | |||
195 | signal Disp_FlagError : std_logic; |
|
195 | signal Disp_FlagError : std_logic; | |
196 | signal Disp_Pong : std_logic; |
|
196 | signal Disp_Pong : std_logic; | |
197 | signal Disp_Write : std_logic_vector(1 downto 0); |
|
197 | signal Disp_Write : std_logic_vector(1 downto 0);-- | |
198 | signal Disp_Data : std_logic_vector(63 downto 0); |
|
198 | signal Disp_Data : std_logic_vector(63 downto 0);-- | |
199 | signal Dma_acq : std_logic; |
|
199 | signal Dma_acq : std_logic; | |
200 |
|
200 | |||
201 | -- FFT |
|
201 | -- FFT | |
202 | signal Drive_Write : std_logic; |
|
202 | signal Drive_Write : std_logic; | |
203 |
signal Drive_Read : std_logic_vector(4 downto 0); |
|
203 | signal Drive_Read : std_logic_vector(4 downto 0); | |
204 | signal Drive_DataRE : std_logic_vector(15 downto 0); |
|
204 | signal Drive_DataRE : std_logic_vector(15 downto 0); | |
205 | signal Drive_DataIM : std_logic_vector(15 downto 0); |
|
205 | signal Drive_DataIM : std_logic_vector(15 downto 0); | |
206 |
|
206 | |||
207 | signal Start : std_logic; |
|
207 | signal Start : std_logic; | |
208 | signal RstnFFT : std_logic; |
|
208 | signal RstnFFT : std_logic; | |
209 | signal FFT_Load : std_logic; |
|
209 | signal FFT_Load : std_logic; | |
210 | signal FFT_Ready : std_logic; |
|
210 | signal FFT_Ready : std_logic; | |
211 | signal FFT_Valid : std_logic; |
|
211 | signal FFT_Valid : std_logic; | |
212 | signal FFT_DataRE : std_logic_vector(15 downto 0); |
|
212 | signal FFT_DataRE : std_logic_vector(15 downto 0); | |
213 | signal FFT_DataIM : std_logic_vector(15 downto 0); |
|
213 | signal FFT_DataIM : std_logic_vector(15 downto 0); | |
214 |
|
214 | |||
215 | signal Link_Read : std_logic; |
|
215 | signal Link_Read : std_logic; | |
216 |
signal Link_Write : std_logic_vector(4 downto 0); |
|
216 | signal Link_Write : std_logic_vector(4 downto 0); | |
217 |
signal Link_ReUse : std_logic_vector(4 downto 0); |
|
217 | signal Link_ReUse : std_logic_vector(4 downto 0); | |
218 |
signal Link_Data : std_logic_vector(79 downto 0); |
|
218 | signal Link_Data : std_logic_vector(79 downto 0); | |
219 |
|
219 | |||
220 | -- ADC |
|
220 | -- ADC | |
221 | signal SmplClk : std_logic; |
|
221 | signal SmplClk : std_logic; | |
222 | signal ADC_DataReady : std_logic; |
|
222 | signal ADC_DataReady : std_logic; | |
223 | signal ADC_SmplOut : Samples_out(4 downto 0); |
|
223 | signal ADC_SmplOut : Samples_out(4 downto 0); | |
224 | signal enableADC : std_logic; |
|
224 | signal enableADC : std_logic; | |
225 |
|
225 | |||
226 | signal WG_Write : std_logic_vector(4 downto 0); |
|
226 | signal WG_Write : std_logic_vector(4 downto 0); | |
227 | signal WG_ReUse : std_logic_vector(4 downto 0); |
|
227 | signal WG_ReUse : std_logic_vector(4 downto 0); | |
228 | signal WG_DATA : std_logic_vector(79 downto 0); |
|
228 | signal WG_DATA : std_logic_vector(79 downto 0); | |
229 | signal s_out : std_logic_vector(79 downto 0); |
|
229 | signal s_out : std_logic_vector(79 downto 0); | |
230 |
|
230 | |||
231 | signal fuller : std_logic_vector(4 downto 0); |
|
231 | signal fuller : std_logic_vector(4 downto 0); | |
232 | signal reader : std_logic_vector(4 downto 0); |
|
232 | signal reader : std_logic_vector(4 downto 0); | |
233 | signal try : std_logic_vector(1 downto 0); |
|
233 | signal try : std_logic_vector(1 downto 0); | |
234 | signal TXDint : std_logic; |
|
234 | signal TXDint : std_logic; | |
235 |
|
235 | |||
236 | -- IIR Filter |
|
236 | -- IIR Filter | |
237 | signal sample_clk_out : std_logic; |
|
237 | signal sample_clk_out : std_logic; | |
238 |
|
238 | |||
239 |
signal Rd : std_logic_vector(0 downto 0); |
|
239 | signal Rd : std_logic_vector(0 downto 0); | |
240 |
signal Ept : std_logic_vector(4 downto 0); |
|
240 | signal Ept : std_logic_vector(4 downto 0); | |
241 |
|
241 | |||
242 | signal Bwr : std_logic_vector(0 downto 0); |
|
242 | signal Bwr : std_logic_vector(0 downto 0); | |
243 | signal Bre : std_logic_vector(0 downto 0); |
|
243 | signal Bre : std_logic_vector(0 downto 0); | |
244 | signal DataTMP : std_logic_vector(15 downto 0); |
|
244 | signal DataTMP : std_logic_vector(15 downto 0); | |
245 | signal FullUp : std_logic_vector(0 downto 0); |
|
245 | signal FullUp : std_logic_vector(0 downto 0); | |
246 | signal EmptyUp : std_logic_vector(0 downto 0); |
|
246 | signal EmptyUp : std_logic_vector(0 downto 0); | |
247 | signal FullDown : std_logic_vector(0 downto 0); |
|
247 | signal FullDown : std_logic_vector(0 downto 0); | |
248 | signal EmptyDown : std_logic_vector(0 downto 0); |
|
248 | signal EmptyDown : std_logic_vector(0 downto 0); | |
249 | --------------------------------------------------------------------- |
|
249 | --------------------------------------------------------------------- | |
250 | constant IOAEN : integer := CFG_CAN; |
|
250 | constant IOAEN : integer := CFG_CAN; | |
251 | constant boardfreq : integer := 50000; |
|
251 | constant boardfreq : integer := 50000; | |
252 |
|
252 | |||
253 | begin |
|
253 | begin | |
254 |
|
254 | |||
255 | --------------------------------------------------------------------- |
|
255 | --------------------------------------------------------------------- | |
256 | --- AJOUT TEST -------------------------------------IPs------------- |
|
256 | --- AJOUT TEST -------------------------------------IPs------------- | |
257 | --------------------------------------------------------------------- |
|
257 | --------------------------------------------------------------------- | |
258 | led(1 downto 0) <= gpio(1 downto 0); |
|
258 | led(1 downto 0) <= gpio(1 downto 0); | |
259 |
|
259 | |||
260 | --- COM USB --------------------------------------------------------- |
|
260 | --- COM USB --------------------------------------------------------- | |
261 | -- MemIn0 : APB_FifoWrite |
|
261 | -- MemIn0 : APB_FifoWrite | |
262 | -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
|
262 | -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) | |
263 | -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); |
|
263 | -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); | |
264 | -- |
|
264 | -- | |
265 | -- BUF0 : APB_USB |
|
265 | -- BUF0 : APB_USB | |
266 | -- generic map (6,6,DataMax => 1024) |
|
266 | -- generic map (6,6,DataMax => 1024) | |
267 | -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); |
|
267 | -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); | |
268 | -- |
|
268 | -- | |
269 | -- MemOut0 : APB_FifoRead |
|
269 | -- MemOut0 : APB_FifoRead | |
270 | -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
|
270 | -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) | |
271 | -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); |
|
271 | -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); | |
272 | -- |
|
272 | -- | |
273 | --slrd <= usb_Read; |
|
273 | --slrd <= usb_Read; | |
274 | --slwr <= usb_Write; |
|
274 | --slwr <= usb_Write; | |
275 |
|
275 | |||
276 | --- CNA ------------------------------------------------------------- |
|
276 | --- CNA ------------------------------------------------------------- | |
277 |
|
277 | |||
278 | -- CONV : APB_CNA |
|
278 | -- CONV : APB_CNA | |
279 | -- generic map (5,5) |
|
279 | -- generic map (5,5) | |
280 | -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); |
|
280 | -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); | |
281 |
|
281 | |||
282 | --TEST(0) <= SmplClk; |
|
282 | --TEST(0) <= SmplClk; | |
283 | --TEST(1) <= WG_Write(0); |
|
283 | --TEST(1) <= WG_Write(0); | |
284 | --TEST(2) <= Fuller(0); |
|
284 | --TEST(2) <= Fuller(0); | |
285 | --TEST(3) <= s_out(s_out'length-1); |
|
285 | --TEST(3) <= s_out(s_out'length-1); | |
286 |
|
286 | |||
287 |
|
287 | |||
288 | SPW1_EN <= '1'; |
|
288 | --SPW1_EN <= '1'; | |
289 | SPW2_EN <= '0'; |
|
289 | --SPW2_EN <= '0'; | |
290 |
|
290 | |||
291 | --- CAN ------------------------------------------------------------- |
|
291 | --- CAN ------------------------------------------------------------- | |
292 |
|
292 | |||
293 | -- Divider : Clk_divider |
|
293 | -- Divider : Clk_divider | |
294 | -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) |
|
294 | -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) | |
295 | -- Port map(clkm,rstn,SmplClk); |
|
295 | -- Port map(clkm,rstn,SmplClk); | |
296 | -- |
|
296 | -- | |
297 | -- ADC : AD7688_drvr |
|
297 | -- ADC : AD7688_drvr | |
298 | -- generic map (ChanelCount => 5, clkkHz => 24_576) |
|
298 | -- generic map (ChanelCount => 5, clkkHz => 24_576) | |
299 | -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); |
|
299 | -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); | |
300 | -- |
|
300 | -- | |
301 | -- WG : WriteGen_ADC |
|
301 | -- WG : WriteGen_ADC | |
302 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); |
|
302 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); | |
303 | -- |
|
303 | -- | |
304 | --enableADC <= gpio(0); |
|
304 | --enableADC <= gpio(0); | |
305 | --Bias_Fails <= '0'; |
|
305 | --Bias_Fails <= '0'; | |
306 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); |
|
306 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); | |
307 | -- |
|
307 | -- | |
308 | -- |
|
308 | -- | |
309 | -- MemIn1 : APB_FIFO |
|
309 | -- MemIn1 : APB_FIFO | |
310 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
310 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
311 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); |
|
311 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); | |
312 |
|
312 | |||
313 | --- FFT ------------------------------------------------------------- |
|
313 | --- FFT ------------------------------------------------------------- | |
314 |
|
314 | |||
315 | MemIn : APB_FIFO |
|
315 | MemIn : APB_FIFO | |
316 | generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
|
316 | generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) | |
317 | port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); |
|
317 | port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); | |
318 | -- MemIn : APB_FIFO |
|
318 | ||
319 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
|
319 | DRIVE : Driver_FFT | |
320 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others =>'1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); |
|
320 | generic map(Data_sz => 16) | |
321 | -- |
|
321 | port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM); | |
322 |
|
|
322 | ||
323 | Start <= '0'; |
|
323 | Start <= '0'; | |
324 |
|
324 | |||
325 | -- DRIVE : FFTamont |
|
|||
326 | -- generic map(Data_sz => 16,NbData => 256) |
|
|||
327 | -- port map(clkm,rstn,FFT_Load,FifoIN_Empty(0),FifoIN_Data,Drive_Write,Drive_Read(0),Drive_DataRE,Drive_DataIM); |
|
|||
328 | DRIVE : Driver_FFT |
|
|||
329 | generic map(Data_sz => 16) |
|
|||
330 | port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM); |
|
|||
331 | -- |
|
|||
332 |
|
|
325 | FFT : CoreFFT | |
333 | generic map( |
|
326 | generic map( | |
334 | LOGPTS => gLOGPTS, |
|
327 | LOGPTS => gLOGPTS, | |
335 | LOGLOGPTS => gLOGLOGPTS, |
|
328 | LOGLOGPTS => gLOGLOGPTS, | |
336 | WSIZE => gWSIZE, |
|
329 | WSIZE => gWSIZE, | |
337 | TWIDTH => gTWIDTH, |
|
330 | TWIDTH => gTWIDTH, | |
338 | DWIDTH => gDWIDTH, |
|
331 | DWIDTH => gDWIDTH, | |
339 | TDWIDTH => gTDWIDTH, |
|
332 | TDWIDTH => gTDWIDTH, | |
340 | RND_MODE => gRND_MODE, |
|
333 | RND_MODE => gRND_MODE, | |
341 | SCALE_MODE => gSCALE_MODE, |
|
334 | SCALE_MODE => gSCALE_MODE, | |
342 | PTS => gPTS, |
|
335 | PTS => gPTS, | |
343 | HALFPTS => gHALFPTS, |
|
336 | HALFPTS => gHALFPTS, | |
344 | inBuf_RWDLY => gInBuf_RWDLY) |
|
337 | inBuf_RWDLY => gInBuf_RWDLY) | |
345 | port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); |
|
338 | port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); | |
346 | -- |
|
339 | ||
347 |
|
|
340 | LINK : Linker_FFT | |
348 | generic map(Data_sz => 16) |
|
341 | generic map(Data_sz => 16) | |
349 |
port map(clkm,rstn,FFT_Ready,FFT_Valid,Fifo |
|
342 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data); | |
350 | -- LINK : FFTaval |
|
343 | ||
351 | -- generic map(Data_sz => 16,NbData => 256) |
|
344 | ----- LINK MEMORY ------------------------------------------------------- | |
352 | -- port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full(0),FFT_DataRE,FFT_DataIM,Link_Read,Link_Write(0),Link_ReUse(0),Link_Data); |
|
345 | ||
353 | -- |
|
346 | -- MemOut : APB_FIFO | |
|
347 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) | |||
|
348 | -- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9)); | |||
|
349 | ||||
|
350 | MemInt : lppFIFOxN | |||
|
351 | generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') | |||
|
352 | port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); | |||
|
353 | ||||
|
354 | -- MemIn : APB_FIFO | |||
|
355 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) | |||
|
356 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); | |||
|
357 | ||||
354 | ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- |
|
358 | ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- | |
355 | -- |
|
|||
356 | MemOut : APB_FIFO |
|
|||
357 | generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) |
|
|||
358 | port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9)); |
|
|||
359 |
|
||||
360 |
|
||||
361 | --TEST(0) <= FifoOUT_Full(0); |
|
|||
362 | --TEST(1) <= Link_Write(0); |
|
|||
363 |
|
359 | |||
364 | -- MemInt : lppFIFOx5 |
|
360 | TopSM : TopSpecMatrix | |
365 |
|
|
361 | generic map (Input_SZ => 16) | |
366 | -- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); |
|
362 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoINT_Full,FifoINT_Data,TopSM_Start,TopSM_Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); | |
367 | -- |
|
363 | ||
368 | --Matrix_WriteV(0) <= not Matrix_Write; |
|
364 | SM : SpectralMatrix | |
369 | --FifoOUT_FullV <= FifoOUT_Full(0); |
|
365 | generic map (Input_SZ => 16, Result_SZ => 32) | |
370 | -- |
|
366 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); | |
371 | ---- MemInt : lppFIFOxN |
|
367 | ||
372 | ---- generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') |
|
368 | Dma_acq <= '1'; | |
373 | ---- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); |
|
|||
374 | -- |
|
|||
375 | -- TopSM : TopMatrix_PDR |
|
|||
376 | -- generic map (Input_SZ => 16) |
|
|||
377 | -- port map (clkm,rstn,FifoINT_Data,FifoINT_Full,Matrix_Read,Matrix_Write,TopSM_Data1,TopSM_Data2,TopSM_Start,TopSM_Read,TopSM_Statu); |
|
|||
378 | -- |
|
|||
379 | -- SM : SpectralMatrix |
|
|||
380 | -- generic map (Input_SZ => 16, Result_SZ => 32) |
|
|||
381 | -- port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); |
|
|||
382 |
|
369 | |||
|
370 | DISP : Dispatch | |||
|
371 | generic map(Data_SZ => 32) | |||
|
372 | port map(clkm,rstn,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError); | |||
|
373 | ||||
|
374 | MemOut : APB_FIFO | |||
|
375 | generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |||
|
376 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(9)); | |||
|
377 | ||||
|
378 | ----- FIFO ------------------------------------------------------------- | |||
|
379 | ||||
|
380 | Memtest : APB_FIFO | |||
|
381 | generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) | |||
|
382 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); | |||
383 |
|
383 | |||
384 | --***************************************TEST DEMI-FIFO******************************************************************************** |
|
384 | --***************************************TEST DEMI-FIFO******************************************************************************** | |
385 | -- MemIn : APB_FIFO |
|
385 | -- MemIn : APB_FIFO | |
386 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
|
386 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) | |
387 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); |
|
387 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); | |
388 | -- |
|
388 | -- | |
389 | -- Pont : Bridge |
|
389 | -- Pont : Bridge | |
390 | -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); |
|
390 | -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); | |
391 | -- |
|
391 | -- | |
392 | -- MemOut : APB_FIFO |
|
392 | -- MemOut : APB_FIFO | |
393 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
393 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
394 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); |
|
394 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); | |
395 | --************************************************************************************************************************************* |
|
395 | --************************************************************************************************************************************* | |
396 |
|
396 | |||
397 |
|
||||
398 |
|
||||
399 |
|
||||
400 |
|
||||
401 |
|
||||
402 |
|
||||
403 |
|
||||
404 |
|
||||
405 |
|
||||
406 |
|
||||
407 | --Dma_acq <= '1'; |
|
|||
408 | -- |
|
|||
409 | -- DISP : Dispatch |
|
|||
410 | -- generic map(Data_SZ => 32) |
|
|||
411 | -- port map(clkm,reset,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError); |
|
|||
412 | -- |
|
|||
413 | ----- FIFO ------------------------------------------------------------- |
|
|||
414 | -- |
|
|||
415 | -- MemOut : APB_FIFO |
|
|||
416 | -- generic map (pindex => 15, paddr => 15, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
|||
417 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(15)); |
|
|||
418 | -- |
|
|||
419 | Memtest : APB_FIFO |
|
|||
420 | generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) |
|
|||
421 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); |
|
|||
422 |
|
||||
423 | --- UART ------------------------------------------------------------- |
|
397 | --- UART ------------------------------------------------------------- | |
424 |
|
398 | |||
425 | COM0 : APB_UART |
|
399 | COM0 : APB_UART | |
426 | generic map (pindex => 4, paddr => 4) |
|
400 | generic map (pindex => 4, paddr => 4) | |
427 | port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD); |
|
401 | port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD); | |
428 |
|
402 | |||
429 | --- DELAY ------------------------------------------------------------ |
|
403 | --- DELAY ------------------------------------------------------------ | |
430 |
|
404 | |||
431 | -- Delay0 : APB_Delay |
|
405 | -- Delay0 : APB_Delay | |
432 | -- generic map (pindex => 4, paddr => 4) |
|
406 | -- generic map (pindex => 4, paddr => 4) | |
433 | -- port map (clkm,rstn,apbi,apbo(4)); |
|
407 | -- port map (clkm,rstn,apbi,apbo(4)); | |
434 |
|
408 | |||
435 | --- IIR Filter ------------------------------------------------------- |
|
409 | --- IIR Filter ------------------------------------------------------- | |
436 | --Test(0) <= sample_clk_out; |
|
410 | --Test(0) <= sample_clk_out; | |
437 | -- |
|
411 | -- | |
438 | -- |
|
412 | -- | |
439 | -- IIR1: APB_IIR_Filter |
|
413 | -- IIR1: APB_IIR_Filter | |
440 | -- generic map( |
|
414 | -- generic map( | |
441 | -- tech => CFG_MEMTECH, |
|
415 | -- tech => CFG_MEMTECH, | |
442 | -- pindex => 8, |
|
416 | -- pindex => 8, | |
443 | -- paddr => 8, |
|
417 | -- paddr => 8, | |
444 | -- Sample_SZ => Sample_SZ, |
|
418 | -- Sample_SZ => Sample_SZ, | |
445 | -- ChanelsCount => ChanelsCount, |
|
419 | -- ChanelsCount => ChanelsCount, | |
446 | -- Coef_SZ => Coef_SZ, |
|
420 | -- Coef_SZ => Coef_SZ, | |
447 | -- CoefCntPerCel => CoefCntPerCel, |
|
421 | -- CoefCntPerCel => CoefCntPerCel, | |
448 | -- Cels_count => Cels_count, |
|
422 | -- Cels_count => Cels_count, | |
449 | -- virgPos => virgPos |
|
423 | -- virgPos => virgPos | |
450 | -- ) |
|
424 | -- ) | |
451 | -- port map( |
|
425 | -- port map( | |
452 | -- rst => rstn, |
|
426 | -- rst => rstn, | |
453 | -- clk => clkm, |
|
427 | -- clk => clkm, | |
454 | -- apbi => apbi, |
|
428 | -- apbi => apbi, | |
455 | -- apbo => apbo(8), |
|
429 | -- apbo => apbo(8), | |
456 | -- sample_clk_out => sample_clk_out, |
|
430 | -- sample_clk_out => sample_clk_out, | |
457 | -- GOtest => Test(1), |
|
431 | -- GOtest => Test(1), | |
458 | -- CoefsInitVal => (others => '1') |
|
432 | -- CoefsInitVal => (others => '1') | |
459 | -- ); |
|
433 | -- ); | |
460 | ---------------------------------------------------------------------- |
|
434 | ---------------------------------------------------------------------- | |
461 |
|
435 | |||
462 | ---------------------------------------------------------------------- |
|
436 | ---------------------------------------------------------------------- | |
463 | --- Reset and Clock generation ------------------------------------- |
|
437 | --- Reset and Clock generation ------------------------------------- | |
464 | ---------------------------------------------------------------------- |
|
438 | ---------------------------------------------------------------------- | |
465 |
|
439 | |||
466 | vcc <= (others => '1'); gnd <= (others => '0'); |
|
440 | vcc <= (others => '1'); gnd <= (others => '0'); | |
467 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
|
441 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; | |
468 |
|
442 | |||
469 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); |
|
443 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); | |
470 |
|
444 | |||
471 |
|
445 | |||
472 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); |
|
446 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); | |
473 |
|
447 | |||
474 | clkgen0 : clkgen -- clock generator |
|
448 | clkgen0 : clkgen -- clock generator | |
475 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
449 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
476 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
|
450 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) | |
477 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); |
|
451 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); | |
478 |
|
452 | |||
479 | ramclk <= clkm; |
|
453 | ramclk <= clkm; | |
480 | process(lclk2x) |
|
454 | process(lclk2x) | |
481 | begin |
|
455 | begin | |
482 | if lclk2x'event and lclk2x = '1' then |
|
456 | if lclk2x'event and lclk2x = '1' then | |
483 | lclk <= not lclk; |
|
457 | lclk <= not lclk; | |
484 | end if; |
|
458 | end if; | |
485 | end process; |
|
459 | end process; | |
486 |
|
460 | |||
487 | ---------------------------------------------------------------------- |
|
461 | ---------------------------------------------------------------------- | |
488 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
462 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
489 | ---------------------------------------------------------------------- |
|
463 | ---------------------------------------------------------------------- | |
490 |
|
464 | |||
491 | l3 : if CFG_LEON3 = 1 generate |
|
465 | l3 : if CFG_LEON3 = 1 generate | |
492 | cpu : for i in 0 to CFG_NCPU-1 generate |
|
466 | cpu : for i in 0 to CFG_NCPU-1 generate | |
493 | u0 : leon3s -- LEON3 processor |
|
467 | u0 : leon3s -- LEON3 processor | |
494 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
468 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
495 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
469 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
496 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
470 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
497 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
471 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
498 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
472 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
499 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
473 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) | |
500 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
474 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, | |
501 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
475 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
502 | end generate; |
|
476 | end generate; | |
503 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); |
|
477 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); | |
504 |
|
478 | |||
505 | dsugen : if CFG_DSU = 1 generate |
|
479 | dsugen : if CFG_DSU = 1 generate | |
506 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
480 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
507 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
481 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
508 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
482 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
509 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
483 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
510 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); |
|
484 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); | |
511 | dsui.enable <= '1'; |
|
485 | dsui.enable <= '1'; | |
512 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); |
|
486 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); | |
513 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); |
|
487 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); | |
514 | end generate; |
|
488 | end generate; | |
515 | end generate; |
|
489 | end generate; | |
516 |
|
490 | |||
517 | nodsu : if CFG_DSU = 0 generate |
|
491 | nodsu : if CFG_DSU = 0 generate | |
518 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
|
492 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; | |
519 | end generate; |
|
493 | end generate; | |
520 |
|
494 | |||
521 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate |
|
495 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate | |
522 | irqctrl0 : irqmp -- interrupt controller |
|
496 | irqctrl0 : irqmp -- interrupt controller | |
523 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
497 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
524 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
498 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
525 | end generate; |
|
499 | end generate; | |
526 | irq3 : if CFG_IRQ3_ENABLE = 0 generate |
|
500 | irq3 : if CFG_IRQ3_ENABLE = 0 generate | |
527 | x : for i in 0 to CFG_NCPU-1 generate |
|
501 | x : for i in 0 to CFG_NCPU-1 generate | |
528 | irqi(i).irl <= "0000"; |
|
502 | irqi(i).irl <= "0000"; | |
529 | end generate; |
|
503 | end generate; | |
530 | apbo(2) <= apb_none; |
|
504 | apbo(2) <= apb_none; | |
531 | end generate; |
|
505 | end generate; | |
532 |
|
506 | |||
533 | ---------------------------------------------------------------------- |
|
507 | ---------------------------------------------------------------------- | |
534 | --- Memory controllers --------------------------------------------- |
|
508 | --- Memory controllers --------------------------------------------- | |
535 | ---------------------------------------------------------------------- |
|
509 | ---------------------------------------------------------------------- | |
536 |
|
510 | |||
537 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) |
|
511 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) | |
538 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); |
|
512 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); | |
539 |
|
513 | |||
540 | memi.brdyn <= '1'; memi.bexcn <= '1'; |
|
514 | memi.brdyn <= '1'; memi.bexcn <= '1'; | |
541 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; |
|
515 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; | |
542 |
|
516 | |||
543 | bdr : for i in 0 to 3 generate |
|
517 | bdr : for i in 0 to 3 generate | |
544 | data_pad : iopadv generic map (tech => padtech, width => 8) |
|
518 | data_pad : iopadv generic map (tech => padtech, width => 8) | |
545 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), |
|
519 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), | |
546 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); |
|
520 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); | |
547 | end generate; |
|
521 | end generate; | |
548 |
|
522 | |||
549 |
|
523 | |||
550 | addr_pad : outpadv generic map (width => 19, tech => padtech) |
|
524 | addr_pad : outpadv generic map (width => 19, tech => padtech) | |
551 | port map (address, memo.address(20 downto 2)); |
|
525 | port map (address, memo.address(20 downto 2)); | |
552 |
|
526 | |||
553 |
|
527 | |||
554 | SSRAM_0:entity ssram_plugin |
|
528 | SSRAM_0:entity ssram_plugin | |
555 | generic map (tech => padtech) |
|
529 | generic map (tech => padtech) | |
556 | port map |
|
530 | port map | |
557 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); |
|
531 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); | |
558 |
|
532 | |||
559 | ---------------------------------------------------------------------- |
|
533 | ---------------------------------------------------------------------- | |
560 | --- AHB CONTROLLER ------------------------------------------------- |
|
534 | --- AHB CONTROLLER ------------------------------------------------- | |
561 | ---------------------------------------------------------------------- |
|
535 | ---------------------------------------------------------------------- | |
562 |
|
536 | |||
563 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
537 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
564 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
538 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
565 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
539 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
566 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
|
540 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | |
567 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
541 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
568 |
|
542 | |||
569 | ---------------------------------------------------------------------- |
|
543 | ---------------------------------------------------------------------- | |
570 | --- AHB UART ------------------------------------------------------- |
|
544 | --- AHB UART ------------------------------------------------------- | |
571 | ---------------------------------------------------------------------- |
|
545 | ---------------------------------------------------------------------- | |
572 |
|
546 | |||
573 | dcomgen : if CFG_AHB_UART = 1 generate |
|
547 | dcomgen : if CFG_AHB_UART = 1 generate | |
574 | dcom0: ahbuart -- Debug UART |
|
548 | dcom0: ahbuart -- Debug UART | |
575 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) |
|
549 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) | |
576 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); |
|
550 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); | |
577 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); |
|
551 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); | |
578 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); |
|
552 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); | |
579 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; |
|
553 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; | |
580 | end generate; |
|
554 | end generate; | |
581 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; |
|
555 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; | |
582 |
|
556 | |||
583 | ---------------------------------------------------------------------- |
|
557 | ---------------------------------------------------------------------- | |
584 | --- APB Bridge ----------------------------------------------------- |
|
558 | --- APB Bridge ----------------------------------------------------- | |
585 | ---------------------------------------------------------------------- |
|
559 | ---------------------------------------------------------------------- | |
586 |
|
560 | |||
587 | apb0 : apbctrl -- AHB/APB bridge |
|
561 | apb0 : apbctrl -- AHB/APB bridge | |
588 | generic map (hindex => 1, haddr => CFG_APBADDR) |
|
562 | generic map (hindex => 1, haddr => CFG_APBADDR) | |
589 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); |
|
563 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); | |
590 |
|
564 | |||
591 | ---------------------------------------------------------------------- |
|
565 | ---------------------------------------------------------------------- | |
592 | --- GPT Timer ------------------------------------------------------ |
|
566 | --- GPT Timer ------------------------------------------------------ | |
593 | ---------------------------------------------------------------------- |
|
567 | ---------------------------------------------------------------------- | |
594 |
|
568 | |||
595 | gpt : if CFG_GPT_ENABLE /= 0 generate |
|
569 | gpt : if CFG_GPT_ENABLE /= 0 generate | |
596 | timer0 : gptimer -- timer unit |
|
570 | timer0 : gptimer -- timer unit | |
597 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
571 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
598 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
572 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
599 | nbits => CFG_GPT_TW) |
|
573 | nbits => CFG_GPT_TW) | |
600 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
574 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
601 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; |
|
575 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; | |
602 | -- led(4) <= gpto.wdog; |
|
576 | -- led(4) <= gpto.wdog; | |
603 | end generate; |
|
577 | end generate; | |
604 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; |
|
578 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; | |
605 |
|
579 | |||
606 |
|
580 | |||
607 | ---------------------------------------------------------------------- |
|
581 | ---------------------------------------------------------------------- | |
608 | --- APB UART ------------------------------------------------------- |
|
582 | --- APB UART ------------------------------------------------------- | |
609 | ---------------------------------------------------------------------- |
|
583 | ---------------------------------------------------------------------- | |
610 |
|
584 | |||
611 | ua1 : if CFG_UART1_ENABLE /= 0 generate |
|
585 | ua1 : if CFG_UART1_ENABLE /= 0 generate | |
612 | uart1 : apbuart -- UART 1 |
|
586 | uart1 : apbuart -- UART 1 | |
613 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
587 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
614 | fifosize => CFG_UART1_FIFO) |
|
588 | fifosize => CFG_UART1_FIFO) | |
615 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); |
|
589 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); | |
616 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; |
|
590 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; | |
617 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; |
|
591 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; | |
618 | -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; |
|
592 | -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; | |
619 | end generate; |
|
593 | end generate; | |
620 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; |
|
594 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; | |
621 |
|
595 | |||
622 | ---------------------------------------------------------------------- |
|
596 | ---------------------------------------------------------------------- | |
623 | --- GPIO ----------------------------------------------------------- |
|
597 | --- GPIO ----------------------------------------------------------- | |
624 | ---------------------------------------------------------------------- |
|
598 | ---------------------------------------------------------------------- | |
625 |
|
599 | |||
626 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit |
|
600 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit | |
627 | grgpio0: grgpio |
|
601 | grgpio0: grgpio | |
628 | generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) |
|
602 | generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) | |
629 | port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); |
|
603 | port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); | |
630 |
|
604 | |||
631 | pio_pads : for i in 0 to 6 generate |
|
605 | pio_pads : for i in 0 to 6 generate | |
632 | pio_pad : iopad generic map (tech => padtech) |
|
606 | pio_pad : iopad generic map (tech => padtech) | |
633 | port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); |
|
607 | port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); | |
634 | end generate; |
|
608 | end generate; | |
635 | end generate; |
|
609 | end generate; | |
636 |
|
610 | |||
637 |
|
611 | |||
638 | end Behavioral; No newline at end of file |
|
612 | end Behavioral; |
@@ -1,109 +1,95 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
25 | use lpp.lpp_matrix.all; |
|
|||
26 |
|
25 | |||
27 | entity Dispatch is |
|
26 | entity Dispatch is | |
28 | generic( |
|
27 | generic( | |
29 | Data_SZ : integer := 32); |
|
28 | Data_SZ : integer := 32); | |
30 | port( |
|
29 | port( | |
31 | clk : in std_logic; |
|
30 | clk : in std_logic; | |
32 | reset : in std_logic; |
|
31 | reset : in std_logic; | |
33 | Acq : in std_logic; |
|
32 | Acq : in std_logic; | |
34 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
33 | Data : in std_logic_vector(Data_SZ-1 downto 0); | |
35 | Write : in std_logic; |
|
34 | Write : in std_logic; | |
36 | Full : in std_logic_vector(1 downto 0); |
|
35 | Full : in std_logic_vector(1 downto 0); | |
37 | -- Empty : in std_logic_vector(1 downto 0); |
|
|||
38 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
36 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); | |
39 | FifoWrite : out std_logic_vector(1 downto 0); |
|
37 | FifoWrite : out std_logic_vector(1 downto 0); | |
40 | -- FifoFull : out std_logic; |
|
|||
41 | Pong : out std_logic; |
|
38 | Pong : out std_logic; | |
42 | Error : out std_logic |
|
39 | Error : out std_logic | |
43 |
|
||||
44 | ); |
|
40 | ); | |
45 | end entity; |
|
41 | end entity; | |
46 |
|
42 | |||
47 |
|
43 | |||
48 | architecture ar_Dispatch of Dispatch is |
|
44 | architecture ar_Dispatch of Dispatch is | |
49 |
|
45 | |||
50 |
type etat is (e0,e1,e2 |
|
46 | type etat is (eX,e0,e1,e2); | |
51 | signal ect : etat; |
|
47 | signal ect : etat; | |
52 |
|
48 | |||
|
49 | signal Pong_int : std_logic; | |||
|
50 | signal FifoCpt : integer range 0 to 1 := 0; | |||
|
51 | ||||
53 | begin |
|
52 | begin | |
54 |
|
53 | |||
55 | process (clk,reset) |
|
54 | process (clk,reset) | |
56 | begin |
|
55 | begin | |
57 | if(reset='0')then |
|
56 | if(reset='0')then | |
58 | Pong <= '0'; |
|
57 | Pong_int <= '0'; | |
59 |
Error <= '0'; |
|
58 | Error <= '0'; | |
|
59 | ect <= e0; | |||
60 |
|
60 | |||
61 | elsif(clk' event and clk='1')then |
|
61 | elsif(clk' event and clk='1')then | |
62 |
|
62 | |||
63 | case ect is |
|
63 | case ect is | |
64 |
|
64 | |||
65 | when e0 => |
|
65 | when e0 => | |
66 |
if(Full( |
|
66 | if(Full(FifoCpt) = '1')then | |
67 | pong <= '1'; |
|
67 | Pong_int <= not Pong_int; | |
68 | ect <= e1; |
|
68 | ect <= e1; | |
69 | end if; |
|
69 | end if; | |
70 |
|
70 | |||
71 | when e1 => |
|
71 | when e1 => | |
72 |
if(Acq |
|
72 | if(Acq = '0')then | |
73 | Error <= '0'; |
|
|||
74 | pong <= '0'; |
|
|||
75 | ect <= e2; |
|
|||
76 | else |
|
|||
77 | Error <= '1'; |
|
73 | Error <= '1'; | |
78 | ect <= e1; |
|
74 | ect <= e1; | |
|
75 | else | |||
|
76 | Error <= '0'; | |||
|
77 | ect <= e0; | |||
79 | end if; |
|
78 | end if; | |
80 |
|
79 | |||
81 |
|
|
80 | when others => | |
82 |
|
|
81 | null; | |
83 | pong <= '1'; |
|
|||
84 | ect <= e3; |
|
|||
85 | end if; |
|
|||
86 |
|
||||
87 | when e3 => |
|
|||
88 | if(Acq <= '1')then |
|
|||
89 | Error <= '0'; |
|
|||
90 | pong <= '0'; |
|
|||
91 | ect <= e0; |
|
|||
92 | else |
|
|||
93 | Error <= '1'; |
|
|||
94 | ect <= e3; |
|
|||
95 | end if; |
|
|||
96 |
|
|
82 | ||
97 |
|
|
83 | end case; | |
98 |
|
84 | |||
99 | end if; |
|
85 | end if; | |
100 | end process; |
|
86 | end process; | |
101 |
|
87 | |||
102 | FifoData <= Data & Data; |
|
88 | FifoData <= Data & Data; | |
|
89 | Pong <= Pong_int; | |||
103 |
|
90 | |||
104 | with ect select |
|
91 | FifoCpt <= 0 when Pong_int='0' else 1; | |
105 | FifoWrite <= '1' & not Write when e0, |
|
92 | ||
106 | not Write & '1' when e2, |
|
93 | FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; | |
107 | "11" when others; |
|
|||
108 |
|
94 | |||
109 | end architecture; No newline at end of file |
|
95 | end architecture; |
@@ -1,259 +1,278 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
29 |
|
29 | |||
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |
31 |
|
31 | |||
32 | package lpp_matrix is |
|
32 | package lpp_matrix is | |
33 |
|
33 | |||
34 | component APB_Matrix is |
|
34 | component APB_Matrix is | |
35 | generic ( |
|
35 | generic ( | |
36 | pindex : integer := 0; |
|
36 | pindex : integer := 0; | |
37 | paddr : integer := 0; |
|
37 | paddr : integer := 0; | |
38 | pmask : integer := 16#fff#; |
|
38 | pmask : integer := 16#fff#; | |
39 | pirq : integer := 0; |
|
39 | pirq : integer := 0; | |
40 | abits : integer := 8; |
|
40 | abits : integer := 8; | |
41 | Input_SZ : integer := 16; |
|
41 | Input_SZ : integer := 16; | |
42 | Result_SZ : integer := 32); |
|
42 | Result_SZ : integer := 32); | |
43 | port ( |
|
43 | port ( | |
44 | clk : in std_logic; |
|
44 | clk : in std_logic; | |
45 | rst : in std_logic; |
|
45 | rst : in std_logic; | |
46 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
46 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
47 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
47 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
48 | Full : in std_logic_vector(1 downto 0); |
|
48 | Full : in std_logic_vector(1 downto 0); | |
49 | Empty : in std_logic_vector(1 downto 0); |
|
49 | Empty : in std_logic_vector(1 downto 0); | |
50 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
50 | ReadFIFO : out std_logic_vector(1 downto 0); | |
51 | FullFIFO : in std_logic; |
|
51 | FullFIFO : in std_logic; | |
52 | WriteFIFO : out std_logic; |
|
52 | WriteFIFO : out std_logic; | |
53 | Result : out std_logic_vector(Result_SZ-1 downto 0); |
|
53 | Result : out std_logic_vector(Result_SZ-1 downto 0); | |
54 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
|
54 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
55 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
55 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
56 | ); |
|
56 | ); | |
57 | end component; |
|
57 | end component; | |
58 |
|
58 | |||
|
59 | component TopSpecMatrix is | |||
|
60 | generic( | |||
|
61 | Input_SZ : integer := 16); | |||
|
62 | port( | |||
|
63 | clk : in std_logic; | |||
|
64 | rstn : in std_logic; | |||
|
65 | Write : in std_logic; | |||
|
66 | ReadIn : in std_logic_vector(1 downto 0); | |||
|
67 | Full : in std_logic_vector(4 downto 0); | |||
|
68 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); | |||
|
69 | Start : out std_logic; | |||
|
70 | ReadOut : out std_logic_vector(4 downto 0); | |||
|
71 | Statu : out std_logic_vector(3 downto 0); | |||
|
72 | DATA1 : out std_logic_vector(Input_SZ-1 downto 0); | |||
|
73 | DATA2 : out std_logic_vector(Input_SZ-1 downto 0) | |||
|
74 | ); | |||
|
75 | end component; | |||
|
76 | ||||
|
77 | ||||
59 | component Top_MatrixSpec is |
|
78 | component Top_MatrixSpec is | |
60 | generic( |
|
79 | generic( | |
61 | Input_SZ : integer := 16; |
|
80 | Input_SZ : integer := 16; | |
62 | Result_SZ : integer := 32); |
|
81 | Result_SZ : integer := 32); | |
63 | port( |
|
82 | port( | |
64 | clk : in std_logic; |
|
83 | clk : in std_logic; | |
65 | reset : in std_logic; |
|
84 | reset : in std_logic; | |
66 | Statu : in std_logic_vector(3 downto 0); |
|
85 | Statu : in std_logic_vector(3 downto 0); | |
67 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
86 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
68 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
87 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
69 | Full : in std_logic_vector(1 downto 0); |
|
88 | Full : in std_logic_vector(1 downto 0); | |
70 | Empty : in std_logic_vector(1 downto 0); |
|
89 | Empty : in std_logic_vector(1 downto 0); | |
71 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
90 | ReadFIFO : out std_logic_vector(1 downto 0); | |
72 | FullFIFO : in std_logic; |
|
91 | FullFIFO : in std_logic; | |
73 | WriteFIFO : out std_logic; |
|
92 | WriteFIFO : out std_logic; | |
74 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
93 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
75 | ); |
|
94 | ); | |
76 | end component; |
|
95 | end component; | |
77 |
|
96 | |||
78 | component SpectralMatrix is |
|
97 | component SpectralMatrix is | |
79 | generic( |
|
98 | generic( | |
80 | Input_SZ : integer := 16; |
|
99 | Input_SZ : integer := 16; | |
81 | Result_SZ : integer := 32); |
|
100 | Result_SZ : integer := 32); | |
82 | port( |
|
101 | port( | |
83 | clk : in std_logic; |
|
102 | clk : in std_logic; | |
84 | reset : in std_logic; |
|
103 | reset : in std_logic; | |
85 | Start : in std_logic; |
|
104 | Start : in std_logic; | |
86 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
105 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
87 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
106 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
88 | Statu : in std_logic_vector(3 downto 0); |
|
107 | Statu : in std_logic_vector(3 downto 0); | |
89 | -- FullFIFO : in std_logic; |
|
108 | -- FullFIFO : in std_logic; | |
90 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
109 | ReadFIFO : out std_logic_vector(1 downto 0); | |
91 | WriteFIFO : out std_logic; |
|
110 | WriteFIFO : out std_logic; | |
92 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
111 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
93 | ); |
|
112 | ); | |
94 | end component; |
|
113 | end component; | |
95 |
|
114 | |||
96 |
|
115 | |||
97 | component Matrix is |
|
116 | component Matrix is | |
98 | generic( |
|
117 | generic( | |
99 | Input_SZ : integer := 16); |
|
118 | Input_SZ : integer := 16); | |
100 | port( |
|
119 | port( | |
101 | clk : in std_logic; |
|
120 | clk : in std_logic; | |
102 | raz : in std_logic; |
|
121 | raz : in std_logic; | |
103 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
122 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); | |
104 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
123 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); | |
105 | Take : in std_logic; |
|
124 | Take : in std_logic; | |
106 | Received : in std_logic; |
|
125 | Received : in std_logic; | |
107 | Conjugate : in std_logic; |
|
126 | Conjugate : in std_logic; | |
108 | Valid : out std_logic; |
|
127 | Valid : out std_logic; | |
109 | Read : out std_logic; |
|
128 | Read : out std_logic; | |
110 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) |
|
129 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) | |
111 | ); |
|
130 | ); | |
112 | end component; |
|
131 | end component; | |
113 |
|
132 | |||
114 | component GetResult is |
|
133 | component GetResult is | |
115 | generic( |
|
134 | generic( | |
116 | Result_SZ : integer := 32); |
|
135 | Result_SZ : integer := 32); | |
117 | port( |
|
136 | port( | |
118 | clk : in std_logic; |
|
137 | clk : in std_logic; | |
119 | raz : in std_logic; |
|
138 | raz : in std_logic; | |
120 | Valid : in std_logic; |
|
139 | Valid : in std_logic; | |
121 | Conjugate : in std_logic; |
|
140 | Conjugate : in std_logic; | |
122 | Res : in std_logic_vector(Result_SZ-1 downto 0); |
|
141 | Res : in std_logic_vector(Result_SZ-1 downto 0); | |
123 | -- Full : in std_logic; |
|
142 | -- Full : in std_logic; | |
124 | WriteFIFO : out std_logic; |
|
143 | WriteFIFO : out std_logic; | |
125 | Received : out std_logic; |
|
144 | Received : out std_logic; | |
126 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
145 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
127 | ); |
|
146 | ); | |
128 | end component; |
|
147 | end component; | |
129 |
|
148 | |||
130 |
|
149 | |||
131 | component TopMatrix_PDR is |
|
150 | component TopMatrix_PDR is | |
132 | generic( |
|
151 | generic( | |
133 | Input_SZ : integer := 16; |
|
152 | Input_SZ : integer := 16; | |
134 | Result_SZ : integer := 32); |
|
153 | Result_SZ : integer := 32); | |
135 | port( |
|
154 | port( | |
136 | clk : in std_logic; |
|
155 | clk : in std_logic; | |
137 | reset : in std_logic; |
|
156 | reset : in std_logic; | |
138 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
157 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
139 | FULLin : in std_logic_vector(4 downto 0); |
|
158 | FULLin : in std_logic_vector(4 downto 0); | |
140 | READin : in std_logic_vector(1 downto 0); |
|
159 | READin : in std_logic_vector(1 downto 0); | |
141 | WRITEin : in std_logic; |
|
160 | WRITEin : in std_logic; | |
142 | FIFO1 : out std_logic_vector(Input_SZ-1 downto 0); |
|
161 | FIFO1 : out std_logic_vector(Input_SZ-1 downto 0); | |
143 | FIFO2 : out std_logic_vector(Input_SZ-1 downto 0); |
|
162 | FIFO2 : out std_logic_vector(Input_SZ-1 downto 0); | |
144 | Start : out std_logic; |
|
163 | Start : out std_logic; | |
145 | Read : out std_logic_vector(4 downto 0); |
|
164 | Read : out std_logic_vector(4 downto 0); | |
146 | Statu : out std_logic_vector(3 downto 0) |
|
165 | Statu : out std_logic_vector(3 downto 0) | |
147 | ); |
|
166 | ); | |
148 | end component; |
|
167 | end component; | |
149 |
|
168 | |||
150 |
|
169 | |||
151 | component Dispatch is |
|
170 | component Dispatch is | |
152 | generic( |
|
171 | generic( | |
153 | Data_SZ : integer := 32); |
|
172 | Data_SZ : integer := 32); | |
154 | port( |
|
173 | port( | |
155 | clk : in std_logic; |
|
174 | clk : in std_logic; | |
156 | reset : in std_logic; |
|
175 | reset : in std_logic; | |
157 | Acq : in std_logic; |
|
176 | Acq : in std_logic; | |
158 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
177 | Data : in std_logic_vector(Data_SZ-1 downto 0); | |
159 | Write : in std_logic; |
|
178 | Write : in std_logic; | |
160 | Full : in std_logic_vector(1 downto 0); |
|
179 | Full : in std_logic_vector(1 downto 0); | |
161 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
180 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); | |
162 | FifoWrite : out std_logic_vector(1 downto 0); |
|
181 | FifoWrite : out std_logic_vector(1 downto 0); | |
163 | Pong : out std_logic; |
|
182 | Pong : out std_logic; | |
164 | Error : out std_logic |
|
183 | Error : out std_logic | |
165 | ); |
|
184 | ); | |
166 | end component; |
|
185 | end component; | |
167 |
|
186 | |||
168 |
|
187 | |||
169 | component DriveInputs is |
|
188 | component DriveInputs is | |
170 | port( |
|
189 | port( | |
171 | clk : in std_logic; |
|
190 | clk : in std_logic; | |
172 | raz : in std_logic; |
|
191 | raz : in std_logic; | |
173 | Read : in std_logic; |
|
192 | Read : in std_logic; | |
174 | Conjugate : in std_logic; |
|
193 | Conjugate : in std_logic; | |
175 | Take : out std_logic; |
|
194 | Take : out std_logic; | |
176 | ReadFIFO : out std_logic_vector(1 downto 0) |
|
195 | ReadFIFO : out std_logic_vector(1 downto 0) | |
177 | ); |
|
196 | ); | |
178 | end component; |
|
197 | end component; | |
179 |
|
198 | |||
180 | component Starter is |
|
199 | component Starter is | |
181 | port( |
|
200 | port( | |
182 | clk : in std_logic; |
|
201 | clk : in std_logic; | |
183 | raz : in std_logic; |
|
202 | raz : in std_logic; | |
184 | Full : in std_logic_vector(1 downto 0); |
|
203 | Full : in std_logic_vector(1 downto 0); | |
185 | Empty : in std_logic_vector(1 downto 0); |
|
204 | Empty : in std_logic_vector(1 downto 0); | |
186 | Statu : in std_logic_vector(3 downto 0); |
|
205 | Statu : in std_logic_vector(3 downto 0); | |
187 | Write : in std_logic; |
|
206 | Write : in std_logic; | |
188 | Start : out std_logic |
|
207 | Start : out std_logic | |
189 | ); |
|
208 | ); | |
190 | end component; |
|
209 | end component; | |
191 |
|
210 | |||
192 | component ALU_Driver is |
|
211 | component ALU_Driver is | |
193 | generic( |
|
212 | generic( | |
194 | Input_SZ_1 : integer := 16; |
|
213 | Input_SZ_1 : integer := 16; | |
195 | Input_SZ_2 : integer := 16); |
|
214 | Input_SZ_2 : integer := 16); | |
196 | port( |
|
215 | port( | |
197 | clk : in std_logic; |
|
216 | clk : in std_logic; | |
198 | reset : in std_logic; |
|
217 | reset : in std_logic; | |
199 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
218 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); | |
200 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
219 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); | |
201 | Take : in std_logic; |
|
220 | Take : in std_logic; | |
202 | Received : in std_logic; |
|
221 | Received : in std_logic; | |
203 | Conjugate : in std_logic; |
|
222 | Conjugate : in std_logic; | |
204 | Valid : out std_logic; |
|
223 | Valid : out std_logic; | |
205 | Read : out std_logic; |
|
224 | Read : out std_logic; | |
206 | CTRL : out std_logic_vector(4 downto 0); |
|
225 | CTRL : out std_logic_vector(4 downto 0); | |
207 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); |
|
226 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); | |
208 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) |
|
227 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) | |
209 | ); |
|
228 | ); | |
210 | end component; |
|
229 | end component; | |
211 |
|
230 | |||
212 |
|
231 | |||
213 | component ALU_v2 is |
|
232 | component ALU_v2 is | |
214 | generic( |
|
233 | generic( | |
215 | Arith_en : integer := 1; |
|
234 | Arith_en : integer := 1; | |
216 | Logic_en : integer := 1; |
|
235 | Logic_en : integer := 1; | |
217 | Input_SZ_1 : integer := 16; |
|
236 | Input_SZ_1 : integer := 16; | |
218 | Input_SZ_2 : integer := 9); |
|
237 | Input_SZ_2 : integer := 9); | |
219 | port( |
|
238 | port( | |
220 | clk : in std_logic; |
|
239 | clk : in std_logic; | |
221 | reset : in std_logic; |
|
240 | reset : in std_logic; | |
222 | ctrl : in std_logic_vector(4 downto 0); |
|
241 | ctrl : in std_logic_vector(4 downto 0); | |
223 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
242 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); | |
224 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
243 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); | |
225 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) |
|
244 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) | |
226 | ); |
|
245 | ); | |
227 | end component; |
|
246 | end component; | |
228 |
|
247 | |||
229 |
|
248 | |||
230 | component MAC_v2 is |
|
249 | component MAC_v2 is | |
231 | generic( |
|
250 | generic( | |
232 | Input_SZ_A : integer := 8; |
|
251 | Input_SZ_A : integer := 8; | |
233 | Input_SZ_B : integer := 8); |
|
252 | Input_SZ_B : integer := 8); | |
234 | port( |
|
253 | port( | |
235 | clk : in std_logic; |
|
254 | clk : in std_logic; | |
236 | reset : in std_logic; |
|
255 | reset : in std_logic; | |
237 | clr_MAC : in std_logic; |
|
256 | clr_MAC : in std_logic; | |
238 | MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); |
|
257 | MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); | |
239 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
258 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
240 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
259 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
241 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) |
|
260 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
242 | ); |
|
261 | ); | |
243 | end component; |
|
262 | end component; | |
244 |
|
263 | |||
245 |
|
264 | |||
246 | component TwoComplementer is |
|
265 | component TwoComplementer is | |
247 | generic( |
|
266 | generic( | |
248 | Input_SZ : integer := 16); |
|
267 | Input_SZ : integer := 16); | |
249 | port( |
|
268 | port( | |
250 | clk : in std_logic; |
|
269 | clk : in std_logic; | |
251 | reset : in std_logic; |
|
270 | reset : in std_logic; | |
252 | clr : in std_logic; |
|
271 | clr : in std_logic; | |
253 | TwoComp : in std_logic; |
|
272 | TwoComp : in std_logic; | |
254 | OP : in std_logic_vector(Input_SZ-1 downto 0); |
|
273 | OP : in std_logic_vector(Input_SZ-1 downto 0); | |
255 | RES : out std_logic_vector(Input_SZ-1 downto 0) |
|
274 | RES : out std_logic_vector(Input_SZ-1 downto 0) | |
256 | ); |
|
275 | ); | |
257 | end component; |
|
276 | end component; | |
258 |
|
277 | |||
259 | end; No newline at end of file |
|
278 | end; |
General Comments 0
You need to be logged in to leave comments.
Login now