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1 | #include <stdio.h> | |
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2 | #include "lpp_apb_functions.h" | |
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3 | #include "apb_fifo_Driver.h" | |
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4 | #include "apb_uart_Driver.h" | |
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5 | ||
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6 | ||
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7 | int main() | |
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8 | { | |
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9 | int i=0; | |
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10 | int data; | |
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11 | char temp[256]; | |
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12 | ||
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13 | int TblSinA[256] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255} ; | |
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14 | int TblSinAB[256] = {255,254,253,252,251,250,249,248,247,246,245,244,243,242,241,240,239,238,237,236,235,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,218,217,216,215,214,213,212,211,210,209,208,207,206,205,204,203,202,201,200,199,198,197,196,195,194,193,192,191,190,189,188,187,186,185,184,183,182,181,180,179,178,177,176,175,174,173,172,171,170,169,168,167,166,165,164,163,162,161,160,159,158,157,156,155,154,153,152,151,150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135,134,133,132,131,130,129,128,127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112,111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96,95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80,79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0} ; | |
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15 | int TblSinB[256] = {100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100} ; | |
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16 | int TblSinBC[256] = {128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,255,254,253,252,251,250,249,248,247,246,245,244,243,242,241,240,239,238,237,236,235,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,218,217,216,215,214,213,212,211,210,209,208,207,206,205,204,203,202,201,200,199,198,197,196,195,194,193,192,191,190,189,188,187,186,185,184,183,182,181,180,179,178,177,176,175,174,173,172,171,170,169,168,167,166,165,164,163,162,161,160,159,158,157,156,155,154,153,152,151,150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135,134,133,132,131,130,129} ; | |
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17 | int TblSinC[256] = {128,127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112,111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96,95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80,79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127} ; | |
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18 | ||
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19 | UART_Device* uart0 = openUART(0); | |
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20 | FIFO_Device* fifotry = openFIFO(0); | |
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21 | FIFO_Device* fifoIn = openFIFO(1); | |
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22 | FIFO_Device* fifoOut = openFIFO(2); | |
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23 | ||
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24 | printf("\nDebut Main\n\n"); | |
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25 | ||
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26 | FillFifo(fifoIn,0,TblSinA,256); | |
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27 | fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); | |
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28 | ||
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29 | FillFifo(fifoIn,1,TblSinAB,256); | |
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30 | fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); | |
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31 | ||
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32 | FillFifo(fifoIn,2,TblSinB,256); | |
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33 | fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); | |
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34 | ||
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35 | FillFifo(fifoIn,3,TblSinBC,256); | |
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36 | fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); | |
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37 | ||
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38 | FillFifo(fifoIn,4,TblSinC,256); | |
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39 | fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); | |
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40 | ||
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41 | ||
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42 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |
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43 | printf("\nFull 1\n"); | |
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44 | while((fifoOut->FIFOreg[(2*1)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |
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45 | printf("\nFull 2\n"); | |
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46 | ||
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47 | while(1){ | |
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48 | ||
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49 | sprintf(temp,"PONG A\n\r"); | |
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50 | uartputs(uart0,temp); | |
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51 | ||
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52 | while(i<257){ | |
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53 | data = (fifoOut->FIFOreg[(2*0)+FIFO_RWdata]); | |
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54 | i++; | |
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55 | sprintf(temp,"%d\n\r",data); | |
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56 | uartputs(uart0,temp); | |
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57 | } | |
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58 | ||
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59 | i=0; | |
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60 | sprintf(temp,"PONG B\n\r"); | |
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61 | uartputs(uart0,temp); | |
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62 | ||
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63 | while(i<257){ | |
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64 | data = (fifoOut->FIFOreg[(2*1)+FIFO_RWdata]); | |
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65 | i++; | |
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66 | sprintf(temp,"%d\n\r",data); | |
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67 | uartputs(uart0,temp); | |
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68 | } | |
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69 | ||
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70 | i=0; | |
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71 | } | |
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72 | printf("\nFin Main\n\n"); | |
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73 | return 0; | |
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74 | } |
@@ -0,0 +1,198 | |||
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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
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14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
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16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------- | |
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19 | -- Author : Martin Morlot | |
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20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
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21 | ------------------------------------------------------------------------------- | |
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22 | library IEEE; | |
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23 | use IEEE.numeric_std.all; | |
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24 | use IEEE.std_logic_1164.all; | |
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25 | ||
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26 | entity TopSpecMatrix is | |
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27 | generic( | |
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28 | Input_SZ : integer := 16); | |
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29 | port( | |
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30 | clk : in std_logic; | |
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31 | rstn : in std_logic; | |
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32 | Write : in std_logic; | |
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33 | ReadIn : in std_logic_vector(1 downto 0); | |
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34 | Full : in std_logic_vector(4 downto 0); | |
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35 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
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36 | Start : out std_logic; | |
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37 | ReadOut : out std_logic_vector(4 downto 0); | |
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38 | Statu : out std_logic_vector(3 downto 0); | |
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39 | DATA1 : out std_logic_vector(Input_SZ-1 downto 0); | |
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40 | DATA2 : out std_logic_vector(Input_SZ-1 downto 0) | |
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41 | ); | |
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42 | end entity; | |
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43 | ||
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44 | architecture ar_TopSpecMatrix of TopSpecMatrix is | |
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45 | ||
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46 | type etat is (eX,e0,e1,e2); | |
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47 | signal ect : etat; | |
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48 | ||
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49 | signal DataCount : integer range 0 to 256 := 0; | |
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50 | signal StatuINT : integer range 1 to 15 := 1; | |
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51 | ||
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52 | signal Write_reg : std_logic; | |
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53 | signal Full_int : std_logic_vector(1 downto 0); | |
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54 | ||
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55 | begin | |
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56 | process(clk,rstn) | |
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57 | begin | |
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58 | ||
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59 | if(rstn='0')then | |
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60 | DataCount <= 0; | |
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61 | StatuINT <= 1; | |
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62 | Write_reg <= '0'; | |
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63 | Start <= '0'; | |
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64 | ect <= e0; | |
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65 | ||
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66 | elsif(clk'event and clk='1')then | |
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67 | Write_reg <= Write; | |
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68 | ||
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69 | if(Write_reg='1' and Write='0')then | |
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70 | if(DataCount=256)then | |
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71 | DataCount <= 0; | |
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72 | else | |
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73 | DataCount <= DataCount + 1; | |
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74 | end if; | |
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75 | end if; | |
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76 | ||
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77 | ||
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78 | case ect is | |
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79 | ||
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80 | when e0 => | |
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81 | if(Full_int = "11")then | |
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82 | Start <= '1'; | |
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83 | if(StatuINT=1 or StatuINT=3 or StatuINT=6 or StatuINT=10 or StatuINT=15)then | |
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84 | ect <= e1; | |
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85 | else | |
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86 | ect <= e2; | |
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87 | end if; | |
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88 | end if; | |
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89 | ||
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90 | when e1 => | |
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91 | if(DataCount=128)then | |
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92 | if(StatuINT=15)then | |
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93 | StatuINT <= 1; | |
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94 | else | |
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95 | StatuINT <= StatuINT + 1; | |
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96 | end if; | |
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97 | DataCount <= 0; | |
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98 | Start <= '0'; | |
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99 | ect <= e0; | |
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100 | end if; | |
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101 | ||
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102 | when e2 => | |
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103 | if(DataCount=256)then | |
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104 | DataCount <= 0; | |
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105 | StatuINT <= StatuINT + 1; | |
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106 | Start <= '0'; | |
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107 | ect <= e0; | |
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108 | end if; | |
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109 | ||
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110 | when others => | |
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111 | null; | |
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112 | ||
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113 | end case; | |
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114 | end if; | |
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115 | end process; | |
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116 | ||
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117 | Statu <= std_logic_vector(to_unsigned(StatuINT,4)); | |
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118 | ||
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119 | with StatuINT select | |
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120 | DATA1 <= Data(15 downto 0) when 1, | |
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121 | Data(15 downto 0) when 2, | |
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122 | Data(31 downto 16) when 3, | |
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123 | Data(15 downto 0) when 4, | |
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124 | Data(31 downto 16) when 5, | |
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125 | Data(47 downto 32) when 6, | |
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126 | Data(15 downto 0) when 7, | |
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127 | Data(31 downto 16) when 8, | |
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128 | Data(47 downto 32) when 9, | |
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129 | Data(63 downto 48) when 10, | |
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130 | Data(15 downto 0) when 11, | |
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131 | Data(31 downto 16) when 12, | |
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132 | Data(47 downto 32) when 13, | |
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133 | Data(63 downto 48) when 14, | |
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134 | Data(79 downto 64) when 15, | |
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135 | X"0000" when others; | |
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136 | ||
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137 | ||
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138 | with StatuINT select | |
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139 | DATA2 <= (others => '0') when 1, | |
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140 | Data(31 downto 16) when 2, | |
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141 | (others => '0') when 3, | |
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142 | Data(47 downto 32) when 4, | |
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143 | Data(47 downto 32) when 5, | |
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144 | (others => '0') when 6, | |
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145 | Data(63 downto 48) when 7, | |
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146 | Data(63 downto 48) when 8, | |
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147 | Data(63 downto 48) when 9, | |
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148 | (others => '0') when 10, | |
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149 | Data(79 downto 64) when 11, | |
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150 | Data(79 downto 64) when 12, | |
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151 | Data(79 downto 64) when 13, | |
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152 | Data(79 downto 64) when 14, | |
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153 | (others => '0') when 15, | |
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154 | X"0000" when others; | |
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155 | ||
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156 | with StatuINT select | |
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157 | ReadOut <= "1111" & not READin(0) when 1, | |
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158 | "111" & not READin(1) & not READin(0) when 2, | |
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159 | "111" & not READin(0) & '1' when 3, | |
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160 | "11" & not READin(1) & '1' & not READin(0) when 4, | |
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161 | "11" & not READin(1) & not READin(0) & '1' when 5, | |
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162 | "11" & not READin(0) & "11" when 6, | |
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163 | "1" & not READin(1) & "11" & not READin(0) when 7, | |
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164 | '1' & not READin(1) & '1' & not READin(0) & '1' when 8, | |
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165 | '1' & not READin(1) & not READin(0) & "11" when 9, | |
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166 | '1' & not READin(0) & "111" when 10, | |
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167 | not READin(1) & "111" & not READin(0) when 11, | |
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168 | not READin(1) & "11" & not READin(0) & '1' when 12, | |
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169 | not READin(1) & '1' & not READin(0) & "11" when 13, | |
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170 | not READin(1) & not READin(0) & "111" when 14, | |
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171 | not READin(0) & "1111" when 15, | |
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172 | "11111" when others; | |
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173 | ||
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174 | with StatuINT select | |
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175 | Full_int <= Full(0) & Full(0) when 1, | |
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176 | Full(1) & Full(0) when 2, | |
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177 | Full(1) & Full(1) when 3, | |
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178 | Full(2) & Full(0) when 4, | |
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179 | Full(2) & Full(1) when 5, | |
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180 | Full(2) & Full(2) when 6, | |
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181 | Full(3) & Full(0) when 7, | |
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182 | Full(3) & Full(1) when 8, | |
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183 | Full(3) & Full(2) when 9, | |
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184 | Full(3) & Full(3) when 10, | |
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185 | Full(4) & Full(0) when 11, | |
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186 | Full(4) & Full(1) when 12, | |
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187 | Full(4) & Full(2) when 13, | |
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188 | Full(4) & Full(3) when 14, | |
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189 | Full(4) & Full(4) when 15, | |
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190 | "00" when others; | |
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191 | ||
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192 | end architecture; | |
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193 | ||
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194 | ||
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195 | ||
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196 | ||
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197 | ||
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198 |
@@ -1,80 +1,73 | |||
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1 | 1 | #include <stdio.h> |
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2 | 2 | #include "lpp_apb_functions.h" |
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3 | 3 | #include "apb_fifo_Driver.h" |
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4 | 4 | #include "apb_uart_Driver.h" |
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5 | #include "apb_delay_Driver.h" | |
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6 | #include "apb_fft_Driver.h" | |
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7 | ||
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8 | 5 | |
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9 | 6 | int main() |
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10 | 7 | { |
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11 | int i; | |
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12 |
int data |
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8 | int i=0; | |
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9 | int data; | |
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13 | 10 | char temp[256]; |
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14 | int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; | |
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15 | int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; | |
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16 | int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD} ; | |
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17 | 11 | |
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18 | /* int TblSin5K[256] = {0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872,0xD0E1,0xC980,0xC256,0xBB6A,0xB4C3,0xAE69,0xA861,0xA2B1,0x9D60,0x9872,0x93ED,0x8FD5,0x8C2F,0x88FD,0x8644,0x8405,0x8244,0x8102,0x8041,0x8000,0x8041,0x8102,0x8244,0x8405,0x8644,0x88FD,0x8C2F,0x8FD5,0x93ED,0x9872,0x9D60,0xA2B1,0xA861,0xAE69,0xB4C3,0xBB6A,0xC256,0xC980,0xD0E1,0xD872,0xE02B,0xE804,0xEFF5,0xF7F6,0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872,0xD0E1,0xC980,0xC256,0xBB6A,0xB4C3,0xAE69,0xA861,0xA2B1,0x9D60,0x9872,0x93ED,0x8FD5,0x8C2F,0x88FD,0x8644,0x8405,0x8244,0x8102,0x8041,0x8000,0x8041,0x8102,0x8244,0x8405,0x8644,0x88FD,0x8C2F,0x8FD5,0x93ED,0x9872,0x9D60,0xA2B1,0xA861,0xAE69,0xB4C3,0xBB6A,0xC256,0xC980,0xD0E1,0xD872,0xE02B,0xE804,0xEFF5,0xF7F6,0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872}; | |
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19 | int TblSin8K[256] = {0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA,0x489C,0x52D3,0x5C33,0x64A5,0x6C13,0x7269,0x7798,0x7B92,0x7E4C,0x7FBF,0x7FE9,0x7EC7,0x7C5E,0x78B4,0x73D1,0x6DC3,0x669A,0x5E67,0x5540,0x4B3D,0x4077,0x350A,0x2915,0x1CB5,0x100B,0x0337,0xF65C,0xE999,0xDD10,0xD0E1,0xC52C,0xBA10,0xAFA8,0xA610,0x9D60,0x95AF,0x8F11,0x8997,0x854F,0x8244,0x807F,0x8003,0x80D1,0x82E9,0x8644,0x8AD9,0x909E,0x9782,0x9F75,0xA861,0xB22F,0xBCC7,0xC80D,0xD3E3,0xE02B,0xECC5,0xF992,0x066E,0x133B,0x1FD5,0x2C1D,0x37F3,0x4339,0x4DD1,0x579F,0x608B,0x687E,0x6F62,0x7527,0x79BC,0x7D17,0x7F2F,0x7FFD,0x7F81,0x7DBC,0x7AB1,0x7669,0x70EF,0x6A51,0x62A0,0x59F0,0x5058,0x45F0,0x3AD4,0x2F1F,0x22F0,0x1667,0x09A4,0xFCC9,0xEFF5,0xE34B,0xD6EB,0xCAF6,0xBF89,0xB4C3,0xAAC0,0xA199,0x9966,0x923D,0x8C2F,0x874C,0x83A2,0x8139,0x8017,0x8041,0x81B4,0x846E,0x8868,0x8D97,0x93ED,0x9B5B,0xA3CD,0xAD2D,0xB764,0xC256,0xCDE7,0xD9FB,0xE670,0xF327,0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA,0x489C,0x52D3,0x5C33,0x64A5,0x6C13,0x7269,0x7798,0x7B92,0x7E4C,0x7FBF,0x7FE9,0x7EC7,0x7C5E,0x78B4,0x73D1,0x6DC3,0x669A,0x5E67,0x5540,0x4B3D,0x4077,0x350A,0x2915,0x1CB5,0x100B,0x0337,0xF65C,0xE999,0xDD10,0xD0E1,0xC52C,0xBA10,0xAFA8,0xA610,0x9D60,0x95AF,0x8F11,0x8997,0x854F,0x8244,0x807F,0x8003,0x80D1,0x82E9,0x8644,0x8AD9,0x909E,0x9782,0x9F75,0xA861,0xB22F,0xBCC7,0xC80D,0xD3E3,0xE02B,0xECC5,0xF992,0x066E,0x133B,0x1FD5,0x2C1D,0x37F3,0x4339,0x4DD1,0x579F,0x608B,0x687E,0x6F62,0x7527,0x79BC,0x7D17,0x7F2F,0x7FFD,0x7F81,0x7DBC,0x7AB1,0x7669,0x70EF,0x6A51,0x62A0,0x59F0,0x5058,0x45F0,0x3AD4,0x2F1F,0x22F0,0x1667,0x09A4,0xFCC9,0xEFF5,0xE34B,0xD6EB,0xCAF6,0xBF89,0xB4C3,0xAAC0,0xA199,0x9966,0x923D,0x8C2F,0x874C,0x83A2,0x8139,0x8017,0x8041,0x81B4,0x846E,0x8868,0x8D97,0x93ED,0x9B5B,0xA3CD,0xAD2D,0xB764,0xC256,0xCDE7,0xD9FB,0xE670,0xF327,0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA}; | |
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20 | int TblSin11K[256] = {0x0000,0x11A3,0x22F0,0x3392,0x4339,0x5197,0x5E67,0x696A,0x7269,0x793B,0x7DBC,0x7FD7,0x7F81,0x7CBD,0x7798,0x702B,0x669A,0x5B14,0x4DD1,0x3F12,0x2F1F,0x1E46,0x0CD9,0xFB2D,0xE999,0xD872,0xC80D,0xB8B8,0xAAC0,0x9E68,0x93ED,0x8B82,0x854F,0x8174,0x8003,0x8102,0x846E,0x8A36,0x923D,0x9C5B,0xA861,0xB612,0xC52C,0xD566,0xE670,0xF7F6,0x09A4,0x1B23,0x2C1D,0x3C40,0x4B3D,0x58CA,0x64A5,0x6E95,0x7669,0x7BFB,0x7F2F,0x7FF6,0x7E4C,0x7A39,0x73D1,0x6B34,0x608B,0x540B,0x45F0,0x3680,0x2605,0x14D1,0x0337,0xF18E,0xE02B,0xCF63,0xBF89,0xB0EA,0xA3CD,0x9872,0x8F11,0x87D8,0x82E9,0x805D,0x8041,0x8294,0x874C,0x8E52,0x9782,0xA2B1,0xAFA8,0xBE27,0xCDE7,0xDE9D,0xEFF5,0x019C,0x133B,0x247C,0x350A,0x4496,0x52D3,0x5F7B,0x6A51,0x7320,0x79BC,0x7E06,0x7FE9,0x7F5B,0x7C5E,0x7703,0x6F62,0x65A1,0x59F0,0x4C88,0x3DAA,0x2D9F,0x1CB5,0x0B3F,0xF992,0xE804,0xD6EB,0xC69B,0xB764,0xA98F,0x9D60,0x9313,0x8AD9,0x84DC,0x8139,0x8000,0x8139,0x84DC,0x8AD9,0x9313,0x9D60,0xA98F,0xB764,0xC69B,0xD6EB,0xE804,0xF992,0x0B3F,0x1CB5,0x2D9F,0x3DAA,0x4C88,0x59F0,0x65A1,0x6F62,0x7703,0x7C5E,0x7F5B,0x7FE9,0x7E06,0x79BC,0x7320,0x6A51,0x5F7B,0x52D3,0x4496,0x350A,0x247C,0x133B,0x019C,0xEFF5,0xDE9D,0xCDE7,0xBE27,0xAFA8,0xA2B1,0x9782,0x8E52,0x874C,0x8294,0x8041,0x805D,0x82E9,0x87D8,0x8F11,0x9872,0xA3CD,0xB0EA,0xBF89,0xCF63,0xE02B,0xF18E,0x0337,0x14D1,0x2605,0x3680,0x45F0,0x540B,0x608B,0x6B34,0x73D1,0x7A39,0x7E4C,0x7FF6,0x7F2F,0x7BFB,0x7669,0x6E95,0x64A5,0x58CA,0x4B3D,0x3C40,0x2C1D,0x1B23,0x09A4,0xF7F6,0xE670,0xD566,0xC52C,0xB612,0xA861,0x9C5B,0x923D,0x8A36,0x846E,0x8102,0x8003,0x8174,0x854F,0x8B82,0x93ED,0x9E68,0xAAC0,0xB8B8,0xC80D,0xD872,0xE999,0xFB2D,0x0CD9,0x1E46,0x2F1F,0x3F12,0x4DD1,0x5B14,0x669A,0x702B,0x7798,0x7CBD,0x7F81,0x7FD7,0x7DBC,0x793B,0x7269,0x696A,0x5E67,0x5197,0x4339,0x3392,0x22F0,0x11A3,0x0000,0xEE5D,0xDD10,0xCC6E,0xBCC7,0xAE69}; | |
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21 | */ int TblSin15K[256] = {0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872,0x8C2F,0x8405,0x8041,0x8102,0x8644,0x8FD5,0x9D60,0xAE69,0xC256,0xD872,0xEFF5,0x080A,0x1FD5,0x3680,0x4B3D,0x5D4F,0x6C13,0x7703,0x7DBC,0x8000,0x7DBC,0x7703,0x6C13,0x5D4F,0x4B3D,0x3680,0x1FD5,0x080A,0xEFF5,0xD872,0xC256,0xAE69,0x9D60,0x8FD5,0x8644,0x8102,0x8041,0x8405,0x8C2F,0x9872,0xA861,0xBB6A,0xD0E1,0xE804,0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872,0x8C2F,0x8405,0x8041,0x8102,0x8644,0x8FD5,0x9D60,0xAE69,0xC256,0xD872,0xEFF5,0x080A,0x1FD5,0x3680,0x4B3D,0x5D4F,0x6C13,0x7703,0x7DBC,0x8000,0x7DBC,0x7703,0x6C13,0x5D4F,0x4B3D,0x3680,0x1FD5,0x080A,0xEFF5,0xD872,0xC256,0xAE69,0x9D60,0x8FD5,0x8644,0x8102,0x8041,0x8405,0x8C2F,0x9872,0xA861,0xBB6A,0xD0E1,0xE804,0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872}; | |
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22 | int TblSin19K[256] = {0x0000,0x1E46,0x3AD4,0x540B,0x687E,0x7703,0x7EC7,0x7F5B,0x78B4,0x6B34,0x579F,0x3F12,0x22F0,0x04D3,0xE670,0xC980,0xAFA8,0x9A5F,0x8AD9,0x81FA,0x8041,0x85C7,0x923D,0xA4EC,0xBCC7,0xD872,0xF65C,0x14D1,0x3219,0x4C88,0x62A0,0x7320,0x7D17,0x7FF6,0x7B92,0x702B,0x5E67,0x4748,0x2C1D,0x0E72,0xEFF5,0xD261,0xB764,0xA085,0x8F11,0x8405,0x8003,0x8343,0x8D97,0x9E68,0xB4C3,0xCF63,0xECC5,0x0B3F,0x2915,0x4496,0x5C33,0x6E95,0x7AB1,0x7FD7,0x7DBC,0x747E,0x64A5,0x4F16,0x350A,0x17FC,0xF992,0xDB84,0xBF89,0xA736,0x93ED,0x86C5,0x807F,0x8174,0x8997,0x9872,0xAD2D,0xC69B,0xE34B,0x019C,0x1FD5,0x3C40,0x5540,0x696A,0x7798,0x7EFE,0x7F2F,0x7828,0x6A51,0x5671,0x3DAA,0x2163,0x0337,0xE4DD,0xC80D,0xAE69,0x9966,0x8A36,0x81B4,0x805D,0x8644,0x9313,0xA610,0xBE27,0xD9FB,0xF7F6,0x1667,0x3392,0x4DD1,0x63A5,0x73D1,0x7D6C,0x7FE9,0x7B24,0x6F62,0x5D4F,0x45F0,0x2A9A,0x0CD9,0xEE5D,0xD0E1,0xB612,0x9F75,0x8E52,0x83A2,0x8000,0x83A2,0x8E52,0x9F75,0xB612,0xD0E1,0xEE5D,0x0CD9,0x2A9A,0x45F0,0x5D4F,0x6F62,0x7B24,0x7FE9,0x7D6C,0x73D1,0x63A5,0x4DD1,0x3392,0x1667,0xF7F6,0xD9FB,0xBE27,0xA610,0x9313,0x8644,0x805D,0x81B4,0x8A36,0x9966,0xAE69,0xC80D,0xE4DD,0x0337,0x2163,0x3DAA,0x5671,0x6A51,0x7828,0x7F2F,0x7EFE,0x7798,0x696A,0x5540,0x3C40,0x1FD5,0x019C,0xE34B,0xC69B,0xAD2D,0x9872,0x8997,0x8174,0x807F,0x86C5,0x93ED,0xA736,0xBF89,0xDB84,0xF992,0x17FC,0x350A,0x4F16,0x64A5,0x747E,0x7DBC,0x7FD7,0x7AB1,0x6E95,0x5C33,0x4496,0x2915,0x0B3F,0xECC5,0xCF63,0xB4C3,0x9E68,0x8D97,0x8343,0x8003,0x8405,0x8F11,0xA085,0xB764,0xD261,0xEFF5,0x0E72,0x2C1D,0x4748,0x5E67,0x702B,0x7B92,0x7FF6,0x7D17,0x7320,0x62A0,0x4C88,0x3219,0x14D1,0xF65C,0xD872,0xBCC7,0xA4EC,0x923D,0x85C7,0x8041,0x81FA,0x8AD9,0x9A5F,0xAFA8,0xC980,0xE670,0x04D3,0x22F0,0x3F12,0x579F,0x6B34,0x78B4,0x7F5B,0x7EC7,0x7703,0x687E,0x540B,0x3AD4,0x1E46,0x0000,0xE1BA,0xC52C,0xABF5,0x9782,0x88FD}; | |
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23 | int Table[256]; | |
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12 | int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; | |
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13 | int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD}; | |
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14 | int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; | |
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15 | int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C}; | |
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16 | int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E}; | |
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24 | 17 | |
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25 |
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26 |
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27 |
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28 |
FIFO_Device* fifo |
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29 | FIFO_Device* fifoOut = openFIFO(1); | |
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18 | UART_Device* uart0 = openUART(0); | |
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19 | FIFO_Device* fifotry = openFIFO(0); | |
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20 | FIFO_Device* fifoIn = openFIFO(1); | |
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21 | FIFO_Device* fifoOut = openFIFO(2); | |
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30 | 22 | |
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31 | 23 | printf("\nDebut Main\n\n"); |
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32 | 24 | |
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33 | Setup(delay,30000000); | |
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34 | ||
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35 | FftInput(TblSinA,fft0,delay); | |
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36 | FftOutput(Table,fft0); | |
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37 | /*for (i = 0 ; i < 256 ; i=i+2) | |
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38 | { | |
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39 | sprintf(temp,"%x\t%x\n\r",Table[i],Table[i+1]); | |
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40 | uartputs(uart0,temp); | |
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41 | }*/ | |
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42 | FillFifo(fifoIn,0,Table); | |
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25 | FillFifo(fifoIn,0,TblSinA,256); | |
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43 | 26 | fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); |
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44 | 27 | |
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45 | FftInput(TblSinAB,fft0,delay); | |
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46 | FftOutput(Table,fft0); | |
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47 | FillFifo(fifoIn,1,Table); | |
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28 | FillFifo(fifoIn,1,TblSinAB,256); | |
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48 | 29 | fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); |
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49 | 30 | |
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50 | FftInput(TblSinB,fft0,delay); | |
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51 | FftOutput(Table,fft0); | |
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52 | FillFifo(fifoIn,2,Table); | |
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31 | FillFifo(fifoIn,2,TblSinB,256); | |
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53 | 32 | fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); |
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54 | 33 | |
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55 | FftInput(TblSin15K,fft0,delay); | |
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56 | FftOutput(Table,fft0); | |
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57 | FillFifo(fifoIn,3,Table); | |
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34 | FillFifo(fifoIn,3,TblSinBC,256); | |
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58 | 35 | fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); |
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59 | 36 | |
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60 | FftInput(TblSin19K,fft0,delay); | |
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61 | FftOutput(Table,fft0); | |
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62 | FillFifo(fifoIn,4,Table); | |
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37 | FillFifo(fifoIn,4,TblSinC,256); | |
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63 | 38 | fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); |
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64 | printf("ok"); | |
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65 | while(1){ | |
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39 | ||
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40 | ||
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41 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |
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42 | printf("\nFull 1\n"); | |
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43 | while((fifoOut->FIFOreg[(2*1)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |
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44 | printf("\nFull 2\n"); | |
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45 | ||
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46 | while(1){ | |
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47 | ||
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48 | sprintf(temp,"PONG A\n\r"); | |
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49 | uartputs(uart0,temp); | |
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66 | 50 | |
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67 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN | |
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51 | while(i<257){ | |
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52 | data = (fifoOut->FIFOreg[(2*0)+FIFO_RWdata]); | |
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53 | i++; | |
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54 | sprintf(temp,"%d\n\r",data); | |
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55 | uartputs(uart0,temp); | |
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56 | } | |
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68 | 57 | |
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69 | data1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |
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70 | data2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |
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58 | i=0; | |
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59 | sprintf(temp,"PONG B\n\r"); | |
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60 | uartputs(uart0,temp); | |
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71 | 61 | |
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72 | sprintf(temp,"%d\t%d\n\r",data1,data2); | |
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62 | while(i<257){ | |
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63 | data = (fifoOut->FIFOreg[(2*1)+FIFO_RWdata]); | |
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64 | i++; | |
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65 | sprintf(temp,"%d\n\r",data); | |
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73 | 66 | uartputs(uart0,temp); |
|
67 | } | |
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68 | ||
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69 | i=0; | |
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74 | 70 | } |
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75 | 71 | printf("\nFin Main\n\n"); |
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76 | 72 | return 0; |
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77 | 73 | } |
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78 | ||
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79 | ||
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80 |
@@ -1,44 +1,44 | |||
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1 | 1 | #------------------------------------------------------------------------------ |
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2 | 2 | #-- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | #-- |
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5 | 5 | #-- This program is free software; you can redistribute it and/or modify |
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6 | 6 | #-- it under the terms of the GNU General Public License as published by |
|
7 | 7 | #-- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | #-- (at your option) any later version. |
|
9 | 9 | #-- |
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10 | 10 | #-- This program is distributed in the hope that it will be useful, |
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11 | 11 | #-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | #-- GNU General Public License for more details. |
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14 | 14 | #-- |
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15 | 15 | #-- You should have received a copy of the GNU General Public License |
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16 | 16 | #-- along with this program; if not, write to the Free Software |
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17 | 17 | #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | #------------------------------------------------------------------------------ |
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19 | 19 | |
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20 | 20 | include ../../rules.mk |
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21 | 21 | LIBDIR = ../../lib |
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22 | 22 | INCPATH = ../../includes |
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23 | 23 | SCRIPTDIR=../../scripts/ |
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24 |
LIBS=-lapb_fft_Driver -llpp_apb_functions |
|
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24 | LIBS=-lapb_fifo_Driver -lapb_uart_Driver -llpp_apb_functions | |
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25 | 25 | INPUTFILE=main.c |
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26 | 26 | EXEC=BenchFFT.bin |
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27 | 27 | OUTBINDIR=bin/ |
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28 | 28 | |
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29 | 29 | |
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30 | 30 | .PHONY:bin |
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31 | 31 | |
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32 | 32 | all:bin |
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33 | 33 | @echo $(EXEC)" file created" |
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34 | 34 | |
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35 | 35 | clean: |
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36 | 36 | rm -f *.{o,a} |
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37 | 37 | |
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38 | 38 | |
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39 | 39 | |
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40 | 40 | help:ruleshelp |
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41 | 41 | @echo " all : makes an executable file called "$(EXEC) |
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42 | 42 | @echo " in "$(OUTBINDIR) |
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43 | 43 | @echo " clean : removes temporary files" |
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44 | 44 |
@@ -1,51 +1,51 | |||
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1 | 1 | #include <stdio.h> |
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2 | 2 | #include "lpp_apb_functions.h" |
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3 | 3 | #include "apb_fifo_Driver.h" |
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4 | 4 | #include "apb_uart_Driver.h" |
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5 | #include "TableTest.h" | |
|
5 | //#include "TableTest.h" | |
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6 | 6 | |
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7 | 7 | |
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8 | 8 | int main() |
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9 | 9 | { |
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10 | 10 | int i=0,j=0; |
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11 | 11 | int data1,data2; |
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12 | 12 | char temp[256]; |
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13 | 13 | |
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14 | 14 | int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; |
|
15 | 15 | int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD}; |
|
16 | 16 | int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; |
|
17 | 17 | int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C}; |
|
18 | 18 | int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E}; |
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19 | 19 | |
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20 | 20 | UART_Device* uart0 = openUART(0); |
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21 | 21 | FIFO_Device* fifotry = openFIFO(0); |
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22 | 22 | FIFO_Device* fifoIn = openFIFO(1); |
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23 | 23 | FIFO_Device* fifoOut = openFIFO(2); |
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24 | 24 | |
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25 | 25 | printf("\nDebut Main\n\n"); |
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26 | 26 | |
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27 | 27 | FillFifo(fifoIn,0,TblSinA,256); |
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28 | 28 | FillFifo(fifoIn,1,TblSinAB,256); |
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29 | 29 | FillFifo(fifoIn,2,TblSinB,256); |
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30 | 30 | FillFifo(fifoIn,3,TblSinBC,256); |
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31 | 31 | FillFifo(fifoIn,4,TblSinC,256); |
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32 | 32 | |
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33 | 33 | while(j<5){ |
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34 | 34 | while((fifoOut->FIFOreg[(2*j)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN |
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35 | 35 | |
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36 | 36 | sprintf(temp,"FIFO %d\n\r",j); |
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37 | 37 | uartputs(uart0,temp); |
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38 | 38 | //while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty){ // TANT QUE empty a 0 ALORS |
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39 | 39 | while(i < 128){ |
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40 | 40 | data1 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex; |
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41 | 41 | data2 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex; |
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42 | 42 | i++; |
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43 | 43 | sprintf(temp,"%d\t%d\n\r",data1,data2); |
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44 | 44 | uartputs(uart0,temp); |
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45 | 45 | } |
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46 | 46 | i=0; |
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47 | 47 | j++; |
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48 | 48 | } |
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49 | 49 | printf("\nFin Main\n\n"); |
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50 | 50 | return 0; |
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51 | 51 | } |
@@ -1,174 +1,174 | |||
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1 | 1 | #include <stdio.h> |
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2 | 2 | #include "lpp_apb_functions.h" |
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3 | 3 | #include "apb_fifo_Driver.h" |
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4 | 4 | #include "apb_Matrix_Driver.h" |
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5 | 5 | #include "apb_uart_Driver.h" |
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6 | 6 | #include "apb_gpio_Driver.h" |
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7 | 7 | |
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8 | 8 | ///////////// Matrix With 2 FIFO Input ///////////////////////////////////////////// |
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9 | 9 | int main() |
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10 | 10 | { |
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11 | 11 | int i=0,save; |
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12 | 12 | char temp[256]; |
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13 | 13 | int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; |
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14 | 14 | int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; |
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15 | 15 | int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; |
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16 | 16 | // int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; |
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17 | 17 | // int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; |
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18 | 18 | int Table[256]; |
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19 | 19 | |
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20 | 20 | |
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21 | 21 | FIFO_Device* fifoX = openFIFO(0); |
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22 | 22 | UART_Device* uart0 = openUART(0); |
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23 | 23 | FIFO_Device* fifoIn = openFIFO(1); |
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24 | 24 | MATRIX_Device* mspec = openMatrix(0); |
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25 | 25 | FIFO_Device* fifoOut = openFIFO(2); |
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26 | 26 | GPIO_Device* gpio0 = openGPIO(0); |
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27 | 27 | |
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28 | 28 | printf("\nDebut Main\n\n"); |
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29 | 29 | |
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30 | 30 | gpio0->oen = 0x3; |
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31 | 31 | gpio0->Dout = 0x0; |
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32 | 32 | |
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33 | 33 | /////////////////////////////////////////////////////////////////////////// |
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34 | 34 | mspec->Statu = 2; |
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35 | FillFifo(fifoIn,0,TblB1); | |
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36 | FillFifo(fifoIn,1,TblB2); | |
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35 | FillFifo(fifoIn,0,TblB1,256); | |
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36 | FillFifo(fifoIn,1,TblB2,256); | |
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37 | 37 | gpio0->Dout = 0x1; |
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38 | 38 | |
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39 | 39 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS |
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40 | 40 | { |
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41 | 41 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
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42 | 42 | i++; |
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43 | 43 | } |
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44 | 44 | save = i; |
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45 | 45 | gpio0->Dout = 0x2; |
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46 | 46 | |
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47 | 47 | sprintf(temp,"\nReels\tImaginaires\n\r"); |
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48 | 48 | uartputs(uart0,temp); |
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49 | 49 | for (i = 0 ; i < save ; i+=2) |
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50 | 50 | { |
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51 | 51 | sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); |
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52 | 52 | uartputs(uart0,temp); |
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53 | 53 | } |
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54 | 54 | i = 0; |
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55 | 55 | gpio0->Dout = 0x0; |
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56 | 56 | |
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57 | 57 | /////////////////////////////////////////////////////////////////////////// |
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58 | 58 | mspec->Statu = 1; |
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59 | FillFifo(fifoIn,0,TblB1); | |
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59 | FillFifo(fifoIn,0,TblB1,256); | |
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60 | 60 | gpio0->Dout = 0x1; |
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61 | 61 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS |
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62 | 62 | { |
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63 | 63 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
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64 | 64 | i++; |
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65 | 65 | } |
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66 | 66 | save = i; |
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67 | 67 | gpio0->Dout = 0x2; |
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68 | 68 | |
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69 | 69 | sprintf(temp,"\nReels\n\r"); |
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70 | 70 | uartputs(uart0,temp); |
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71 | 71 | for (i = 0 ; i < save ; i++) |
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72 | 72 | { |
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73 | 73 | sprintf(temp,"%d\n\r",Table[i]); |
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74 | 74 | uartputs(uart0,temp); |
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75 | 75 | } |
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76 | 76 | i = 0; |
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77 | 77 | gpio0->Dout = 0x0; |
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78 | 78 | |
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79 | 79 | /////////////////////////////////////////////////////////////////////////// |
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80 | 80 | mspec->Statu = 4; |
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81 | FillFifo(fifoIn,0,TblB1); | |
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82 | FillFifo(fifoIn,1,TblB3); | |
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81 | FillFifo(fifoIn,0,TblB1,256); | |
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82 | FillFifo(fifoIn,1,TblB3,256); | |
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83 | 83 | gpio0->Dout = 0x1; |
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84 | 84 | |
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85 | 85 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS |
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86 | 86 | { |
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87 | 87 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
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88 | 88 | i++; |
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89 | 89 | } |
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90 | 90 | save = i; |
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91 | 91 | gpio0->Dout = 0x2; |
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92 | 92 | |
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93 | 93 | sprintf(temp,"\nReels\tImaginaires\n\r"); |
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94 | 94 | uartputs(uart0,temp); |
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95 | 95 | for (i = 0 ; i < save ; i+=2) |
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96 | 96 | { |
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97 | 97 | sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); |
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98 | 98 | uartputs(uart0,temp); |
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99 | 99 | } |
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100 | 100 | i = 0; |
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101 | 101 | gpio0->Dout = 0x0; |
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102 | 102 | |
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103 | 103 | printf("\nFin Main\n\n"); |
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104 | 104 | return 0; |
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105 | 105 | } |
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106 | 106 | |
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107 | 107 | |
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108 | 108 | ///////////// Matrix With 5 FIFO Input ///////////////////////////////////////////// |
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109 | 109 | int main2() |
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110 | 110 | { |
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111 | 111 | int save1,save2; |
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112 | 112 | char temp[256]; |
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113 | 113 | int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; |
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114 | 114 | int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; |
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115 | 115 | int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; |
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116 | 116 | int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; |
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117 | 117 | int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; |
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118 | 118 | |
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119 | 119 | FIFO_Device* fifoX = openFIFO(0); |
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120 | 120 | UART_Device* uart0 = openUART(0); |
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121 | 121 | FIFO_Device* fifoIn = openFIFO(1); |
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122 | 122 | FIFO_Device* fifoOut = openFIFO(2); |
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123 | 123 | |
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124 | 124 | printf("\nDebut Main\n\n"); |
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125 | 125 | |
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126 | FillFifo(fifoIn,0,TblB1); | |
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126 | FillFifo(fifoIn,0,TblB1,256); | |
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127 | 127 | fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); |
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128 | 128 | |
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129 | FillFifo(fifoIn,1,TblB2); | |
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129 | FillFifo(fifoIn,1,TblB2,256); | |
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130 | 130 | fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); |
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131 | 131 | |
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132 | FillFifo(fifoIn,2,TblB3); | |
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132 | FillFifo(fifoIn,2,TblB3,256); | |
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133 | 133 | fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); |
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134 | 134 | |
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135 | FillFifo(fifoIn,3,TblE1); | |
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135 | FillFifo(fifoIn,3,TblE1,256); | |
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136 | 136 | fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); |
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137 | 137 | |
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138 | FillFifo(fifoIn,4,TblE2); | |
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138 | FillFifo(fifoIn,4,TblE2,256); | |
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139 | 139 | |
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140 | 140 | fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); |
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141 | 141 | |
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142 | 142 | while(1){ |
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143 | 143 | |
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144 | 144 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN |
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145 | 145 | |
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146 | 146 | save1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
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147 | 147 | save2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
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148 | 148 | |
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149 | 149 | sprintf(temp,"%d\t%d\n\r",save1,save2); |
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150 | 150 | uartputs(uart0,temp); |
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151 | 151 | } |
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152 | 152 | printf("\nFin Main\n\n"); |
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153 | 153 | return 0; |
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154 | 154 | } |
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155 | 155 | |
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156 | 156 | |
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157 | 157 | |
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158 | 158 | |
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159 | 159 | /////////////////// Test R/W Fifo OKAI /////////////////////////////////// |
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160 | 160 | |
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161 | 161 | /*fifoX->FIFOreg[(2*0)+FIFO_RWdata] = 0x11; |
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162 | 162 | Table[1] = fifoX->FIFOreg[(2*0)+FIFO_RWdata]; |
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163 | 163 | printf("data: %x\n",Table[1]); |
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164 | 164 | |
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165 | 165 | FillFifo(fifoX,0,TblX); |
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166 | 166 | for (i = 1 ; i < 8 ; i++) |
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167 | 167 | { |
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168 | 168 | Table[i] = fifoX->FIFOreg[(2*0)+FIFO_RWdata] & Mask_2hex; |
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169 | 169 | } |
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170 | 170 | printf("data: %x\n",Table[1]); |
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171 | 171 | printf("data: %x\n",Table[2]); |
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172 | 172 | printf("data: %x\n",Table[3]); |
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173 | 173 | printf("data: %x\n",Table[4]);*/ |
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174 | 174 |
@@ -1,76 +1,76 | |||
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1 | 1 | /*------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Martin Morlot |
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20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
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21 | 21 | -----------------------------------------------------------------------------*/ |
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22 | 22 | #ifndef APB_FIFO_DRIVER_H |
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23 | 23 | #define APB_FIFO_DRIVER_H |
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24 | 24 | |
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25 | 25 | /*! \file apb_fifo_Driver.h |
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26 | 26 | \brief LPP FIFO driver. |
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27 | 27 | |
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28 | 28 | This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, |
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29 | 29 | used in many type of application. |
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30 | 30 | |
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31 | 31 | \todo Check "DEVICE1 => count = 2" function Open |
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32 | 32 | \author Martin Morlot martin.morlot@lpp.polytechnique.fr |
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33 | 33 | */ |
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34 | 34 | #define FIFO_Ctrl 0 |
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35 | 35 | #define FIFO_RWdata 1 |
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36 | 36 | |
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37 | 37 | #define FIFO_Full 0x00010000 |
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38 | 38 | #define FIFO_Empty 0x00000001 |
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39 | 39 | #define FIFO_ReUse 0x00000002 |
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40 | 40 | |
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41 | 41 | #define Mask_2hex 0x000000FF |
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42 | 42 | #define Mask_4hex 0x0000FFFF |
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43 | 43 | |
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44 | 44 | |
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45 | 45 | /*=================================================== |
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46 | 46 | T Y P E S D E F |
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47 | 47 | ====================================================*/ |
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48 | 48 | |
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49 | 49 | /*! \struct APB_FIFO_REG |
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50 | 50 | \brief Sturcture representing the fifo registers |
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51 | 51 | */ |
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52 | 52 | struct APB_FIFO_REG |
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53 | 53 | { |
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54 | int IDreg; | |
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55 | int FIFOreg[2*8]; | |
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54 | volatile int IDreg; | |
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55 | volatile int FIFOreg[2*8]; | |
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56 | 56 | }; |
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57 | 57 | |
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58 | 58 | typedef volatile struct APB_FIFO_REG FIFO_Device; |
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59 | 59 | |
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60 | 60 | /*=================================================== |
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61 | 61 | F U N C T I O N S |
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62 | 62 | ====================================================*/ |
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63 | 63 | |
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64 | 64 | /*! \fn APB_FIFO_Device* apbfifoOpen(int count); |
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65 | 65 | \brief Return count FIFO. |
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66 | 66 | |
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67 | 67 | This Function scans APB devices table and returns count FIFO. |
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68 | 68 | |
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69 | 69 | \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want |
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70 | 70 | to use FIFO1 so count = 1. |
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71 | 71 | \return The pointer to the device. |
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72 | 72 | */ |
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73 | 73 | FIFO_Device* openFIFO(int count); |
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74 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[]); | |
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74 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count); | |
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75 | 75 | |
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76 | 76 | #endif |
@@ -1,44 +1,53 | |||
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1 | 1 | /*------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | -----------------------------------------------------------------------------*/ |
|
22 | 22 | #include "lpp_apb_functions.h" |
|
23 | 23 | #include "apb_fifo_Driver.h" |
|
24 | 24 | #include <stdio.h> |
|
25 | 25 | |
|
26 | 26 | |
|
27 | 27 | FIFO_Device* openFIFO(int count) |
|
28 | 28 | { |
|
29 | 29 | FIFO_Device* fifo0; |
|
30 | 30 | fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count); |
|
31 | 31 | return fifo0; |
|
32 | 32 | } |
|
33 | 33 | |
|
34 | 34 | |
|
35 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[]) | |
|
35 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count) | |
|
36 | 36 | { |
|
37 | 37 | int i=0; |
|
38 | while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full) // TANT QUE full a 0 ALORS | |
|
38 | //int poub; | |
|
39 | //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]); | |
|
40 | while(i<count) | |
|
41 | //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE full a 0 ALORS | |
|
39 | 42 | { |
|
43 | //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]); | |
|
44 | //printf("%d\n",i); | |
|
40 | 45 | dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[i]; |
|
41 | 46 | i++; |
|
42 | 47 | } |
|
48 | //poub = dev->FIFOreg[(2*ID)+FIFO_RWdata]; | |
|
49 | //dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[0]; | |
|
50 | //printf("END:%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]); | |
|
51 | //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN | |
|
43 | 52 | return 0; |
|
44 | 53 | } |
@@ -1,76 +1,76 | |||
|
1 | 1 | /*------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | -----------------------------------------------------------------------------*/ |
|
22 | 22 | #ifndef APB_FIFO_DRIVER_H |
|
23 | 23 | #define APB_FIFO_DRIVER_H |
|
24 | 24 | |
|
25 | 25 | /*! \file apb_fifo_Driver.h |
|
26 | 26 | \brief LPP FIFO driver. |
|
27 | 27 | |
|
28 | 28 | This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, |
|
29 | 29 | used in many type of application. |
|
30 | 30 | |
|
31 | 31 | \todo Check "DEVICE1 => count = 2" function Open |
|
32 | 32 | \author Martin Morlot martin.morlot@lpp.polytechnique.fr |
|
33 | 33 | */ |
|
34 | 34 | #define FIFO_Ctrl 0 |
|
35 | 35 | #define FIFO_RWdata 1 |
|
36 | 36 | |
|
37 | 37 | #define FIFO_Full 0x00010000 |
|
38 | 38 | #define FIFO_Empty 0x00000001 |
|
39 | 39 | #define FIFO_ReUse 0x00000002 |
|
40 | 40 | |
|
41 | 41 | #define Mask_2hex 0x000000FF |
|
42 | 42 | #define Mask_4hex 0x0000FFFF |
|
43 | 43 | |
|
44 | 44 | |
|
45 | 45 | /*=================================================== |
|
46 | 46 | T Y P E S D E F |
|
47 | 47 | ====================================================*/ |
|
48 | 48 | |
|
49 | 49 | /*! \struct APB_FIFO_REG |
|
50 | 50 | \brief Sturcture representing the fifo registers |
|
51 | 51 | */ |
|
52 | 52 | struct APB_FIFO_REG |
|
53 | 53 | { |
|
54 | int IDreg; | |
|
55 | int FIFOreg[2*8]; | |
|
54 | volatile int IDreg; | |
|
55 | volatile int FIFOreg[2*8]; | |
|
56 | 56 | }; |
|
57 | 57 | |
|
58 | 58 | typedef volatile struct APB_FIFO_REG FIFO_Device; |
|
59 | 59 | |
|
60 | 60 | /*=================================================== |
|
61 | 61 | F U N C T I O N S |
|
62 | 62 | ====================================================*/ |
|
63 | 63 | |
|
64 | 64 | /*! \fn APB_FIFO_Device* apbfifoOpen(int count); |
|
65 | 65 | \brief Return count FIFO. |
|
66 | 66 | |
|
67 | 67 | This Function scans APB devices table and returns count FIFO. |
|
68 | 68 | |
|
69 | 69 | \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want |
|
70 | 70 | to use FIFO1 so count = 1. |
|
71 | 71 | \return The pointer to the device. |
|
72 | 72 | */ |
|
73 | 73 | FIFO_Device* openFIFO(int count); |
|
74 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[]); | |
|
74 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count); | |
|
75 | 75 | |
|
76 | 76 | #endif |
@@ -1,638 +1,612 | |||
|
1 | 1 | ----------------------------------------------------------------------------- |
|
2 | 2 | -- LEON3 Demonstration design |
|
3 | 3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 2 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | |
|
20 | 20 | |
|
21 | 21 | library ieee; |
|
22 | 22 | use ieee.std_logic_1164.all; |
|
23 | 23 | library grlib; |
|
24 | 24 | use grlib.amba.all; |
|
25 | 25 | use grlib.stdlib.all; |
|
26 | 26 | library techmap; |
|
27 | 27 | use techmap.gencomp.all; |
|
28 | 28 | library gaisler; |
|
29 | 29 | use gaisler.memctrl.all; |
|
30 | 30 | use gaisler.leon3.all; |
|
31 | 31 | use gaisler.uart.all; |
|
32 | 32 | use gaisler.misc.all; |
|
33 | 33 | library esa; |
|
34 | 34 | use esa.memoryctrl.all; |
|
35 | 35 | use work.config.all; |
|
36 | 36 | library lpp; |
|
37 | 37 | use lpp.lpp_amba.all; |
|
38 | 38 | use lpp.lpp_memory.all; |
|
39 | 39 | use lpp.lpp_uart.all; |
|
40 | 40 | use lpp.lpp_matrix.all; |
|
41 | 41 | use lpp.lpp_delay.all; |
|
42 | 42 | use lpp.lpp_fft.all; |
|
43 | 43 | use lpp.fft_components.all; |
|
44 | 44 | use lpp.lpp_ad_conv.all; |
|
45 | 45 | use lpp.iir_filter.all; |
|
46 | 46 | use lpp.general_purpose.all; |
|
47 | 47 | use lpp.Filtercfg.all; |
|
48 | 48 | |
|
49 | 49 | entity leon3mp is |
|
50 | 50 | generic ( |
|
51 | 51 | fabtech : integer := CFG_FABTECH; |
|
52 | 52 | memtech : integer := CFG_MEMTECH; |
|
53 | 53 | padtech : integer := CFG_PADTECH; |
|
54 | 54 | clktech : integer := CFG_CLKTECH; |
|
55 | 55 | disas : integer := CFG_DISAS; -- Enable disassembly to console |
|
56 | 56 | dbguart : integer := CFG_DUART; -- Print UART on console |
|
57 | 57 | pclow : integer := CFG_PCLOW |
|
58 | 58 | ); |
|
59 | 59 | port ( |
|
60 | 60 | clk50MHz : in std_ulogic; |
|
61 | 61 | reset : in std_ulogic; |
|
62 | 62 | ramclk : out std_logic; |
|
63 | 63 | |
|
64 | 64 | ahbrxd : in std_ulogic; -- DSU rx data |
|
65 | 65 | ahbtxd : out std_ulogic; -- DSU tx data |
|
66 | 66 | dsubre : in std_ulogic; |
|
67 | 67 | dsuact : out std_ulogic; |
|
68 | 68 | urxd1 : in std_ulogic; -- UART1 rx data |
|
69 | 69 | utxd1 : out std_ulogic; -- UART1 tx data |
|
70 | 70 | errorn : out std_ulogic; |
|
71 | 71 | |
|
72 | 72 | address : out std_logic_vector(18 downto 0); |
|
73 | 73 | data : inout std_logic_vector(31 downto 0); |
|
74 | 74 | gpio : inout std_logic_vector(6 downto 0); -- I/O port |
|
75 | 75 | |
|
76 | 76 | nBWa : out std_logic; |
|
77 | 77 | nBWb : out std_logic; |
|
78 | 78 | nBWc : out std_logic; |
|
79 | 79 | nBWd : out std_logic; |
|
80 | 80 | nBWE : out std_logic; |
|
81 | 81 | nADSC : out std_logic; |
|
82 | 82 | nADSP : out std_logic; |
|
83 | 83 | nADV : out std_logic; |
|
84 | 84 | nGW : out std_logic; |
|
85 | 85 | nCE1 : out std_logic; |
|
86 | 86 | CE2 : out std_logic; |
|
87 | 87 | nCE3 : out std_logic; |
|
88 | 88 | nOE : out std_logic; |
|
89 | 89 | MODE : out std_logic; |
|
90 | 90 | SSRAM_CLK : out std_logic; |
|
91 | 91 | ZZ : out std_logic; |
|
92 | 92 | --------------------------------------------------------------------- |
|
93 | 93 | --- AJOUT TEST ------------------------In/Out----------------------- |
|
94 | 94 | --------------------------------------------------------------------- |
|
95 | 95 | -- UART |
|
96 | 96 | UART_RXD : in std_logic; |
|
97 | 97 | UART_TXD : out std_logic; |
|
98 | 98 | -- ADC |
|
99 | 99 | -- ADC_in : in AD7688_in(4 downto 0); |
|
100 | 100 | -- ADC_out : out AD7688_out; |
|
101 | 101 | -- Bias_Fails : out std_logic; |
|
102 | 102 | -- CNA |
|
103 | 103 | -- DAC_SYNC : out std_logic; |
|
104 | 104 | -- DAC_SCLK : out std_logic; |
|
105 | 105 | -- DAC_DATA : out std_logic; |
|
106 | 106 | -- Diver |
|
107 | 107 | SPW1_EN : out std_logic; |
|
108 | 108 | SPW2_EN : out std_logic; |
|
109 | 109 | TEST : out std_logic_vector(3 downto 0); |
|
110 | 110 | |
|
111 | 111 | BP : in std_logic; |
|
112 | 112 | --------------------------------------------------------------------- |
|
113 | 113 | led : out std_logic_vector(1 downto 0) |
|
114 | 114 | ); |
|
115 | 115 | end; |
|
116 | 116 | |
|
117 | 117 | architecture Behavioral of leon3mp is |
|
118 | 118 | |
|
119 | 119 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
|
120 | 120 | CFG_GRETH+CFG_AHB_JTAG; |
|
121 | 121 | constant maxahbm : integer := maxahbmsp; |
|
122 | 122 | |
|
123 | 123 | --Clk & Rst gοΏ½nοΏ½ |
|
124 | 124 | signal vcc : std_logic_vector(4 downto 0); |
|
125 | 125 | signal gnd : std_logic_vector(4 downto 0); |
|
126 | 126 | signal resetnl : std_ulogic; |
|
127 | 127 | signal clk2x : std_ulogic; |
|
128 | 128 | signal lclk : std_ulogic; |
|
129 | 129 | signal lclk2x : std_ulogic; |
|
130 | 130 | signal clkm : std_ulogic; |
|
131 | 131 | signal rstn : std_ulogic; |
|
132 | 132 | signal rstraw : std_ulogic; |
|
133 | 133 | signal pciclk : std_ulogic; |
|
134 | 134 | signal sdclkl : std_ulogic; |
|
135 | 135 | signal cgi : clkgen_in_type; |
|
136 | 136 | signal cgo : clkgen_out_type; |
|
137 | 137 | --- AHB / APB |
|
138 | 138 | signal apbi : apb_slv_in_type; |
|
139 | 139 | signal apbo : apb_slv_out_vector := (others => apb_none); |
|
140 | 140 | signal ahbsi : ahb_slv_in_type; |
|
141 | 141 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); |
|
142 | 142 | signal ahbmi : ahb_mst_in_type; |
|
143 | 143 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); |
|
144 | 144 | --UART |
|
145 | 145 | signal ahbuarti : uart_in_type; |
|
146 | 146 | signal ahbuarto : uart_out_type; |
|
147 | 147 | signal apbuarti : uart_in_type; |
|
148 | 148 | signal apbuarto : uart_out_type; |
|
149 | 149 | --MEM CTRLR |
|
150 | 150 | signal memi : memory_in_type; |
|
151 | 151 | signal memo : memory_out_type; |
|
152 | 152 | signal wpo : wprot_out_type; |
|
153 | 153 | signal sdo : sdram_out_type; |
|
154 | 154 | --IRQ |
|
155 | 155 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); |
|
156 | 156 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); |
|
157 | 157 | --Timer |
|
158 | 158 | signal gpti : gptimer_in_type; |
|
159 | 159 | signal gpto : gptimer_out_type; |
|
160 | 160 | --GPIO |
|
161 | 161 | signal gpioi : gpio_in_type; |
|
162 | 162 | signal gpioo : gpio_out_type; |
|
163 | 163 | --DSU |
|
164 | 164 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); |
|
165 | 165 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); |
|
166 | 166 | signal dsui : dsu_in_type; |
|
167 | 167 | signal dsuo : dsu_out_type; |
|
168 | 168 | |
|
169 | 169 | --------------------------------------------------------------------- |
|
170 | 170 | --- AJOUT TEST ------------------------Signaux---------------------- |
|
171 | 171 | --------------------------------------------------------------------- |
|
172 | 172 | -- FIFOs |
|
173 |
signal FifoIN_Full : std_logic_vector(4 downto 0); |
|
|
174 |
signal FifoIN_Empty : std_logic_vector(4 downto 0); |
|
|
175 |
signal FifoIN_Data : std_logic_vector(79 downto 0); |
|
|
173 | signal FifoIN_Full : std_logic_vector(4 downto 0); | |
|
174 | signal FifoIN_Empty : std_logic_vector(4 downto 0); | |
|
175 | signal FifoIN_Data : std_logic_vector(79 downto 0); | |
|
176 | 176 | |
|
177 | 177 | signal FifoINT_Full : std_logic_vector(4 downto 0); |
|
178 | 178 | signal FifoINT_Data : std_logic_vector(79 downto 0); |
|
179 | 179 | |
|
180 | 180 | signal FifoOUT_FullV : std_logic; |
|
181 |
signal FifoOUT_Full : std_logic_vector( |
|
|
181 | signal FifoOUT_Full : std_logic_vector(1 downto 0); | |
|
182 | 182 | signal Matrix_WriteV : std_logic_vector(0 downto 0); |
|
183 | 183 | |
|
184 | 184 | -- MATRICE SPECTRALE |
|
185 | 185 | signal Matrix_Write : std_logic; |
|
186 | 186 | signal Matrix_Read : std_logic_vector(1 downto 0); |
|
187 | 187 | signal Matrix_Result : std_logic_vector(31 downto 0); |
|
188 | 188 | |
|
189 | 189 | signal TopSM_Start : std_logic; |
|
190 | 190 | signal TopSM_Statu : std_logic_vector(3 downto 0); |
|
191 | 191 | signal TopSM_Read : std_logic_vector(4 downto 0); |
|
192 | 192 | signal TopSM_Data1 : std_logic_vector(15 downto 0); |
|
193 | 193 | signal TopSM_Data2 : std_logic_vector(15 downto 0); |
|
194 | 194 | |
|
195 | 195 | signal Disp_FlagError : std_logic; |
|
196 | 196 | signal Disp_Pong : std_logic; |
|
197 | signal Disp_Write : std_logic_vector(1 downto 0); | |
|
198 | signal Disp_Data : std_logic_vector(63 downto 0); | |
|
199 | signal Dma_acq : std_logic; | |
|
197 | signal Disp_Write : std_logic_vector(1 downto 0);-- | |
|
198 | signal Disp_Data : std_logic_vector(63 downto 0);-- | |
|
199 | signal Dma_acq : std_logic; | |
|
200 | 200 | |
|
201 | 201 | -- FFT |
|
202 | 202 | signal Drive_Write : std_logic; |
|
203 |
signal Drive_Read : std_logic_vector(4 downto 0); |
|
|
203 | signal Drive_Read : std_logic_vector(4 downto 0); | |
|
204 | 204 | signal Drive_DataRE : std_logic_vector(15 downto 0); |
|
205 | 205 | signal Drive_DataIM : std_logic_vector(15 downto 0); |
|
206 | 206 | |
|
207 | 207 | signal Start : std_logic; |
|
208 | 208 | signal RstnFFT : std_logic; |
|
209 | 209 | signal FFT_Load : std_logic; |
|
210 | 210 | signal FFT_Ready : std_logic; |
|
211 | 211 | signal FFT_Valid : std_logic; |
|
212 | 212 | signal FFT_DataRE : std_logic_vector(15 downto 0); |
|
213 | 213 | signal FFT_DataIM : std_logic_vector(15 downto 0); |
|
214 | 214 | |
|
215 | 215 | signal Link_Read : std_logic; |
|
216 |
signal Link_Write : std_logic_vector(4 downto 0); |
|
|
217 |
signal Link_ReUse : std_logic_vector(4 downto 0); |
|
|
218 |
signal Link_Data : std_logic_vector(79 downto 0); |
|
|
216 | signal Link_Write : std_logic_vector(4 downto 0); | |
|
217 | signal Link_ReUse : std_logic_vector(4 downto 0); | |
|
218 | signal Link_Data : std_logic_vector(79 downto 0); | |
|
219 | 219 | |
|
220 | 220 | -- ADC |
|
221 | 221 | signal SmplClk : std_logic; |
|
222 | 222 | signal ADC_DataReady : std_logic; |
|
223 | 223 | signal ADC_SmplOut : Samples_out(4 downto 0); |
|
224 | 224 | signal enableADC : std_logic; |
|
225 | 225 | |
|
226 | 226 | signal WG_Write : std_logic_vector(4 downto 0); |
|
227 | 227 | signal WG_ReUse : std_logic_vector(4 downto 0); |
|
228 | 228 | signal WG_DATA : std_logic_vector(79 downto 0); |
|
229 | 229 | signal s_out : std_logic_vector(79 downto 0); |
|
230 | 230 | |
|
231 | 231 | signal fuller : std_logic_vector(4 downto 0); |
|
232 | 232 | signal reader : std_logic_vector(4 downto 0); |
|
233 | 233 | signal try : std_logic_vector(1 downto 0); |
|
234 | 234 | signal TXDint : std_logic; |
|
235 | 235 | |
|
236 | 236 | -- IIR Filter |
|
237 | 237 | signal sample_clk_out : std_logic; |
|
238 | 238 | |
|
239 |
signal Rd : std_logic_vector(0 downto 0); |
|
|
240 |
signal Ept : std_logic_vector(4 downto 0); |
|
|
239 | signal Rd : std_logic_vector(0 downto 0); | |
|
240 | signal Ept : std_logic_vector(4 downto 0); | |
|
241 | 241 | |
|
242 | 242 | signal Bwr : std_logic_vector(0 downto 0); |
|
243 | 243 | signal Bre : std_logic_vector(0 downto 0); |
|
244 | 244 | signal DataTMP : std_logic_vector(15 downto 0); |
|
245 | 245 | signal FullUp : std_logic_vector(0 downto 0); |
|
246 | 246 | signal EmptyUp : std_logic_vector(0 downto 0); |
|
247 | 247 | signal FullDown : std_logic_vector(0 downto 0); |
|
248 | 248 | signal EmptyDown : std_logic_vector(0 downto 0); |
|
249 | 249 | --------------------------------------------------------------------- |
|
250 | 250 | constant IOAEN : integer := CFG_CAN; |
|
251 | 251 | constant boardfreq : integer := 50000; |
|
252 | 252 | |
|
253 | 253 | begin |
|
254 | 254 | |
|
255 | 255 | --------------------------------------------------------------------- |
|
256 | 256 | --- AJOUT TEST -------------------------------------IPs------------- |
|
257 | 257 | --------------------------------------------------------------------- |
|
258 | 258 | led(1 downto 0) <= gpio(1 downto 0); |
|
259 | 259 | |
|
260 | 260 | --- COM USB --------------------------------------------------------- |
|
261 | 261 | -- MemIn0 : APB_FifoWrite |
|
262 | 262 | -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
|
263 | 263 | -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); |
|
264 | 264 | -- |
|
265 | 265 | -- BUF0 : APB_USB |
|
266 | 266 | -- generic map (6,6,DataMax => 1024) |
|
267 | 267 | -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); |
|
268 | 268 | -- |
|
269 | 269 | -- MemOut0 : APB_FifoRead |
|
270 | 270 | -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
|
271 | 271 | -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); |
|
272 | 272 | -- |
|
273 | 273 | --slrd <= usb_Read; |
|
274 | 274 | --slwr <= usb_Write; |
|
275 | 275 | |
|
276 | 276 | --- CNA ------------------------------------------------------------- |
|
277 | 277 | |
|
278 | 278 | -- CONV : APB_CNA |
|
279 | 279 | -- generic map (5,5) |
|
280 | 280 | -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); |
|
281 | 281 | |
|
282 | 282 | --TEST(0) <= SmplClk; |
|
283 | 283 | --TEST(1) <= WG_Write(0); |
|
284 | 284 | --TEST(2) <= Fuller(0); |
|
285 | 285 | --TEST(3) <= s_out(s_out'length-1); |
|
286 | 286 | |
|
287 | 287 | |
|
288 | SPW1_EN <= '1'; | |
|
289 | SPW2_EN <= '0'; | |
|
288 | --SPW1_EN <= '1'; | |
|
289 | --SPW2_EN <= '0'; | |
|
290 | 290 | |
|
291 | 291 | --- CAN ------------------------------------------------------------- |
|
292 | 292 | |
|
293 | 293 | -- Divider : Clk_divider |
|
294 | 294 | -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) |
|
295 | 295 | -- Port map(clkm,rstn,SmplClk); |
|
296 | 296 | -- |
|
297 | 297 | -- ADC : AD7688_drvr |
|
298 | 298 | -- generic map (ChanelCount => 5, clkkHz => 24_576) |
|
299 | 299 | -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); |
|
300 | 300 | -- |
|
301 | 301 | -- WG : WriteGen_ADC |
|
302 | 302 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); |
|
303 | 303 | -- |
|
304 | 304 | --enableADC <= gpio(0); |
|
305 | 305 | --Bias_Fails <= '0'; |
|
306 | 306 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); |
|
307 | 307 | -- |
|
308 | 308 | -- |
|
309 | 309 | -- MemIn1 : APB_FIFO |
|
310 | 310 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
311 | 311 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); |
|
312 | 312 | |
|
313 | 313 | --- FFT ------------------------------------------------------------- |
|
314 | 314 | |
|
315 | 315 | MemIn : APB_FIFO |
|
316 | 316 | generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
|
317 | 317 | port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); |
|
318 | -- MemIn : APB_FIFO | |
|
319 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) | |
|
320 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others =>'1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); | |
|
321 | -- | |
|
322 | 318 | |
|
323 | Start <= '0'; | |
|
324 | ||
|
325 | -- DRIVE : FFTamont | |
|
326 | -- generic map(Data_sz => 16,NbData => 256) | |
|
327 | -- port map(clkm,rstn,FFT_Load,FifoIN_Empty(0),FifoIN_Data,Drive_Write,Drive_Read(0),Drive_DataRE,Drive_DataIM); | |
|
328 | 319 | DRIVE : Driver_FFT |
|
329 | 320 | generic map(Data_sz => 16) |
|
330 | 321 | port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM); |
|
331 | -- | |
|
322 | ||
|
323 | Start <= '0'; | |
|
324 | ||
|
332 | 325 |
|
|
333 | 326 | generic map( |
|
334 | 327 | LOGPTS => gLOGPTS, |
|
335 | 328 | LOGLOGPTS => gLOGLOGPTS, |
|
336 | 329 | WSIZE => gWSIZE, |
|
337 | 330 | TWIDTH => gTWIDTH, |
|
338 | 331 | DWIDTH => gDWIDTH, |
|
339 | 332 | TDWIDTH => gTDWIDTH, |
|
340 | 333 | RND_MODE => gRND_MODE, |
|
341 | 334 | SCALE_MODE => gSCALE_MODE, |
|
342 | 335 | PTS => gPTS, |
|
343 | 336 | HALFPTS => gHALFPTS, |
|
344 | 337 | inBuf_RWDLY => gInBuf_RWDLY) |
|
345 | 338 | port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); |
|
346 | -- | |
|
339 | ||
|
347 | 340 |
|
|
348 | 341 | generic map(Data_sz => 16) |
|
349 |
port map(clkm,rstn,FFT_Ready,FFT_Valid,Fifo |
|
|
350 | -- LINK : FFTaval | |
|
351 | -- generic map(Data_sz => 16,NbData => 256) | |
|
352 | -- port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full(0),FFT_DataRE,FFT_DataIM,Link_Read,Link_Write(0),Link_ReUse(0),Link_Data); | |
|
353 | -- | |
|
342 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data); | |
|
343 | ||
|
344 | ----- LINK MEMORY ------------------------------------------------------- | |
|
345 | ||
|
346 | -- MemOut : APB_FIFO | |
|
347 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) | |
|
348 | -- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9)); | |
|
349 | ||
|
350 | MemInt : lppFIFOxN | |
|
351 | generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') | |
|
352 | port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); | |
|
353 | ||
|
354 | -- MemIn : APB_FIFO | |
|
355 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) | |
|
356 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); | |
|
357 | ||
|
354 | 358 | ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- |
|
355 | -- | |
|
356 | MemOut : APB_FIFO | |
|
357 | generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) | |
|
358 | port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9)); | |
|
359 | ||
|
360 | ||
|
361 | --TEST(0) <= FifoOUT_Full(0); | |
|
362 | --TEST(1) <= Link_Write(0); | |
|
363 | 359 | |
|
364 | -- MemInt : lppFIFOx5 | |
|
365 |
|
|
|
366 | -- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); | |
|
367 | -- | |
|
368 | --Matrix_WriteV(0) <= not Matrix_Write; | |
|
369 | --FifoOUT_FullV <= FifoOUT_Full(0); | |
|
370 | -- | |
|
371 | ---- MemInt : lppFIFOxN | |
|
372 | ---- generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') | |
|
373 | ---- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); | |
|
374 | -- | |
|
375 | -- TopSM : TopMatrix_PDR | |
|
376 | -- generic map (Input_SZ => 16) | |
|
377 | -- port map (clkm,rstn,FifoINT_Data,FifoINT_Full,Matrix_Read,Matrix_Write,TopSM_Data1,TopSM_Data2,TopSM_Start,TopSM_Read,TopSM_Statu); | |
|
378 | -- | |
|
379 | -- SM : SpectralMatrix | |
|
380 | -- generic map (Input_SZ => 16, Result_SZ => 32) | |
|
381 | -- port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); | |
|
360 | TopSM : TopSpecMatrix | |
|
361 | generic map (Input_SZ => 16) | |
|
362 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoINT_Full,FifoINT_Data,TopSM_Start,TopSM_Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); | |
|
363 | ||
|
364 | SM : SpectralMatrix | |
|
365 | generic map (Input_SZ => 16, Result_SZ => 32) | |
|
366 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); | |
|
382 | 367 | |
|
368 | Dma_acq <= '1'; | |
|
369 | ||
|
370 | DISP : Dispatch | |
|
371 | generic map(Data_SZ => 32) | |
|
372 | port map(clkm,rstn,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError); | |
|
373 | ||
|
374 | MemOut : APB_FIFO | |
|
375 | generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
|
376 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(9)); | |
|
377 | ||
|
378 | ----- FIFO ------------------------------------------------------------- | |
|
379 | ||
|
380 | Memtest : APB_FIFO | |
|
381 | generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) | |
|
382 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); | |
|
383 | 383 | |
|
384 | 384 | --***************************************TEST DEMI-FIFO******************************************************************************** |
|
385 | 385 | -- MemIn : APB_FIFO |
|
386 | 386 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
|
387 | 387 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); |
|
388 | 388 | -- |
|
389 | 389 | -- Pont : Bridge |
|
390 | 390 | -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); |
|
391 | 391 | -- |
|
392 | 392 | -- MemOut : APB_FIFO |
|
393 | 393 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
394 | 394 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); |
|
395 | 395 | --************************************************************************************************************************************* |
|
396 | 396 | |
|
397 | ||
|
398 | ||
|
399 | ||
|
400 | ||
|
401 | ||
|
402 | ||
|
403 | ||
|
404 | ||
|
405 | ||
|
406 | ||
|
407 | --Dma_acq <= '1'; | |
|
408 | -- | |
|
409 | -- DISP : Dispatch | |
|
410 | -- generic map(Data_SZ => 32) | |
|
411 | -- port map(clkm,reset,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError); | |
|
412 | -- | |
|
413 | ----- FIFO ------------------------------------------------------------- | |
|
414 | -- | |
|
415 | -- MemOut : APB_FIFO | |
|
416 | -- generic map (pindex => 15, paddr => 15, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
|
417 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(15)); | |
|
418 | -- | |
|
419 | Memtest : APB_FIFO | |
|
420 | generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) | |
|
421 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); | |
|
422 | ||
|
423 | 397 | --- UART ------------------------------------------------------------- |
|
424 | 398 | |
|
425 | 399 | COM0 : APB_UART |
|
426 | 400 | generic map (pindex => 4, paddr => 4) |
|
427 | 401 | port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD); |
|
428 | 402 | |
|
429 | 403 | --- DELAY ------------------------------------------------------------ |
|
430 | 404 | |
|
431 | 405 | -- Delay0 : APB_Delay |
|
432 | 406 | -- generic map (pindex => 4, paddr => 4) |
|
433 | 407 | -- port map (clkm,rstn,apbi,apbo(4)); |
|
434 | 408 | |
|
435 | 409 | --- IIR Filter ------------------------------------------------------- |
|
436 | 410 | --Test(0) <= sample_clk_out; |
|
437 | 411 | -- |
|
438 | 412 | -- |
|
439 | 413 | -- IIR1: APB_IIR_Filter |
|
440 | 414 | -- generic map( |
|
441 | 415 | -- tech => CFG_MEMTECH, |
|
442 | 416 | -- pindex => 8, |
|
443 | 417 | -- paddr => 8, |
|
444 | 418 | -- Sample_SZ => Sample_SZ, |
|
445 | 419 | -- ChanelsCount => ChanelsCount, |
|
446 | 420 | -- Coef_SZ => Coef_SZ, |
|
447 | 421 | -- CoefCntPerCel => CoefCntPerCel, |
|
448 | 422 | -- Cels_count => Cels_count, |
|
449 | 423 | -- virgPos => virgPos |
|
450 | 424 | -- ) |
|
451 | 425 | -- port map( |
|
452 | 426 | -- rst => rstn, |
|
453 | 427 | -- clk => clkm, |
|
454 | 428 | -- apbi => apbi, |
|
455 | 429 | -- apbo => apbo(8), |
|
456 | 430 | -- sample_clk_out => sample_clk_out, |
|
457 | 431 | -- GOtest => Test(1), |
|
458 | 432 | -- CoefsInitVal => (others => '1') |
|
459 | 433 | -- ); |
|
460 | 434 | ---------------------------------------------------------------------- |
|
461 | 435 | |
|
462 | 436 | ---------------------------------------------------------------------- |
|
463 | 437 | --- Reset and Clock generation ------------------------------------- |
|
464 | 438 | ---------------------------------------------------------------------- |
|
465 | 439 | |
|
466 | 440 | vcc <= (others => '1'); gnd <= (others => '0'); |
|
467 | 441 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
|
468 | 442 | |
|
469 | 443 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); |
|
470 | 444 | |
|
471 | 445 | |
|
472 | 446 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); |
|
473 | 447 | |
|
474 | 448 | clkgen0 : clkgen -- clock generator |
|
475 | 449 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
476 | 450 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
|
477 | 451 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); |
|
478 | 452 | |
|
479 | 453 | ramclk <= clkm; |
|
480 | 454 | process(lclk2x) |
|
481 | 455 | begin |
|
482 | 456 | if lclk2x'event and lclk2x = '1' then |
|
483 | 457 | lclk <= not lclk; |
|
484 | 458 | end if; |
|
485 | 459 | end process; |
|
486 | 460 | |
|
487 | 461 | ---------------------------------------------------------------------- |
|
488 | 462 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
489 | 463 | ---------------------------------------------------------------------- |
|
490 | 464 | |
|
491 | 465 | l3 : if CFG_LEON3 = 1 generate |
|
492 | 466 | cpu : for i in 0 to CFG_NCPU-1 generate |
|
493 | 467 | u0 : leon3s -- LEON3 processor |
|
494 | 468 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
495 | 469 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
496 | 470 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
497 | 471 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
498 | 472 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
499 | 473 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
500 | 474 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
501 | 475 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
502 | 476 | end generate; |
|
503 | 477 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); |
|
504 | 478 | |
|
505 | 479 | dsugen : if CFG_DSU = 1 generate |
|
506 | 480 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
507 | 481 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
508 | 482 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
509 | 483 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
510 | 484 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); |
|
511 | 485 | dsui.enable <= '1'; |
|
512 | 486 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); |
|
513 | 487 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); |
|
514 | 488 | end generate; |
|
515 | 489 | end generate; |
|
516 | 490 | |
|
517 | 491 | nodsu : if CFG_DSU = 0 generate |
|
518 | 492 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
|
519 | 493 | end generate; |
|
520 | 494 | |
|
521 | 495 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate |
|
522 | 496 | irqctrl0 : irqmp -- interrupt controller |
|
523 | 497 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
524 | 498 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
525 | 499 | end generate; |
|
526 | 500 | irq3 : if CFG_IRQ3_ENABLE = 0 generate |
|
527 | 501 | x : for i in 0 to CFG_NCPU-1 generate |
|
528 | 502 | irqi(i).irl <= "0000"; |
|
529 | 503 | end generate; |
|
530 | 504 | apbo(2) <= apb_none; |
|
531 | 505 | end generate; |
|
532 | 506 | |
|
533 | 507 | ---------------------------------------------------------------------- |
|
534 | 508 | --- Memory controllers --------------------------------------------- |
|
535 | 509 | ---------------------------------------------------------------------- |
|
536 | 510 | |
|
537 | 511 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) |
|
538 | 512 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); |
|
539 | 513 | |
|
540 | 514 | memi.brdyn <= '1'; memi.bexcn <= '1'; |
|
541 | 515 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; |
|
542 | 516 | |
|
543 | 517 | bdr : for i in 0 to 3 generate |
|
544 | 518 | data_pad : iopadv generic map (tech => padtech, width => 8) |
|
545 | 519 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), |
|
546 | 520 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); |
|
547 | 521 | end generate; |
|
548 | 522 | |
|
549 | 523 | |
|
550 | 524 | addr_pad : outpadv generic map (width => 19, tech => padtech) |
|
551 | 525 | port map (address, memo.address(20 downto 2)); |
|
552 | 526 | |
|
553 | 527 | |
|
554 | 528 | SSRAM_0:entity ssram_plugin |
|
555 | 529 | generic map (tech => padtech) |
|
556 | 530 | port map |
|
557 | 531 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); |
|
558 | 532 | |
|
559 | 533 | ---------------------------------------------------------------------- |
|
560 | 534 | --- AHB CONTROLLER ------------------------------------------------- |
|
561 | 535 | ---------------------------------------------------------------------- |
|
562 | 536 | |
|
563 | 537 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
564 | 538 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
565 | 539 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
566 | 540 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
|
567 | 541 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
568 | 542 | |
|
569 | 543 | ---------------------------------------------------------------------- |
|
570 | 544 | --- AHB UART ------------------------------------------------------- |
|
571 | 545 | ---------------------------------------------------------------------- |
|
572 | 546 | |
|
573 | 547 | dcomgen : if CFG_AHB_UART = 1 generate |
|
574 | 548 | dcom0: ahbuart -- Debug UART |
|
575 | 549 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) |
|
576 | 550 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); |
|
577 | 551 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); |
|
578 | 552 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); |
|
579 | 553 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; |
|
580 | 554 | end generate; |
|
581 | 555 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; |
|
582 | 556 | |
|
583 | 557 | ---------------------------------------------------------------------- |
|
584 | 558 | --- APB Bridge ----------------------------------------------------- |
|
585 | 559 | ---------------------------------------------------------------------- |
|
586 | 560 | |
|
587 | 561 | apb0 : apbctrl -- AHB/APB bridge |
|
588 | 562 | generic map (hindex => 1, haddr => CFG_APBADDR) |
|
589 | 563 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); |
|
590 | 564 | |
|
591 | 565 | ---------------------------------------------------------------------- |
|
592 | 566 | --- GPT Timer ------------------------------------------------------ |
|
593 | 567 | ---------------------------------------------------------------------- |
|
594 | 568 | |
|
595 | 569 | gpt : if CFG_GPT_ENABLE /= 0 generate |
|
596 | 570 | timer0 : gptimer -- timer unit |
|
597 | 571 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
598 | 572 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
599 | 573 | nbits => CFG_GPT_TW) |
|
600 | 574 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
601 | 575 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; |
|
602 | 576 | -- led(4) <= gpto.wdog; |
|
603 | 577 | end generate; |
|
604 | 578 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; |
|
605 | 579 | |
|
606 | 580 | |
|
607 | 581 | ---------------------------------------------------------------------- |
|
608 | 582 | --- APB UART ------------------------------------------------------- |
|
609 | 583 | ---------------------------------------------------------------------- |
|
610 | 584 | |
|
611 | 585 | ua1 : if CFG_UART1_ENABLE /= 0 generate |
|
612 | 586 | uart1 : apbuart -- UART 1 |
|
613 | 587 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
614 | 588 | fifosize => CFG_UART1_FIFO) |
|
615 | 589 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); |
|
616 | 590 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; |
|
617 | 591 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; |
|
618 | 592 | -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; |
|
619 | 593 | end generate; |
|
620 | 594 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; |
|
621 | 595 | |
|
622 | 596 | ---------------------------------------------------------------------- |
|
623 | 597 | --- GPIO ----------------------------------------------------------- |
|
624 | 598 | ---------------------------------------------------------------------- |
|
625 | 599 | |
|
626 | 600 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit |
|
627 | 601 | grgpio0: grgpio |
|
628 | 602 | generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) |
|
629 | 603 | port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); |
|
630 | 604 | |
|
631 | 605 | pio_pads : for i in 0 to 6 generate |
|
632 | 606 | pio_pad : iopad generic map (tech => padtech) |
|
633 | 607 | port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); |
|
634 | 608 | end generate; |
|
635 | 609 | end generate; |
|
636 | 610 | |
|
637 | 611 | |
|
638 | 612 | end Behavioral; No newline at end of file |
@@ -1,109 +1,95 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | library IEEE; |
|
23 | 23 | use IEEE.numeric_std.all; |
|
24 | 24 | use IEEE.std_logic_1164.all; |
|
25 | use lpp.lpp_matrix.all; | |
|
26 | 25 | |
|
27 | 26 | entity Dispatch is |
|
28 | 27 | generic( |
|
29 | 28 | Data_SZ : integer := 32); |
|
30 | 29 | port( |
|
31 | 30 | clk : in std_logic; |
|
32 | 31 | reset : in std_logic; |
|
33 | 32 | Acq : in std_logic; |
|
34 | 33 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
35 | 34 | Write : in std_logic; |
|
36 | 35 | Full : in std_logic_vector(1 downto 0); |
|
37 | -- Empty : in std_logic_vector(1 downto 0); | |
|
38 | 36 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
39 | 37 | FifoWrite : out std_logic_vector(1 downto 0); |
|
40 | -- FifoFull : out std_logic; | |
|
41 | 38 | Pong : out std_logic; |
|
42 | 39 | Error : out std_logic |
|
43 | ||
|
44 | 40 | ); |
|
45 | 41 | end entity; |
|
46 | 42 | |
|
47 | 43 | |
|
48 | 44 | architecture ar_Dispatch of Dispatch is |
|
49 | 45 | |
|
50 |
type etat is (e0,e1,e2 |
|
|
46 | type etat is (eX,e0,e1,e2); | |
|
51 | 47 | signal ect : etat; |
|
52 | 48 | |
|
49 | signal Pong_int : std_logic; | |
|
50 | signal FifoCpt : integer range 0 to 1 := 0; | |
|
51 | ||
|
53 | 52 | begin |
|
54 | 53 | |
|
55 | 54 | process (clk,reset) |
|
56 | 55 | begin |
|
57 | 56 | if(reset='0')then |
|
58 | Pong <= '0'; | |
|
59 |
Error <= '0'; |
|
|
57 | Pong_int <= '0'; | |
|
58 | Error <= '0'; | |
|
59 | ect <= e0; | |
|
60 | 60 | |
|
61 | 61 | elsif(clk' event and clk='1')then |
|
62 | 62 | |
|
63 | 63 | case ect is |
|
64 | 64 | |
|
65 | 65 | when e0 => |
|
66 |
if(Full( |
|
|
67 | pong <= '1'; | |
|
66 | if(Full(FifoCpt) = '1')then | |
|
67 | Pong_int <= not Pong_int; | |
|
68 | 68 | ect <= e1; |
|
69 | 69 | end if; |
|
70 | 70 | |
|
71 | 71 | when e1 => |
|
72 |
if(Acq |
|
|
73 | Error <= '0'; | |
|
74 | pong <= '0'; | |
|
75 | ect <= e2; | |
|
76 | else | |
|
72 | if(Acq = '0')then | |
|
77 | 73 | Error <= '1'; |
|
78 | 74 | ect <= e1; |
|
79 |
e |
|
|
80 | ||
|
81 | when e2 => | |
|
82 | if(Full(1) = '1')then | |
|
83 | pong <= '1'; | |
|
84 | ect <= e3; | |
|
85 | end if; | |
|
86 | ||
|
87 | when e3 => | |
|
88 | if(Acq <= '1')then | |
|
75 | else | |
|
89 | 76 | Error <= '0'; |
|
90 | pong <= '0'; | |
|
91 | 77 | ect <= e0; |
|
92 |
e |
|
|
93 |
|
|
|
94 | ect <= e3; | |
|
95 |
|
|
|
78 | end if; | |
|
79 | ||
|
80 | when others => | |
|
81 | null; | |
|
96 | 82 |
|
|
97 | 83 |
|
|
98 | 84 | |
|
99 | 85 | end if; |
|
100 | 86 | end process; |
|
101 | 87 | |
|
102 | 88 | FifoData <= Data & Data; |
|
89 | Pong <= Pong_int; | |
|
103 | 90 | |
|
104 | with ect select | |
|
105 | FifoWrite <= '1' & not Write when e0, | |
|
106 | not Write & '1' when e2, | |
|
107 | "11" when others; | |
|
91 | FifoCpt <= 0 when Pong_int='0' else 1; | |
|
92 | ||
|
93 | FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; | |
|
108 | 94 | |
|
109 | 95 | end architecture; No newline at end of file |
@@ -1,259 +1,278 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | 22 | library ieee; |
|
23 | 23 | use ieee.std_logic_1164.all; |
|
24 | 24 | library grlib; |
|
25 | 25 | use grlib.amba.all; |
|
26 | 26 | use std.textio.all; |
|
27 | 27 | library lpp; |
|
28 | 28 | use lpp.lpp_amba.all; |
|
29 | 29 | |
|
30 | 30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
31 | 31 | |
|
32 | 32 | package lpp_matrix is |
|
33 | 33 | |
|
34 | 34 | component APB_Matrix is |
|
35 | 35 | generic ( |
|
36 | 36 | pindex : integer := 0; |
|
37 | 37 | paddr : integer := 0; |
|
38 | 38 | pmask : integer := 16#fff#; |
|
39 | 39 | pirq : integer := 0; |
|
40 | 40 | abits : integer := 8; |
|
41 | 41 | Input_SZ : integer := 16; |
|
42 | 42 | Result_SZ : integer := 32); |
|
43 | 43 | port ( |
|
44 | 44 | clk : in std_logic; |
|
45 | 45 | rst : in std_logic; |
|
46 | 46 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
47 | 47 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
48 | 48 | Full : in std_logic_vector(1 downto 0); |
|
49 | 49 | Empty : in std_logic_vector(1 downto 0); |
|
50 | 50 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
51 | 51 | FullFIFO : in std_logic; |
|
52 | 52 | WriteFIFO : out std_logic; |
|
53 | 53 | Result : out std_logic_vector(Result_SZ-1 downto 0); |
|
54 | 54 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
|
55 | 55 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
56 | 56 | ); |
|
57 | 57 | end component; |
|
58 | 58 | |
|
59 | component TopSpecMatrix is | |
|
60 | generic( | |
|
61 | Input_SZ : integer := 16); | |
|
62 | port( | |
|
63 | clk : in std_logic; | |
|
64 | rstn : in std_logic; | |
|
65 | Write : in std_logic; | |
|
66 | ReadIn : in std_logic_vector(1 downto 0); | |
|
67 | Full : in std_logic_vector(4 downto 0); | |
|
68 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
|
69 | Start : out std_logic; | |
|
70 | ReadOut : out std_logic_vector(4 downto 0); | |
|
71 | Statu : out std_logic_vector(3 downto 0); | |
|
72 | DATA1 : out std_logic_vector(Input_SZ-1 downto 0); | |
|
73 | DATA2 : out std_logic_vector(Input_SZ-1 downto 0) | |
|
74 | ); | |
|
75 | end component; | |
|
76 | ||
|
77 | ||
|
59 | 78 | component Top_MatrixSpec is |
|
60 | 79 | generic( |
|
61 | 80 | Input_SZ : integer := 16; |
|
62 | 81 | Result_SZ : integer := 32); |
|
63 | 82 | port( |
|
64 | 83 | clk : in std_logic; |
|
65 | 84 | reset : in std_logic; |
|
66 | 85 | Statu : in std_logic_vector(3 downto 0); |
|
67 | 86 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
68 | 87 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
69 | 88 | Full : in std_logic_vector(1 downto 0); |
|
70 | 89 | Empty : in std_logic_vector(1 downto 0); |
|
71 | 90 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
72 | 91 | FullFIFO : in std_logic; |
|
73 | 92 | WriteFIFO : out std_logic; |
|
74 | 93 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
75 | 94 | ); |
|
76 | 95 | end component; |
|
77 | 96 | |
|
78 | 97 | component SpectralMatrix is |
|
79 | 98 | generic( |
|
80 | 99 | Input_SZ : integer := 16; |
|
81 | 100 | Result_SZ : integer := 32); |
|
82 | 101 | port( |
|
83 | 102 | clk : in std_logic; |
|
84 | 103 | reset : in std_logic; |
|
85 | 104 | Start : in std_logic; |
|
86 | 105 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
87 | 106 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
88 | 107 | Statu : in std_logic_vector(3 downto 0); |
|
89 | 108 | -- FullFIFO : in std_logic; |
|
90 | 109 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
91 | 110 | WriteFIFO : out std_logic; |
|
92 | 111 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
93 | 112 | ); |
|
94 | 113 | end component; |
|
95 | 114 | |
|
96 | 115 | |
|
97 | 116 | component Matrix is |
|
98 | 117 | generic( |
|
99 | 118 | Input_SZ : integer := 16); |
|
100 | 119 | port( |
|
101 | 120 | clk : in std_logic; |
|
102 | 121 | raz : in std_logic; |
|
103 | 122 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
104 | 123 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
105 | 124 | Take : in std_logic; |
|
106 | 125 | Received : in std_logic; |
|
107 | 126 | Conjugate : in std_logic; |
|
108 | 127 | Valid : out std_logic; |
|
109 | 128 | Read : out std_logic; |
|
110 | 129 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) |
|
111 | 130 | ); |
|
112 | 131 | end component; |
|
113 | 132 | |
|
114 | 133 | component GetResult is |
|
115 | 134 | generic( |
|
116 | 135 | Result_SZ : integer := 32); |
|
117 | 136 | port( |
|
118 | 137 | clk : in std_logic; |
|
119 | 138 | raz : in std_logic; |
|
120 | 139 | Valid : in std_logic; |
|
121 | 140 | Conjugate : in std_logic; |
|
122 | 141 | Res : in std_logic_vector(Result_SZ-1 downto 0); |
|
123 | 142 | -- Full : in std_logic; |
|
124 | 143 | WriteFIFO : out std_logic; |
|
125 | 144 | Received : out std_logic; |
|
126 | 145 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
127 | 146 | ); |
|
128 | 147 | end component; |
|
129 | 148 | |
|
130 | 149 | |
|
131 | 150 | component TopMatrix_PDR is |
|
132 | 151 | generic( |
|
133 | 152 | Input_SZ : integer := 16; |
|
134 | 153 | Result_SZ : integer := 32); |
|
135 | 154 | port( |
|
136 | 155 | clk : in std_logic; |
|
137 | 156 | reset : in std_logic; |
|
138 | 157 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
139 | 158 | FULLin : in std_logic_vector(4 downto 0); |
|
140 | 159 | READin : in std_logic_vector(1 downto 0); |
|
141 | 160 | WRITEin : in std_logic; |
|
142 | 161 | FIFO1 : out std_logic_vector(Input_SZ-1 downto 0); |
|
143 | 162 | FIFO2 : out std_logic_vector(Input_SZ-1 downto 0); |
|
144 | 163 | Start : out std_logic; |
|
145 | 164 | Read : out std_logic_vector(4 downto 0); |
|
146 | 165 | Statu : out std_logic_vector(3 downto 0) |
|
147 | 166 | ); |
|
148 | 167 | end component; |
|
149 | 168 | |
|
150 | 169 | |
|
151 | 170 | component Dispatch is |
|
152 | 171 | generic( |
|
153 | 172 | Data_SZ : integer := 32); |
|
154 | 173 | port( |
|
155 | 174 | clk : in std_logic; |
|
156 | 175 | reset : in std_logic; |
|
157 | 176 | Acq : in std_logic; |
|
158 | 177 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
159 | 178 | Write : in std_logic; |
|
160 | 179 | Full : in std_logic_vector(1 downto 0); |
|
161 | 180 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
162 | 181 | FifoWrite : out std_logic_vector(1 downto 0); |
|
163 | 182 | Pong : out std_logic; |
|
164 | 183 | Error : out std_logic |
|
165 | 184 | ); |
|
166 | 185 | end component; |
|
167 | 186 | |
|
168 | 187 | |
|
169 | 188 | component DriveInputs is |
|
170 | 189 | port( |
|
171 | 190 | clk : in std_logic; |
|
172 | 191 | raz : in std_logic; |
|
173 | 192 | Read : in std_logic; |
|
174 | 193 | Conjugate : in std_logic; |
|
175 | 194 | Take : out std_logic; |
|
176 | 195 | ReadFIFO : out std_logic_vector(1 downto 0) |
|
177 | 196 | ); |
|
178 | 197 | end component; |
|
179 | 198 | |
|
180 | 199 | component Starter is |
|
181 | 200 | port( |
|
182 | 201 | clk : in std_logic; |
|
183 | 202 | raz : in std_logic; |
|
184 | 203 | Full : in std_logic_vector(1 downto 0); |
|
185 | 204 | Empty : in std_logic_vector(1 downto 0); |
|
186 | 205 | Statu : in std_logic_vector(3 downto 0); |
|
187 | 206 | Write : in std_logic; |
|
188 | 207 | Start : out std_logic |
|
189 | 208 | ); |
|
190 | 209 | end component; |
|
191 | 210 | |
|
192 | 211 | component ALU_Driver is |
|
193 | 212 | generic( |
|
194 | 213 | Input_SZ_1 : integer := 16; |
|
195 | 214 | Input_SZ_2 : integer := 16); |
|
196 | 215 | port( |
|
197 | 216 | clk : in std_logic; |
|
198 | 217 | reset : in std_logic; |
|
199 | 218 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
200 | 219 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
201 | 220 | Take : in std_logic; |
|
202 | 221 | Received : in std_logic; |
|
203 | 222 | Conjugate : in std_logic; |
|
204 | 223 | Valid : out std_logic; |
|
205 | 224 | Read : out std_logic; |
|
206 | 225 | CTRL : out std_logic_vector(4 downto 0); |
|
207 | 226 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); |
|
208 | 227 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) |
|
209 | 228 | ); |
|
210 | 229 | end component; |
|
211 | 230 | |
|
212 | 231 | |
|
213 | 232 | component ALU_v2 is |
|
214 | 233 | generic( |
|
215 | 234 | Arith_en : integer := 1; |
|
216 | 235 | Logic_en : integer := 1; |
|
217 | 236 | Input_SZ_1 : integer := 16; |
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218 | 237 | Input_SZ_2 : integer := 9); |
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219 | 238 | port( |
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220 | 239 | clk : in std_logic; |
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221 | 240 | reset : in std_logic; |
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222 | 241 | ctrl : in std_logic_vector(4 downto 0); |
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223 | 242 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
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224 | 243 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
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225 | 244 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) |
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226 | 245 | ); |
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227 | 246 | end component; |
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228 | 247 | |
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229 | 248 | |
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230 | 249 | component MAC_v2 is |
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231 | 250 | generic( |
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232 | 251 | Input_SZ_A : integer := 8; |
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233 | 252 | Input_SZ_B : integer := 8); |
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234 | 253 | port( |
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235 | 254 | clk : in std_logic; |
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236 | 255 | reset : in std_logic; |
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237 | 256 | clr_MAC : in std_logic; |
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238 | 257 | MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); |
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239 | 258 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
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240 | 259 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
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241 | 260 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) |
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242 | 261 | ); |
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243 | 262 | end component; |
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244 | 263 | |
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245 | 264 | |
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246 | 265 | component TwoComplementer is |
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247 | 266 | generic( |
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248 | 267 | Input_SZ : integer := 16); |
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249 | 268 | port( |
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250 | 269 | clk : in std_logic; |
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251 | 270 | reset : in std_logic; |
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252 | 271 | clr : in std_logic; |
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253 | 272 | TwoComp : in std_logic; |
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254 | 273 | OP : in std_logic_vector(Input_SZ-1 downto 0); |
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255 | 274 | RES : out std_logic_vector(Input_SZ-1 downto 0) |
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256 | 275 | ); |
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257 | 276 | end component; |
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258 | 277 | |
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259 | 278 | end; No newline at end of file |
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