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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | -- jean-christophe.pellion@easii-ic.com |
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22 | 22 | ------------------------------------------------------------------------------- |
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23 | 23 | -- 1.0 - initial version |
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24 | 24 | ------------------------------------------------------------------------------- |
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25 | 25 | LIBRARY ieee; |
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26 | 26 | USE ieee.std_logic_1164.ALL; |
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27 | 27 | USE ieee.numeric_std.ALL; |
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28 | 28 | LIBRARY grlib; |
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29 | 29 | USE grlib.amba.ALL; |
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30 | 30 | USE grlib.stdlib.ALL; |
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31 | 31 | USE grlib.devices.ALL; |
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32 | 32 | |
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33 | 33 | LIBRARY lpp; |
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34 | 34 | USE lpp.lpp_amba.ALL; |
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35 | 35 | USE lpp.apb_devices_list.ALL; |
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36 | 36 | USE lpp.lpp_memory.ALL; |
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37 | 37 | USE lpp.lpp_dma_pkg.ALL; |
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38 | 38 | USE lpp.general_purpose.ALL; |
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39 | 39 | --USE lpp.lpp_waveform_pkg.ALL; |
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40 | 40 | LIBRARY techmap; |
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41 | 41 | USE techmap.gencomp.ALL; |
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42 | 42 | |
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43 | 43 | |
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44 | 44 | ENTITY lpp_dma_SEND16B_FIFO2DMA IS |
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45 | 45 | GENERIC ( |
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46 | 46 | hindex : INTEGER := 2; |
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47 | 47 | vendorid : IN INTEGER := 0; |
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48 | 48 | deviceid : IN INTEGER := 0; |
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49 | 49 | version : IN INTEGER := 0 |
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50 | 50 | ); |
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51 | 51 | PORT ( |
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52 | 52 | clk : IN STD_LOGIC; |
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53 | 53 | rstn : IN STD_LOGIC; |
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54 | 54 | |
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55 | 55 | -- AMBA AHB Master Interface |
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56 | 56 | AHB_Master_In : IN AHB_Mst_In_Type; |
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57 | 57 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
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58 | 58 | |
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59 | 59 | -- FIFO Interface |
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60 | 60 | ren : OUT STD_LOGIC; |
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61 | 61 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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62 | 62 | |
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63 | 63 | -- Controls |
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64 | 64 | send : IN STD_LOGIC; |
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65 | 65 | valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
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66 | 66 | done : OUT STD_LOGIC; |
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67 | 67 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
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68 | 68 | ); |
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69 | 69 | END; |
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70 | 70 | |
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71 | 71 | ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS |
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72 | 72 | |
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73 | 73 | CONSTANT HConfig : AHB_Config_Type := ( |
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74 | 74 | 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0), |
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75 | 75 | OTHERS => (OTHERS => '0')); |
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76 | 76 | |
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77 | 77 | TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA); |
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78 | 78 | SIGNAL state : AHB_DMA_FSM_STATE; |
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79 | 79 | |
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80 | 80 | SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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81 | 81 | SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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82 | 82 | |
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83 | 83 | SIGNAL data_window : STD_LOGIC; |
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84 | 84 | SIGNAL ctrl_window : STD_LOGIC; |
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85 | 85 | |
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86 | 86 | SIGNAL bus_request : STD_LOGIC; |
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87 | 87 | SIGNAL bus_lock : STD_LOGIC; |
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88 | 88 | |
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89 | 89 | BEGIN |
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90 | 90 | |
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91 | 91 | ----------------------------------------------------------------------------- |
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92 | 92 | AHB_Master_Out.HCONFIG <= HConfig; |
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93 | 93 | AHB_Master_Out.HSIZE <= "010"; --WORDS 32b |
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94 | 94 | AHB_Master_Out.HINDEX <= hindex; |
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95 | 95 | AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS |
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96 | 96 | AHB_Master_Out.HIRQ <= (OTHERS => '0'); |
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97 | 97 | AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16 |
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98 | 98 | AHB_Master_Out.HWRITE <= '1'; |
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99 | 99 | |
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100 | 100 | --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE; |
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101 | 101 | |
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102 | 102 | --AHB_Master_Out.HBUSREQ <= bus_request; |
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103 | 103 | --AHB_Master_Out.HLOCK <= data_window; |
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104 | 104 | |
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105 | 105 | --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE |
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106 | 106 | -- '1' WHEN ctrl_window = '1' ELSE |
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107 | 107 | -- '0'; |
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108 | 108 | |
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109 | 109 | --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE |
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110 | 110 | -- '1' WHEN ctrl_window = '1' ELSE '0'; |
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111 | 111 | |
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112 | 112 | ----------------------------------------------------------------------------- |
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113 | 113 | AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; |
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114 | 114 | AHB_Master_Out.HWDATA <= ahbdrivedata(data); |
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115 | 115 | |
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116 | 116 | ----------------------------------------------------------------------------- |
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117 | 117 | --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY ); |
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118 | 118 | --ren <= NOT beat; |
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119 | 119 | ----------------------------------------------------------------------------- |
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120 | 120 | PROCESS (clk, rstn) |
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121 | 121 | BEGIN -- PROCESS |
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122 | 122 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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123 | 123 | state <= IDLE; |
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124 | 124 | done <= '0'; |
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125 | 125 | address_counter_reg <= (OTHERS => '0'); |
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126 | 126 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
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127 | 127 | AHB_Master_Out.HBUSREQ <= '0'; |
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128 | 128 | AHB_Master_Out.HLOCK <= '0'; |
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129 | 129 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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130 | 130 | done <= '0'; |
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131 | 131 | CASE state IS |
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132 | 132 | WHEN IDLE => |
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133 | 133 | AHB_Master_Out.HBUSREQ <= '0'; |
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134 | 134 | AHB_Master_Out.HLOCK <= '0'; |
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135 | 135 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
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136 | 136 | address_counter_reg <= (OTHERS => '0'); |
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137 | 137 | IF send = '1' THEN |
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138 | 138 | AHB_Master_Out.HBUSREQ <= '1'; |
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139 | 139 | AHB_Master_Out.HLOCK <= '1'; |
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140 | 140 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
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141 | 141 | state <= s_ARBITER; |
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142 | 142 | END IF; |
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143 | 143 | |
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144 | 144 | WHEN s_ARBITER => |
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145 | 145 | AHB_Master_Out.HBUSREQ <= '1'; |
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146 | 146 | AHB_Master_Out.HLOCK <= '1'; |
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147 | 147 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
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148 | 148 | address_counter_reg <= (OTHERS => '0'); |
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149 | 149 | |
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150 | 150 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN |
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151 | 151 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
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152 | 152 | state <= s_CTRL; |
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153 | 153 | END IF; |
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154 | 154 | |
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155 | 155 | WHEN s_CTRL => |
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156 | 156 | AHB_Master_Out.HBUSREQ <= '1'; |
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157 | 157 | AHB_Master_Out.HLOCK <= '1'; |
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158 | 158 | AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; |
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159 | 159 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN |
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160 | 160 | AHB_Master_Out.HTRANS <= HTRANS_SEQ; |
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161 | 161 | state <= s_CTRL_DATA; |
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162 | 162 | END IF; |
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163 | 163 | |
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164 | 164 | WHEN s_CTRL_DATA => |
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165 | 165 | AHB_Master_Out.HBUSREQ <= '1'; |
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166 | 166 | AHB_Master_Out.HLOCK <= '1'; |
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167 | 167 | AHB_Master_Out.HTRANS <= HTRANS_SEQ; |
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168 | 168 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN |
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169 | 169 | address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1); |
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170 | 170 | END IF; |
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171 | 171 | |
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172 | 172 | IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN |
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173 | 173 | AHB_Master_Out.HBUSREQ <= '0'; |
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174 | 174 | AHB_Master_Out.HLOCK <= '1';--'0'; |
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175 | 175 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
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176 | 176 | state <= s_DATA; |
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177 | 177 | END IF; |
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178 | 178 | |
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179 | 179 | WHEN s_DATA => |
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180 | 180 | AHB_Master_Out.HBUSREQ <= '0'; |
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181 | AHB_Master_Out.HLOCK <= '0'; | |
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181 | --AHB_Master_Out.HLOCK <= '0'; | |
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182 | 182 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
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183 | 183 | IF AHB_Master_In.HREADY = '1' THEN |
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184 | AHB_Master_Out.HLOCK <= '0'; | |
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184 | 185 | state <= IDLE; |
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185 | 186 | done <= '1'; |
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186 | 187 | END IF; |
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187 | 188 | |
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188 | 189 | WHEN OTHERS => NULL; |
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189 | 190 | END CASE; |
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190 | 191 | END IF; |
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191 | 192 | END PROCESS; |
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192 | 193 | |
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193 | 194 | ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0'; |
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194 | 195 | data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0'; |
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195 | 196 | ----------------------------------------------------------------------------- |
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196 | 197 | ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1'; |
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197 | 198 | |
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198 | 199 | ----------------------------------------------------------------------------- |
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199 | 200 | --PROCESS (clk, rstn) |
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200 | 201 | --BEGIN -- PROCESS |
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201 | 202 | -- IF rstn = '0' THEN -- asynchronous reset (active low) |
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202 | 203 | -- address_counter_reg <= (OTHERS => '0'); |
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203 | 204 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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204 | 205 | -- address_counter_reg <= address_counter; |
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205 | 206 | -- END IF; |
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206 | 207 | --END PROCESS; |
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207 | 208 | |
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208 | 209 | --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE |
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209 | 210 | -- address_counter_reg; |
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210 | 211 | ----------------------------------------------------------------------------- |
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211 | 212 | |
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212 | 213 | |
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213 | 214 | END Behavioral; |
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