leon3mp.srr
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| 1.1 MiB
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TextLexer
martin
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r284 | #Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 | ||
| #install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1 | ||||
| #OS: 6.1 | ||||
| #Hostname: PC-SOLAR2 | ||||
| #Implementation: synthesis | ||||
| #Thu Dec 19 12:48:21 2013 | ||||
| $ Start of Compile | ||||
| #Thu Dec 19 12:48:21 2013 | ||||
| Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 | ||||
| @N|Running in 32-bit mode | ||||
| Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved | ||||
| @N: CD720 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns | ||||
| @N:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":54:7:54:13|Top entity is set to leon3mp. | ||||
| @W: CD433 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\sparc\sparc_disas.vhd":720:24:720:24|No design units in file | ||||
| @W: CD266 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":270:15:270:22|dac_sclk is not readable. This may cause a simulation mismatch. | ||||
| @W: CD266 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":271:15:271:22|dac_data is not readable. This may cause a simulation mismatch. | ||||
| @W: CD266 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":272:15:272:22|dac_sync is not readable. This may cause a simulation mismatch. | ||||
| VHDL syntax check successful! | ||||
| Options changed - recompiling | ||||
| @N: CD231 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vhd\std_logic_textio.vhd":79:15:79:16|Using onehot encoding for type mvl9plus ('U'="1000000000") | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":54:7:54:13|Synthesizing work.leon3mp.behavioral | ||||
| @W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":384:2:384:8|Port lock of entity techmap.clkpad is unconnected | ||||
| @W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":386:2:386:8|Port clkc of entity techmap.clkgen is unconnected | ||||
| @W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":386:2:386:8|Port clkb of entity techmap.clkgen is unconnected | ||||
| @W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":386:2:386:8|Port clk2xu of entity techmap.clkgen is unconnected | ||||
| @W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":386:2:386:8|Port clk1xu of entity techmap.clkgen is unconnected | ||||
| @W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":386:2:386:8|Port clk4x of entity techmap.clkgen is unconnected | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":134:7:134:13|Signal resetnl is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":143:7:143:9|Signal cgi.clksel is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":143:7:143:9|Signal cgi.pllref is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_9.pindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_9.pconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_9.pconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_9.pirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_9.prdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_10.pindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_10.pconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_10.pconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_10.pirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_10.prdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_12.pindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_12.pconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_12.pconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_12.pirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_12.prdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_13.pindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_13.pconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_13.pconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_13.pirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_13.prdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_14.pindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_14.pconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_14.pconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_14.pirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_14.prdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_15.pindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_15.pconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_15.pconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_15.pirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":147:7:147:10|Signal apbo_15.prdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_15.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_14.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_13.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_12.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_11.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_10.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_9.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_8.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_7.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_6.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_5.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_4.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hcache is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hsplit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hrdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hresp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":149:7:149:11|Signal ahbso_3.hready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_15.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_14.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_13.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_12.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_11.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_10.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_9.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_8.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_7.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_6.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_5.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_4.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_3.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hconfig_0 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hconfig_1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hconfig_2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hconfig_3 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hconfig_4 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hconfig_5 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hconfig_6 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hconfig_7 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hirq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hprot is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.haddr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":151:7:151:11|Signal ahbmo_2.hbusreq is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":153:7:153:14|Signal ahbuarti.extclk is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":153:7:153:14|Signal ahbuarti.ctsn is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Signal memi.edac is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Signal memi.scb is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Signal memi.cb is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Signal memi.sd is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":160:7:160:9|Signal wpo.wprothit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":166:7:166:10|Signal gpti.wdogen is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Signal gpioi.sig_en is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Signal gpioi.sig_in is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 7 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 8 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 9 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 10 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 11 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 12 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 13 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 14 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 15 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 16 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 17 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 18 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 19 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 20 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 21 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 22 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 23 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 24 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 25 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 26 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 27 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 28 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 29 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 30 of signal gpioi.din is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 31 of signal gpioi.din is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":221:7:221:19|Signal fifoout_empty is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":222:7:222:18|Signal fifoout_data is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":225:7:225:14|Signal dma_read is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":229:7:229:15|Signal head_read is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":230:7:230:15|Signal head_data is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":231:7:231:16|Signal head_empty is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":232:7:232:17|Signal head_header is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":234:7:234:14|Signal head_val is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":243:7:243:9|Signal bwr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":244:7:244:9|Signal bre is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":245:7:245:13|Signal datatmp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":246:7:246:12|Signal fullup is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":247:7:247:13|Signal emptyup is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":248:7:248:14|Signal fulldown is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":249:7:249:15|Signal emptydown is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\iopad.vhd":32:7:32:11|Synthesizing techmap.iopad.rtl | ||||
| Post processing for techmap.iopad.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":45:7:45:12|Synthesizing gaisler.grgpio.rtl | ||||
| Post processing for gaisler.grgpio.rtl | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_6(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_5(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_4(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_3(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_2(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_1(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_0(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.bypass(6 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.ilat(6 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.edge(6 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.level(6 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.imask(6 downto 0) | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":47:7:47:13|Synthesizing gaisler.apbuart.rtl | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":77:15:77:16|Using sequential encoding for type txfsmtype | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":76:15:76:16|Using onehot encoding for type rxfsmtype (idle="10000") | ||||
| Post processing for gaisler.apbuart.rtl | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.rwaddr(0) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.tshift(10) is always 1, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.tcnt(1) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.rcnt(1) is always 0, optimizing ... | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Pruning Register bit 1 of r.tcnt(1 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Pruning Register bit 10 of r.tshift(10 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Pruning Register bit 1 of r.rcnt(1 downto 0) | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":47:7:47:13|Synthesizing gaisler.gptimer.rtl | ||||
| Post processing for gaisler.gptimer.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":43:7:43:13|Synthesizing grlib.apbctrl.rtl | ||||
| Post processing for grlib.apbctrl.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\outpad.vhd":32:7:32:12|Synthesizing techmap.outpad.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\outpad.vhd":39:7:39:10|Signal padx is undriven | ||||
| Post processing for techmap.outpad.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\inpad.vhd":32:7:32:11|Synthesizing techmap.inpad.rtl | ||||
| Post processing for techmap.inpad.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\ahbuart.vhd":45:7:45:13|Synthesizing gaisler.ahbuart.struct | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":35:7:35:10|Synthesizing gaisler.dcom.struct | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":49:21:49:22|Using onehot encoding for type dcom_state_type (idle="100000") | ||||
| Post processing for gaisler.dcom.struct | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":147:8:147:9|Pruning Register r.hresp(1 downto 0) | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":39:7:39:15|Synthesizing gaisler.dcom_uart.rtl | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":66:15:66:16|Using sequential encoding for type txfsmtype | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":65:15:65:16|Using sequential encoding for type rxfsmtype | ||||
| Post processing for gaisler.dcom_uart.rtl | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":49:4:49:5|uo.flow is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":49:4:49:5|uo.txen is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Register bit r.tshift(10) is always 1, optimizing ... | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Pruning Register bit 10 of r.tshift(10 downto 0) | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":35:7:35:12|Synthesizing gaisler.ahbmst.rtl | ||||
| Post processing for gaisler.ahbmst.rtl | ||||
| Post processing for gaisler.ahbuart.struct | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":37:7:37:13|Synthesizing grlib.ahbctrl.rtl | ||||
| Post processing for grlib.ahbctrl.rtl | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register r.lsplmst(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register reg0.r.defmst_3 | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register r.beat(3 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register r.hsize(2 downto 0) | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Register bit r.ldefmst is always 0, optimizing ... | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 0 of r.htrans(1 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 15 of r.haddr(15 downto 2) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 14 of r.haddr(15 downto 2) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 13 of r.haddr(15 downto 2) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 12 of r.haddr(15 downto 2) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 11 of r.haddr(15 downto 2) | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":34:7:34:18|Synthesizing lpp.ssram_plugin.ar_ssram_plugin | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":80:16:80:17|Using onehot encoding for type statet (idle="10000") | ||||
| Post processing for lpp.ssram_plugin.ar_ssram_plugin | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":172:4:172:5|Pruning Register OEreg | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":140:4:140:5|Pruning Register RAMSN_reg | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\outpad.vhd":115:7:115:13|Synthesizing techmap.outpadv.rtl | ||||
| Post processing for techmap.outpadv.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\iopad.vhd":137:7:137:12|Synthesizing techmap.iopadv.rtl | ||||
| Post processing for techmap.iopadv.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":46:7:46:11|Synthesizing esa.mctrl.rtl | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":120:18:120:19|Using onehot encoding for type memcycletype (idle="10000000") | ||||
| @W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":740:4:740:17|OTHERS clause is not synthesized | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|Signal sdmo.vhready is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|Signal sdmo.bsel is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|Signal sdmo.hsel is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":199:7:199:9|Signal sdi.merror is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.dqm is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.casn is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.rasn is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.sdwen is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.sdcsn is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.sdcke is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Signal rrsbdrive is undriven | ||||
| Post processing for esa.mctrl.rtl | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 0 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 1 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 2 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 3 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 4 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 5 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 6 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 7 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 8 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 9 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 10 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 11 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 12 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 13 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 14 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 15 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 16 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 17 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 18 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 19 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 20 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 21 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 22 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 23 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 24 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 25 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 26 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 27 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 28 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 29 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 30 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 31 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 32 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 33 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 34 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 35 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 36 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 37 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 38 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 39 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 40 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 41 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 42 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 43 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 44 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 45 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 46 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 47 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 48 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 49 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 50 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 51 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 52 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 53 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 54 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 55 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 56 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 57 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 58 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 59 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 60 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 61 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 62 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 63 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 0 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 1 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 2 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 3 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 4 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 5 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 6 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 7 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|lsdo.casn is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|lsdo.rasn is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|lsdo.sdwen is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 0 of signal lsdo.sdcsn is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 1 of signal lsdo.sdcsn is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 0 of signal lsdo.sdcke is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 1 of signal lsdo.sdcke is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":199:7:199:9|sdi.merror is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":199:7:199:9|sdi.idle is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|sdmo.vhready is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|sdmo.bsel is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|sdmo.hsel is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|memo.rs_edac_en is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|memo.sdram_en is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|memo.ce is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 0 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 1 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 2 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 3 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 4 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 5 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 6 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 7 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 8 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 9 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 10 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 11 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 12 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 13 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 14 of signal memo.sa is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 0 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 1 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 2 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 3 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 4 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 5 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 6 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 7 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 8 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 9 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 10 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 11 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 12 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 13 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 14 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 15 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 16 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 17 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 18 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 19 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 20 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 21 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 22 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 23 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 24 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 25 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 26 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 27 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 28 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 29 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 30 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 31 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 32 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 33 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 34 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 35 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 36 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 37 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 38 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 39 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 40 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 41 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 42 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 43 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 44 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 45 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 46 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 47 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 48 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 49 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 50 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 51 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 52 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 53 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 54 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 55 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 56 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 57 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 58 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 59 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 60 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 61 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 62 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 63 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register stdregs.rsbdrive_3(63 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sd(63 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sa(14 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.htrans(1 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sdhsel | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.hsel | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.haddr(31 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.mcfg2.sdren | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.mcfg2.srdis | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.mcfg2.brdyen | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register stdregs.r.nbdrive_3(3 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.ready8 | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.readdata(31 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sdwritedata(63 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.writedata8(15 downto 0) | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramsn(4) to a constant 1 | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 4 of r.ramsn(4 downto 0) | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":43:7:43:11|Synthesizing gaisler.irqmp.rtl | ||||
| Post processing for gaisler.irqmp.rtl | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":316:8:316:9|Pruning Register r.ibroadcast(15 downto 1) | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3.vhd":44:7:44:10|Synthesizing gaisler.dsu3.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":37:7:37:11|Synthesizing gaisler.dsu3x.rtl | ||||
| @W: CD434 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":164:79:164:86|Signal hrdata2x in the sensitivity list is not used in the process | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Signal tbo.data is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.break is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbwr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.write is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.read is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.mask is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.addr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.write is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.read is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.mask is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.addr is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.delaycnt is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.dcnten is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.bphit2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.bphit is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.enable is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.aindex is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.ahbactive is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hsel is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hmastlock is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hmaster is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hwdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hburst is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hsize is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.htrans is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hwrite is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.haddr is undriven | ||||
| Post processing for gaisler.dsu3x.rtl | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":158:13:158:16|rhin.irq is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.break is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbwr is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg2.write is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg2.read is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg1.write is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg1.read is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.dcnten is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.bphit2 is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.bphit is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.enable is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.ahbactive is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.hsel is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.hmastlock is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hmaster is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hmaster is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hmaster is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.hmaster is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 30 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 31 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hburst is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hburst is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hburst is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hsize is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hsize is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hsize is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.htrans is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.htrans is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.hwrite is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 30 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 31 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 0 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 1 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 2 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 3 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 4 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 5 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 6 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 7 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 8 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 9 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 10 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 11 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 12 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 13 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 14 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 15 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 16 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 17 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 18 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 19 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 20 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 21 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 22 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 23 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 24 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 25 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 26 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 27 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 28 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 29 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 30 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 31 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 32 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 33 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 34 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 35 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 36 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 37 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 38 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 39 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 40 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 41 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 42 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 43 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 44 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 45 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 46 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 47 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 48 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 49 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 50 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 51 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 52 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 53 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 54 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 55 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 56 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 57 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 58 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 59 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 60 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 61 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 62 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 63 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 64 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 65 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 66 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 67 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 68 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 69 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 70 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 71 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 72 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 73 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 74 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 75 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 76 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 77 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 78 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 79 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 80 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 81 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 82 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 83 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 84 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 85 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 86 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 87 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 88 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 89 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 90 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 91 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 92 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 93 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 94 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 95 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 96 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 97 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 98 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 99 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 100 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 101 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 102 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 103 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 104 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 105 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 106 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 107 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 108 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 109 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 110 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 111 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 112 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 113 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 114 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 115 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 116 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 117 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 118 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 119 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 120 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 121 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 122 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 123 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 124 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 125 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 126 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 127 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Pruning Register bit 1 of r.slv.haddr(24 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Pruning Register bit 0 of r.slv.haddr(24 downto 0) | ||||
| Post processing for gaisler.dsu3.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":158:7:158:12|Synthesizing gaisler.leon3s.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Signal tbo.data is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":241:7:241:9|Signal rd1 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":241:12:241:14|Signal rd2 is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":241:17:241:18|Signal wd is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":37:7:37:14|Synthesizing gaisler.cachemem.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":127:9:127:17|Signal ildataout is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":148:19:148:26|Signal ldataout is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":34:7:34:13|Synthesizing techmap.syncram.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":49:9:49:12|Signal rena is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":49:15:49:18|Signal wena is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":50:19:50:24|Signal databp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":50:27:50:34|Signal testdata is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":380:7:380:22|Synthesizing techmap.proasic3_syncram.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":178:7:178:25|Synthesizing techmap.proasic3_syncram_dp.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":33:7:33:21|Synthesizing techmap.proasic3_ram4k9.rtl | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":77:7:77:8|Bit 9 of signal qa is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":77:11:77:12|Bit 9 of signal qb is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":46:12:46:17|Synthesizing techmap.ram4k9.syn_black_box | ||||
| Post processing for techmap.ram4k9.syn_black_box | ||||
| Post processing for techmap.proasic3_ram4k9.rtl | ||||
| Post processing for techmap.proasic3_syncram_dp.rtl | ||||
| Post processing for techmap.proasic3_syncram.rtl | ||||
| Post processing for techmap.syncram.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":34:7:34:13|Synthesizing techmap.syncram.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":49:9:49:12|Signal rena is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":49:15:49:18|Signal wena is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":50:19:50:24|Signal databp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":50:27:50:34|Signal testdata is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":380:7:380:22|Synthesizing techmap.proasic3_syncram.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":120:7:120:24|Synthesizing techmap.proasic3_ram512x18.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":132:12:132:20|Synthesizing techmap.ram512x18.syn_black_box | ||||
| Post processing for techmap.ram512x18.syn_black_box | ||||
| Post processing for techmap.proasic3_ram512x18.rtl | ||||
| Post processing for techmap.proasic3_syncram_2p.rtl | ||||
| Post processing for techmap.proasic3_syncram.rtl | ||||
| Post processing for techmap.syncram.rtl | ||||
| Post processing for gaisler.cachemem.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\regfile_3p.vhd":32:7:32:16|Synthesizing techmap.regfile_3p.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
| @W: CD434 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":107:36:107:41|Signal testin in the sensitivity list is not used in the process | ||||
| @W: CD729 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":199:4:199:5|Component declaration has 3 generics but entity declares only 2 generics | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl | ||||
| Post processing for techmap.proasic3_syncram_2p.rtl | ||||
| Post processing for techmap.syncram_2p.rtl | ||||
| Post processing for techmap.regfile_3p.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\proc3.vhd":43:7:43:11|Synthesizing gaisler.proc3.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_cache.vhd":39:7:39:15|Synthesizing gaisler.mmu_cache.rtl | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":40:7:40:16|Synthesizing gaisler.mmu_acache.rtl | ||||
| @W: CD434 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":100:57:100:62|Signal hclken in the sensitivity list is not used in the process | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":96:7:96:8|Signal r2.hclken2 is undriven | ||||
| Post processing for gaisler.mmu_acache.rtl | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":96:7:96:8|r2.hclken2 is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 0 of signal mcdo.par is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 1 of signal mcdo.par is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 2 of signal mcdo.par is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 3 of signal mcdo.par is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 0 of signal mcio.par is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 1 of signal mcio.par is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 2 of signal mcio.par is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 3 of signal mcio.par is floating - a simulation mismatch is possible | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":41:7:41:16|Synthesizing gaisler.mmu_dcache.rtl | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":131:16:131:17|Using onehot encoding for type dstatetype (idle="100000000") | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":118:15:118:16|Using onehot encoding for type rdatatype (dtag="100000000") | ||||
| @W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1061:4:1061:17|OTHERS clause is not synthesized | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Signal rh.snmiss is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Signal rh.hitaddr is undriven | ||||
| Post processing for gaisler.mmu_dcache.rtl | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|rh.snmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 0 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 1 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 2 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 3 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 4 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 5 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 6 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 7 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.sdiag is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.sdiag is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.sdiag is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.sdiag is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|dcrami.spar is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 4 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 5 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 6 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 7 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 8 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 9 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 10 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 11 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 12 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 13 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 14 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 15 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 16 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 17 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 18 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 19 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|dco.cache is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 0 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 1 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 2 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 3 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.cache is always 1, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.cctrl.dsnoop is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.e is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.nf is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.pso is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.tlbdis is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.bar(0) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.bar(1) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.pagesize(0) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.pagesize(1) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(0) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(1) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(2) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(3) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(4) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(5) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(6) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(7) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(0) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(1) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(2) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(3) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(4) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(5) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(6) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(7) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(8) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(9) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(10) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(11) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(12) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(13) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(14) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(15) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(16) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(17) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(18) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(19) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(20) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(21) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(22) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(23) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(24) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(25) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(26) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(27) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(28) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(29) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.lock is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.flush_op is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.trans_op is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.dsuset(0) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.lrr is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.ilramen is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.ready is always 0, optimizing ... | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":37:7:37:16|Synthesizing gaisler.mmu_icache.rtl | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":162:16:162:17|Using sequential encoding for type istatetype | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":94:15:94:16|Using sequential encoding for type rdatatype | ||||
| @W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":474:4:474:17|OTHERS clause is not synthesized | ||||
| Post processing for gaisler.mmu_icache.rtl | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.dpar is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.dpar is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.dpar is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.dpar is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_0 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_1 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_2 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_3 is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.mhold is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.chold is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.tmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.cmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflushtyp | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflushaddr(31 downto 12) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflushr | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflush | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.diagset(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.setrepl(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.rndcnt(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.flush3 | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.lock is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.trans_op is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.lrr is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.cache is always 1, optimizing ... | ||||
| Post processing for gaisler.mmu_cache.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":42:7:42:9|Synthesizing gaisler.iu3.rtl | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":242:23:242:24|Using sequential encoding for type exception_state | ||||
| @N: CD364 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2808:4:2808:4|Removed redundant assignment | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2349:9:2349:17|Signal cpu_index is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2350:9:2350:15|Signal disasen is undriven | ||||
| Post processing for gaisler.iu3.rtl | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.su is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.wbhold is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.mhold is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.chold is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.tmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.cmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.mhold is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.chold is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.tmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.cmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.bpmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 0 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 1 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 2 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 3 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 4 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 5 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.fcnt is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":78:4:78:7|irqo.fpen is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":73:4:73:6|dci.flushl is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":71:4:71:6|ici.pnull is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":3026:6:3026:7|Pruning Register dsur.tbufcnt(5 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.w.except | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.w.wreg | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.w.wa(6 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.mac | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.asi(7 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.dsuen | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.lock | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.write | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.read | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.enaddr | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.m.casaz | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.m.mul | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.m.divz | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.e.mul | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldchkex | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldchkra | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldcheck2 | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldcheck1 | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.d.divrdy | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.divstart is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.mulstart is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.w.s.ec is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.w.s.ef is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(0) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(1) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(2) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(3) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(4) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(5) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.x.npc(2) is always 0, optimizing ... | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register bit 2 of r.x.npc(2 downto 0) | ||||
| Post processing for gaisler.proc3.rtl | ||||
| Post processing for gaisler.leon3s.rtl | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 0 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 1 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 2 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 3 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 4 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 5 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 6 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 7 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 8 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 9 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 10 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 11 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 12 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 13 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 14 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 15 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 16 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 17 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 18 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 19 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 20 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 21 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 22 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 23 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 24 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 25 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 26 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 27 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 28 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 29 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 30 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 31 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 32 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 33 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 34 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 35 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 36 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 37 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 38 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 39 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 40 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 41 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 42 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 43 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 44 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 45 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 46 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 47 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 48 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 49 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 50 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 51 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 52 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 53 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 54 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 55 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 56 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 57 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 58 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 59 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 60 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 61 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 62 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 63 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 64 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 65 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 66 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 67 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 68 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 69 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 70 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 71 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 72 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 73 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 74 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 75 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 76 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 77 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 78 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 79 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 80 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 81 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 82 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 83 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 84 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 85 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 86 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 87 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 88 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 89 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 90 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 91 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 92 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 93 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 94 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 95 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 96 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 97 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 98 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 99 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 100 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 101 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 102 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 103 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 104 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 105 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 106 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 107 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 108 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 109 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 110 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 111 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 112 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 113 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 114 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 115 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 116 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 117 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 118 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 119 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 120 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 121 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 122 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 123 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 124 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 125 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 126 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 127 of signal tbo.data is floating - a simulation mismatch is possible | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 0 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 1 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 2 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 3 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 4 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 5 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 6 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 7 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 8 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 9 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 10 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 11 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 12 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 13 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 14 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 15 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 16 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 17 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 18 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 19 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 20 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 21 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 22 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 23 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 24 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 25 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 26 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 27 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 28 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 29 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 30 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 31 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 32 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 33 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 34 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 35 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 36 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 37 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 38 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 39 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 40 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 41 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 42 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 43 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 44 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 45 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 46 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 47 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 48 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 49 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 50 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 51 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 52 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 53 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 54 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 55 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 56 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 57 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 58 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 59 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 60 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 61 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 62 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 63 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 64 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 65 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 66 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 67 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 68 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 69 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 70 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 71 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 72 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 73 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 74 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 75 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 76 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 77 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 78 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 79 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 80 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 81 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 82 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 83 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 84 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 85 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 86 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 87 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 88 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 89 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 90 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 91 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 92 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 93 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 94 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 95 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 96 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 97 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 98 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 99 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 100 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 101 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 102 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 103 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 104 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 105 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 106 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 107 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 108 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 109 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 110 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 111 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 112 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 113 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 114 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 115 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 116 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 117 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 118 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 119 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 120 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 121 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 122 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 123 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 124 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 125 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 126 of input tbo of instance p0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 127 of input tbo of instance p0 is floating | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":32:7:32:12|Synthesizing techmap.clkgen.struct | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":67:7:67:10|Signal lock is undriven | ||||
| Post processing for techmap.clkgen.struct | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":62:4:62:7|clkc is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":61:4:61:7|clkb is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":60:4:60:9|clk2xu is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":58:4:58:8|clk4x is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkpad.vhd":32:7:32:12|Synthesizing techmap.clkpad.rtl | ||||
| Post processing for techmap.clkpad.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\rstgen.vhd":29:7:29:12|Synthesizing gaisler.rstgen.rtl | ||||
| Post processing for gaisler.rstgen.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":36:7:36:14|Synthesizing lpp.apb_uart.ar_apb_uart | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":78:7:78:13|Signal temp_nd is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\UART.vhd":32:7:32:10|Synthesizing lpp.uart.ar_uart | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\Shift_REG.vhd":31:7:31:15|Synthesizing lpp.shift_reg.ar_shift_reg | ||||
| Post processing for lpp.shift_reg.ar_shift_reg | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\BaudGen.vhd":30:7:30:13|Synthesizing lpp.baudgen.ar_baudgen | ||||
| Post processing for lpp.baudgen.ar_baudgen | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\BaudGen.vhd":58:4:58:5|Feedback mux created for signal RX_reg. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| Post processing for lpp.uart.ar_uart | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\UART.vhd":81:4:81:5|Feedback mux created for signal RDATA[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\UART.vhd":81:4:81:5|Feedback mux created for signal Taken_reg. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| Post processing for lpp.apb_uart.ar_apb_uart | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 0 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 1 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 2 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 3 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 4 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 5 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 6 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 7 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 8 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 9 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 10 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 11 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 12 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 13 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 14 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 15 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 16 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 17 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 18 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 19 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 20 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 21 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 22 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 23 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 24 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 25 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 26 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 27 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 28 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 29 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 30 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 31 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Feedback mux created for signal Rdata[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Feedback mux created for signal Rec.UART_Cfg[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Feedback mux created for signal ACK. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Register bit Rdata(12) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Register bit Rdata(16) is always 0, optimizing ... | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 16 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 12 of Rdata(31 downto 0) | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":37:7:37:13|Synthesizing lpp.apb_dac.ar_apb_dac | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":74:7:74:11|Signal ready is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\DacDriver.vhd":30:7:30:15|Synthesizing lpp.dacdriver.ar_dacdriver | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Serialize.vhd":28:7:28:15|Synthesizing lpp.serialize.ar_serialize | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Serialize.vhd":42:10:42:11|Using sequential encoding for type etat | ||||
| Post processing for lpp.serialize.ar_serialize | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Serialize.vhd":96:8:96:9|Feedback mux created for signal send_reg. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Serialize.vhd":96:8:96:9|Optimizing register bit vector_int(0) to a constant 0 | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Serialize.vhd":96:8:96:9|Pruning Register bit 0 of vector_int(16 downto 0) | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Gene_SYNC.vhd":28:7:28:15|Synthesizing lpp.gene_sync.ar_gene_sync | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Gene_SYNC.vhd":46:10:46:11|Using sequential encoding for type etat | ||||
| Post processing for lpp.gene_sync.ar_gene_sync | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Gene_SYNC.vhd":52:8:52:9|Feedback mux created for signal SysClk_reg. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| Post processing for lpp.dacdriver.ar_dacdriver | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\ClkSetting.vhd":30:7:30:16|Synthesizing lpp.clksetting.ar_clksetting | ||||
| Post processing for lpp.clksetting.ar_clksetting | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Clock_Divider.vhd":28:7:28:19|Synthesizing lpp.clock_divider.ar_clock_divider | ||||
| Post processing for lpp.clock_divider.ar_clock_divider | ||||
| Post processing for lpp.apb_dac.ar_apb_dac | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 0 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 1 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 2 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 3 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 4 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 5 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 6 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 7 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 8 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 9 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 10 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 11 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 12 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 13 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 14 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 15 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 16 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 17 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 18 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 19 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 20 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 21 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 22 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 23 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 24 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 25 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 26 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 27 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 28 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 29 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 30 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":49:4:49:7|Bit 31 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Feedback mux created for signal Rdata[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Feedback mux created for signal Rec.DAC_Cfg[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":38:7:38:14|Synthesizing lpp.apb_fifo.ar_apb_fifo | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":115:13:115:14|Using sequential encoding for type state_t | ||||
| @W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":258:16:258:29|OTHERS clause is not synthesized | ||||
| @W: CG296 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":228:0:228:6|Incomplete sensitivity list - assuming completeness | ||||
| @W: CG290 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":235:39:235:44|Referenced variable sempty is not in sensitivity list | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Signal Rec_0.fifo_rdata is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 12 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 13 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 14 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 15 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 28 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 29 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 30 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 31 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 6 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 7 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 24 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 25 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 26 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 27 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 28 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 29 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 30 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 31 of signal fifo_id is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":111:7:111:18|Signal regdatavalid is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":112:7:112:13|Signal regdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":113:7:113:12|Signal regren is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":31:7:31:14|Synthesizing lpp.lpp_fifo.ar_lpp_fifo | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl | ||||
| Post processing for techmap.proasic3_syncram_2p.rtl | ||||
| Post processing for techmap.syncram_2p.rtl | ||||
| Post processing for lpp.lpp_fifo.ar_lpp_fifo | ||||
| Post processing for lpp.apb_fifo.ar_apb_fifo | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 0 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 1 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 2 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 3 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 4 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 5 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 6 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 7 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 8 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 9 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 10 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 11 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 12 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 13 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 14 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 15 of signal Rec_0.FIFO_Rdata is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 0 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 1 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 2 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 3 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 4 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 5 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 6 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 7 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 8 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 9 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 10 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 11 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 12 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 13 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 14 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 15 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 16 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 17 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 18 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 19 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 20 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 21 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 22 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 23 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 24 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 25 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 26 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 27 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 28 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 29 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 30 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 31 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":230:8:230:9|Pruning Register sRen_APB(0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(31) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(30) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(29) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(28) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(27) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(26) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(25) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(24) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(15) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(14) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(13) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(12) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(7) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(6) | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":239:12:239:15|Feedback mux created for signal sEmpty_d[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[1:1]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[2:2]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[3:3]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[4:4]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[5:5]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[8:8]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[9:9]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[10:10]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[11:11]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[16:16]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[17:17]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[18:18]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[19:19]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[20:20]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[21:21]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[22:22]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[23:23]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[6:6]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[7:7]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[12:12]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[13:13]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[14:14]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[15:15]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[24:24]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[25:25]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[26:26]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[27:27]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[28:28]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[29:29]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[30:30]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Feedback mux created for signal PRdata[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(6), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(7), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(12), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(13), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(14), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(15), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(24), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(25), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(26), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(27), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(28), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(29), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(30), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(31), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Register bit PRdata_cl(31) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Register bit PRdata(15) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Register bit PRdata(14) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Register bit PRdata(13) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Register bit PRdata(12) is always 1, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Register bit PRdata(18) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Register bit PRdata(17) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Register bit PRdata(3) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Register bit PRdata(2) is always 0, optimizing ... | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":38:7:38:14|Synthesizing lpp.apb_fifo.ar_apb_fifo | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":115:13:115:14|Using sequential encoding for type state_t | ||||
| @W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":258:16:258:29|OTHERS clause is not synthesized | ||||
| @W: CG296 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":228:0:228:6|Incomplete sensitivity list - assuming completeness | ||||
| @W: CG290 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":235:39:235:44|Referenced variable sempty is not in sensitivity list | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 12 of signal Rec_1.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 13 of signal Rec_1.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 14 of signal Rec_1.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 15 of signal Rec_1.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 28 of signal Rec_1.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 29 of signal Rec_1.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 30 of signal Rec_1.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 31 of signal Rec_1.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 12 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 13 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 14 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 15 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 28 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 29 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 30 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":91:7:91:9|Bit 31 of signal Rec_0.fifo_ctrl is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 6 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 7 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 24 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 25 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 26 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 27 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 28 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 29 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 30 of signal fifo_id is undriven | ||||
| @W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":93:7:93:13|Bit 31 of signal fifo_id is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":111:7:111:18|Signal regdatavalid is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":112:7:112:13|Signal regdata is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":113:7:113:12|Signal regren is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":31:7:31:14|Synthesizing lpp.lpp_fifo.ar_lpp_fifo | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl | ||||
| Post processing for techmap.proasic3_syncram_2p.rtl | ||||
| Post processing for techmap.syncram_2p.rtl | ||||
| Post processing for lpp.lpp_fifo.ar_lpp_fifo | ||||
| Post processing for lpp.apb_fifo.ar_apb_fifo | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 0 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 1 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 2 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 3 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 4 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 5 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 6 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 7 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 8 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 9 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 10 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 11 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 12 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 13 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 14 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 15 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 16 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 17 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 18 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 19 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 20 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 21 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 22 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 23 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 24 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 25 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 26 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 27 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 28 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 29 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 30 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":69:4:69:7|Bit 31 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 0 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 1 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 2 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 3 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 4 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 5 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 6 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 7 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 8 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 9 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 10 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 11 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 12 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 13 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 14 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 15 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 16 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 17 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 18 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 19 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 20 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 21 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 22 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 23 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 24 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 25 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 26 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 27 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 28 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 29 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 30 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 31 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 32 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 33 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 34 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 35 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 36 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 37 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 38 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 39 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 40 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 41 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 42 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 43 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 44 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 45 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 46 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 47 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 48 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 49 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 50 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 51 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 52 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 53 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 54 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 55 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 56 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 57 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 58 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 59 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 60 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 61 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 62 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Bit 63 of signal RDATA is floating - a simulation mismatch is possible | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Pruning Register Rec_1.FIFO_Wdata(31 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":194:12:194:13|Pruning Register sWen_APB(1 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":185:8:185:9|Pruning Register Rec_0.FIFO_Wdata(31 downto 0) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(31) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(30) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(29) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(28) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(27) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(26) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(25) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(24) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(15) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(14) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(13) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(12) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(7) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":226:16:226:17|Pruning Register apbo.prdata_cl(6) | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":233:16:233:26|Feedback mux created for signal sEmpty_d[1:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[1:1]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[2:2]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[3:3]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[4:4]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[5:5]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[8:8]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[9:9]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[10:10]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[11:11]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[16:16]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[17:17]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[18:18]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[19:19]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[20:20]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[21:21]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[22:22]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[23:23]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[6:6]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[7:7]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[12:12]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[13:13]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[14:14]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[15:15]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[24:24]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[25:25]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[26:26]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[27:27]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[28:28]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[29:29]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[30:30]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":196:24:196:25|Feedback mux created for signal PRdata[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(6), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(7), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(12), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(13), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(14), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(15), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(24), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(25), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(26), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(27), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(28), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(29), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(30), probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
| @W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":209:18:209:55|Latch generated from process for signal apbo.prdata(31), probably caused by a missing assignment in an if or case stmt | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd":28:7:28:22|Synthesizing lpp.matricespectrale.ar_matricespectrale | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\Dispatch.vhd":26:7:26:14|Synthesizing lpp.dispatch.ar_dispatch | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\Dispatch.vhd":45:10:45:11|Using sequential encoding for type etat | ||||
| Post processing for lpp.dispatch.ar_dispatch | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd":28:7:28:20|Synthesizing lpp.spectralmatrix.ar_spectralmatrix | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\GetResult.vhd":26:7:26:15|Synthesizing lpp.getresult.ar_getresult | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\GetResult.vhd":47:11:47:12|Using sequential encoding for type state | ||||
| Post processing for lpp.getresult.ar_getresult | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\Matrix.vhd":31:7:31:12|Synthesizing lpp.matrix.ar_matrix | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\ALU.vhd":30:7:30:9|Synthesizing lpp.alu.ar_alu | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC.vhd":32:7:32:9|Synthesizing lpp.mac.ar_mac | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC.vhd":80:9:80:19|Signal clr_mac_d_d is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC.vhd":81:9:81:24|Signal mac_mul_add_2c_d is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_MUX2.vhd":27:7:27:14|Synthesizing lpp.mac_mux2.ar_mac_mux2 | ||||
| Post processing for lpp.mac_mux2.ar_mac_mux2 | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_MUX.vhd":26:7:26:13|Synthesizing lpp.mac_mux.ar_mac_mux | ||||
| Post processing for lpp.mac_mux.ar_mac_mux | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_REG.vhd":26:7:26:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
| Post processing for lpp.mac_reg.ar_mac_reg | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_REG.vhd":26:7:26:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
| Post processing for lpp.mac_reg.ar_mac_reg | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_REG.vhd":26:7:26:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
| Post processing for lpp.mac_reg.ar_mac_reg | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\TwoComplementer.vhd":28:7:28:21|Synthesizing lpp.twocomplementer.ar_twocomplementer | ||||
| Post processing for lpp.twocomplementer.ar_twocomplementer | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Adder.vhd":26:7:26:11|Synthesizing lpp.adder.ar_adder | ||||
| Post processing for lpp.adder.ar_adder | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Multiplier.vhd":26:7:26:16|Synthesizing lpp.multiplier.ar_multiplier | ||||
| Post processing for lpp.multiplier.ar_multiplier | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd":29:7:29:19|Synthesizing lpp.mac_controler.ar_mac_controler | ||||
| Post processing for lpp.mac_controler.ar_mac_controler | ||||
| Post processing for lpp.mac.ar_mac | ||||
| Post processing for lpp.alu.ar_alu | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":30:7:30:16|Synthesizing lpp.alu_driver.ar_alu_driver | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":64:10:64:11|Using onehot encoding for type etat (ex="1000000000") | ||||
| Post processing for lpp.alu_driver.ar_alu_driver | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Feedback mux created for signal OP2[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Feedback mux created for signal OP1[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Feedback mux created for signal OP2re[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Feedback mux created for signal OP2im[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Feedback mux created for signal OP1re[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Feedback mux created for signal OP1im[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Optimizing register bit COMP(0) to a constant 0 | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Pruning Register bit 0 of COMP(1 downto 0) | ||||
| Post processing for lpp.matrix.ar_matrix | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\DriveInputs.vhd":26:7:26:17|Synthesizing lpp.driveinputs.ar_driveinputs | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\DriveInputs.vhd":43:11:43:12|Using onehot encoding for type state (stx="1000000") | ||||
| Post processing for lpp.driveinputs.ar_driveinputs | ||||
| Post processing for lpp.spectralmatrix.ar_spectralmatrix | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd":26:7:26:19|Synthesizing lpp.topspecmatrix.ar_topspecmatrix | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd":46:10:46:11|Using sequential encoding for type etat | ||||
| Post processing for lpp.topspecmatrix.ar_topspecmatrix | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":26:7:26:17|Synthesizing lpp.reuse_ctrlr.ar_reuse_ctrlr | ||||
| Post processing for lpp.reuse_ctrlr.ar_reuse_ctrlr | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(4) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(5) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(6) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(7) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(8) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(9) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(10) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(11) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(12) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(13) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(14) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(15) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(16) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(17) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(18) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(19) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(20) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(21) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(22) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(23) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(24) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(25) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(26) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(27) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(28) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(29) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(30) assign '0', register removed by optimization | ||||
| @W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd":54:8:54:9|All reachable assignments to MatrixParam_Reg(31) assign '0', register removed by optimization | ||||
| Post processing for lpp.matricespectrale.ar_matricespectrale | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lppFIFOxN.vhd":31:7:31:15|Synthesizing lpp.lppfifoxn.ar_lppfifoxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":31:7:31:14|Synthesizing lpp.lpp_fifo.ar_lpp_fifo | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":113:7:113:24|Synthesizing techmap.generic_syncram_2p.behav | ||||
| Post processing for techmap.generic_syncram_2p.behav | ||||
| @N: CL134 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Found RAM rfd, depth=256, width=16 | ||||
| Post processing for techmap.syncram_2p.rtl | ||||
| Post processing for lpp.lpp_fifo.ar_lpp_fifo | ||||
| Post processing for lpp.lppfifoxn.ar_lppfifoxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\FFT.vhd":31:7:31:9|Synthesizing lpp.fft.ar_fft | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":26:7:26:16|Synthesizing lpp.linker_fft.ar_linker | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":49:10:49:11|Using sequential encoding for type etat | ||||
| Post processing for lpp.linker_fft.ar_linker | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":63:8:63:9|Feedback mux created for signal DATA[79:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":63:8:63:9|Feedback mux created for signal DataTmp[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd":33:7:33:13|Synthesizing lpp.corefft.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":592:7:592:15|Synthesizing lpp.autoscale.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":100:7:100:16|Synthesizing lpp.edgedetect.translated | ||||
| Post processing for lpp.edgedetect.translated | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":127:4:127:5|Pruning Register in_pipe | ||||
| Post processing for lpp.autoscale.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":450:7:450:13|Synthesizing lpp.outbuff.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":561:7:561:13|Synthesizing lpp.wrapram.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actram.vhd":8:7:8:12|Synthesizing lpp.actram.def_arch | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2967:10:2967:18|Synthesizing proasic3.ram512x18.syn_black_box | ||||
| Post processing for proasic3.ram512x18.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":1782:10:1782:12|Synthesizing proasic3.gnd.syn_black_box | ||||
| Post processing for proasic3.gnd.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2722:10:2722:12|Synthesizing proasic3.vcc.syn_black_box | ||||
| Post processing for proasic3.vcc.syn_black_box | ||||
| Post processing for lpp.actram.def_arch | ||||
| Post processing for lpp.wrapram.rtl | ||||
| Post processing for lpp.outbuff.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":21:7:21:12|Synthesizing lpp.switch.translated | ||||
| Post processing for lpp.switch.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":517:7:517:13|Synthesizing lpp.twidlut.translated | ||||
| Post processing for lpp.twidlut.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\twiddle.vhd":22:7:22:13|Synthesizing lpp.twiddle.translated | ||||
| Post processing for lpp.twiddle.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":183:7:183:11|Synthesizing lpp.bfly2.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":118:7:118:10|Synthesizing lpp.agen.rtl | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":72:7:72:14|Synthesizing lpp.kitrndup.rtl | ||||
| Post processing for lpp.kitrndup.rtl | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":94:4:94:5|Pruning bit 0 of int_outp(16 downto 0) - not in use ... | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":8:7:8:11|Synthesizing lpp.actar.def_arch | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":14:10:14:13|Synthesizing proasic3.and2.syn_black_box | ||||
| Post processing for proasic3.and2.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2825:10:2825:13|Synthesizing proasic3.xor3.syn_black_box | ||||
| Post processing for proasic3.xor3.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2093:10:2093:13|Synthesizing proasic3.nor2.syn_black_box | ||||
| Post processing for proasic3.nor2.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":137:10:137:12|Synthesizing proasic3.ao1.syn_black_box | ||||
| Post processing for proasic3.ao1.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":1996:10:1996:12|Synthesizing proasic3.mx2.syn_black_box | ||||
| Post processing for proasic3.mx2.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2817:10:2817:13|Synthesizing proasic3.xor2.syn_black_box | ||||
| Post processing for proasic3.xor2.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":1374:10:1374:13|Synthesizing proasic3.dfn1.syn_black_box | ||||
| Post processing for proasic3.dfn1.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":38:10:38:13|Synthesizing proasic3.and3.syn_black_box | ||||
| Post processing for proasic3.and3.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":191:10:191:13|Synthesizing proasic3.aoi1.syn_black_box | ||||
| Post processing for proasic3.aoi1.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":1942:10:1942:13|Synthesizing proasic3.maj3.syn_black_box | ||||
| Post processing for proasic3.maj3.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2852:10:2852:13|Synthesizing proasic3.buff.syn_black_box | ||||
| Post processing for proasic3.buff.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2222:10:2222:12|Synthesizing proasic3.or3.syn_black_box | ||||
| Post processing for proasic3.or3.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2782:10:2782:14|Synthesizing proasic3.xnor2.syn_black_box | ||||
| Post processing for proasic3.xnor2.syn_black_box | ||||
| @N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":22:10:22:14|Synthesizing proasic3.and2a.syn_black_box | ||||
| Post processing for proasic3.and2a.syn_black_box | ||||
| Post processing for lpp.actar.def_arch | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":3405:4:3405:10|Pruning instance AND2_97 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":3322:4:3322:10|Pruning instance AND2_84 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":3270:4:3270:10|Pruning instance XOR2_77 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":3198:4:3198:10|Pruning instance AND2_41 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":3019:4:3019:11|Pruning instance AND2_152 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2971:4:2971:9|Pruning instance AO1_49 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2926:4:2926:11|Pruning instance AND2_200 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2885:4:2885:11|Pruning instance AND2_242 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2856:4:2856:11|Pruning instance AND2_130 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2837:4:2837:11|Pruning instance AND2_234 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2806:4:2806:11|Pruning instance AND2_117 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2750:4:2750:11|Pruning instance AND2_159 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2696:4:2696:10|Pruning instance AND2_89 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2539:4:2539:11|Pruning instance AND2_235 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2526:4:2526:10|Pruning instance AND2_59 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2421:4:2421:9|Pruning instance AO1_81 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2329:4:2329:10|Pruning instance AND2_15 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2304:4:2304:11|Pruning instance AND2_213 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2247:4:2247:9|Pruning instance AO1_32 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2122:4:2122:10|Pruning instance AND2_34 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2070:4:2070:11|Pruning instance XOR2_111 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2066:4:2066:11|Pruning instance AND2_228 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1976:4:1976:11|Pruning instance AND2_220 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1875:4:1875:10|Pruning instance AND2_58 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1830:4:1830:10|Pruning instance AND2_95 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1759:4:1759:11|Pruning instance AND2_231 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1704:4:1704:11|Pruning instance AND2_100 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1687:4:1687:9|Pruning instance AND2_7 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1678:4:1678:9|Pruning instance AND2_1 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1651:4:1651:11|Pruning instance AND2_105 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1525:4:1525:11|Pruning instance AND2_172 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1489:4:1489:11|Pruning instance AND2_195 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1430:4:1430:10|Pruning instance AND2_39 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":1367:4:1367:11|Pruning instance AND2_160 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":829:4:829:9|Pruning instance AO1_56 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":765:4:765:11|Pruning instance AND2_250 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":709:4:709:10|Pruning instance AND2_99 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":686:4:686:11|Pruning instance AND2_125 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":684:4:684:11|Pruning instance AND2_174 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":670:4:670:10|Pruning instance AND2_53 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":624:4:624:10|Pruning instance AND2_60 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":606:4:606:11|Pruning instance AND2_153 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":479:4:479:10|Pruning instance AND2_69 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":435:4:435:11|Pruning instance AND2_248 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":411:4:411:10|Pruning instance AND2_49 - not in use ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":380:4:380:11|Pruning instance AND2_225 - not in use ... | ||||
| Post processing for lpp.agen.rtl | ||||
| Post processing for lpp.bfly2.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":383:7:383:16|Synthesizing lpp.pipobuffer.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":308:7:308:14|Synthesizing lpp.inbuffer.translated | ||||
| Post processing for lpp.inbuffer.translated | ||||
| Post processing for lpp.pipobuffer.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":503:7:503:12|Synthesizing lpp.sm_top.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":410:7:410:13|Synthesizing lpp.outbufa.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":23:7:23:13|Synthesizing lpp.counter.translated | ||||
| Post processing for lpp.counter.translated | ||||
| Post processing for lpp.outbufa.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":282:7:282:16|Synthesizing lpp.inbuf_ffta.translated | ||||
| Post processing for lpp.inbuf_ffta.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":356:7:356:16|Synthesizing lpp.twid_wamod.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":69:7:69:14|Synthesizing lpp.bcounter.translated | ||||
| Post processing for lpp.bcounter.translated | ||||
| Post processing for lpp.twid_wamod.translated | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":393:4:393:5|Feedback mux created for signal rstAfterInit_int. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":393:4:393:5|Feedback mux created for signal preRstAfterInit. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":22:7:22:13|Synthesizing lpp.twid_ra.translated | ||||
| Post processing for lpp.twid_ra.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":193:7:193:15|Synthesizing lpp.inbuf_lda.translated | ||||
| Post processing for lpp.inbuf_lda.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":148:7:148:16|Synthesizing lpp.wrffttimer.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":23:7:23:13|Synthesizing lpp.counter.translated | ||||
| Post processing for lpp.counter.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":23:7:23:13|Synthesizing lpp.counter.translated | ||||
| Post processing for lpp.counter.translated | ||||
| Post processing for lpp.wrffttimer.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":67:7:67:16|Synthesizing lpp.rdffttimer.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":23:7:23:13|Synthesizing lpp.counter.translated | ||||
| Post processing for lpp.counter.translated | ||||
| Post processing for lpp.rdffttimer.translated | ||||
| Post processing for lpp.sm_top.translated | ||||
| Post processing for lpp.corefft.translated | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":26:7:26:16|Synthesizing lpp.driver_fft.ar_driver | ||||
| @N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":47:10:47:11|Using sequential encoding for type etat | ||||
| Post processing for lpp.driver_fft.ar_driver | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(0) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(1) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(2) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(3) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(4) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(5) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(6) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(7) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(8) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(9) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(10) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(11) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(12) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(13) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(14) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Optimizing register bit Data_im(15) to a constant 0 | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Pruning Register Data_im(15 downto 0) | ||||
| Post processing for lpp.fft.ar_fft | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_demux\DEMUX.vhd":26:7:26:11|Synthesizing lpp.demux.ar_demux | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_demux\DEMUX.vhd":54:10:54:11|Using onehot encoding for type etat (ex="10000") | ||||
| Post processing for lpp.demux.ar_demux | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lppFIFOxN.vhd":31:7:31:15|Synthesizing lpp.lppfifoxn.ar_lppfifoxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":31:7:31:14|Synthesizing lpp.lpp_fifo.ar_lpp_fifo | ||||
| Post processing for lpp.lpp_fifo.ar_lpp_fifo | ||||
| Post processing for lpp.lppfifoxn.ar_lppfifoxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lppFIFOxN.vhd":31:7:31:15|Synthesizing lpp.lppfifoxn.ar_lppfifoxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":31:7:31:14|Synthesizing lpp.lpp_fifo.ar_lpp_fifo | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":113:7:113:24|Synthesizing techmap.generic_syncram_2p.behav | ||||
| Post processing for techmap.generic_syncram_2p.behav | ||||
| @N: CL134 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Found RAM rfd, depth=512, width=16 | ||||
| Post processing for techmap.syncram_2p.rtl | ||||
| Post processing for lpp.lpp_fifo.ar_lpp_fifo | ||||
| Post processing for lpp.lppfifoxn.ar_lppfifoxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_acq.vhd":12:7:12:17|Synthesizing lpp.lpp_top_acq.tb | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_acq.vhd":84:9:84:24|Signal downsampling_cnt is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_acq.vhd":85:9:85:35|Signal sample_downsampling_out_val is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_acq.vhd":86:9:86:31|Signal sample_downsampling_out is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":28:7:28:18|Synthesizing lpp.downsampling.beh | ||||
| Post processing for lpp.downsampling.beh | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":28:7:28:18|Synthesizing lpp.downsampling.beh | ||||
| Post processing for lpp.downsampling.beh | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":28:7:28:18|Synthesizing lpp.downsampling.beh | ||||
| Post processing for lpp.downsampling.beh | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":28:7:28:18|Synthesizing lpp.downsampling.beh | ||||
| Post processing for lpp.downsampling.beh | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd":34:7:34:22|Synthesizing lpp.iir_cel_ctrlr_v2.ar_iir_cel_ctrlr_v2 | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":30:7:30:30|Synthesizing lpp.iir_cel_ctrlr_v2_control.ar_iir_cel_ctrlr_v2_control | ||||
| @N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":59:20:59:21|Using onehot encoding for type fsmiir_cel_t (waiting="1000000000") | ||||
| Post processing for lpp.iir_cel_ctrlr_v2_control.ar_iir_cel_ctrlr_v2_control | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 31 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 30 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 29 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 28 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 27 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 26 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 25 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 24 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 23 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 22 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 21 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 20 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 19 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 18 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 17 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 16 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 15 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 14 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 13 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 12 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 11 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 10 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 9 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 8 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 7 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 6 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Pruning bit 5 of alu_selected_coeff(31 downto 0) - not in use ... | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd":31:7:31:31|Synthesizing lpp.iir_cel_ctrlr_v2_dataflow.ar_iir_cel_ctrlr_v2_dataflow | ||||
| @N: CD364 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd":108:21:108:33|Removed redundant assignment | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\ALU.vhd":30:7:30:9|Synthesizing lpp.alu.ar_alu | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC.vhd":32:7:32:9|Synthesizing lpp.mac.ar_mac | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC.vhd":80:9:80:19|Signal clr_mac_d_d is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC.vhd":81:9:81:24|Signal mac_mul_add_2c_d is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_MUX2.vhd":27:7:27:14|Synthesizing lpp.mac_mux2.ar_mac_mux2 | ||||
| Post processing for lpp.mac_mux2.ar_mac_mux2 | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_MUX.vhd":26:7:26:13|Synthesizing lpp.mac_mux.ar_mac_mux | ||||
| Post processing for lpp.mac_mux.ar_mac_mux | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_REG.vhd":26:7:26:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
| Post processing for lpp.mac_reg.ar_mac_reg | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_REG.vhd":26:7:26:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
| Post processing for lpp.mac_reg.ar_mac_reg | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC_REG.vhd":26:7:26:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
| Post processing for lpp.mac_reg.ar_mac_reg | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Adder.vhd":26:7:26:11|Synthesizing lpp.adder.ar_adder | ||||
| Post processing for lpp.adder.ar_adder | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Multiplier.vhd":26:7:26:16|Synthesizing lpp.multiplier.ar_multiplier | ||||
| Post processing for lpp.multiplier.ar_multiplier | ||||
| Post processing for lpp.mac.ar_mac | ||||
| Post processing for lpp.alu.ar_alu | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MUXN.vhd":28:7:28:10|Synthesizing lpp.muxn.ar_muxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MUXN.vhd":28:7:28:10|Synthesizing lpp.muxn.ar_muxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MUXN.vhd":28:7:28:10|Synthesizing lpp.muxn.ar_muxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MUXN.vhd":28:7:28:10|Synthesizing lpp.muxn.ar_muxn | ||||
| Post processing for lpp.muxn.ar_muxn | ||||
| Post processing for lpp.muxn.ar_muxn | ||||
| Post processing for lpp.muxn.ar_muxn | ||||
| Post processing for lpp.muxn.ar_muxn | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd":32:7:32:18|Synthesizing lpp.ram_ctrlr_v2.ar_ram_ctrlr_v2 | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd":59:8:59:10|Signal wen is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd":59:13:59:15|Signal ren is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
| @W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":113:7:113:24|Synthesizing techmap.generic_syncram_2p.behav | ||||
| Post processing for techmap.generic_syncram_2p.behav | ||||
| @N: CL134 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Found RAM rfd, depth=256, width=18 | ||||
| Post processing for techmap.syncram_2p.rtl | ||||
| Post processing for lpp.ram_ctrlr_v2.ar_ram_ctrlr_v2 | ||||
| Post processing for lpp.iir_cel_ctrlr_v2_dataflow.ar_iir_cel_ctrlr_v2_dataflow | ||||
| Post processing for lpp.iir_cel_ctrlr_v2.ar_iir_cel_ctrlr_v2 | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":31:7:31:17|Synthesizing lpp.ad7688_drvr.ar_ad7688_drvr | ||||
| @N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\SYNC_FF.vhd":26:7:26:13|Synthesizing lpp.sync_ff.beh | ||||
| Post processing for lpp.sync_ff.beh | ||||
| Post processing for lpp.ad7688_drvr.ar_ad7688_drvr | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning bit 15 of shift_reg_7(15 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning bit 15 of shift_reg_6(15 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning bit 15 of shift_reg_5(15 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning bit 15 of shift_reg_4(15 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning bit 15 of shift_reg_3(15 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning bit 15 of shift_reg_2(15 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning bit 15 of shift_reg_1(15 downto 0) - not in use ... | ||||
| @W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning bit 15 of shift_reg_0(15 downto 0) - not in use ... | ||||
| Post processing for lpp.lpp_top_acq.tb | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_acq.vhd":167:4:167:5|Pruning Register sample_filter_v2_out_r(0 to 143) | ||||
| @W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_acq.vhd":167:4:167:5|Pruning Register sample_filter_v2_out_r_val | ||||
| Post processing for work.leon3mp.behavioral | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 0 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 1 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 2 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 3 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 4 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 5 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 6 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 7 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 8 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 9 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 10 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 11 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 12 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 13 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 14 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 15 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 16 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 17 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 18 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 19 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 20 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 21 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 22 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 23 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 24 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 25 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 26 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 27 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 28 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 29 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 30 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 31 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 0 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 1 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 2 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 3 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 4 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 5 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 6 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 7 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 8 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 9 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 10 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 11 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 12 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 13 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 14 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 15 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 16 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 17 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 18 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 19 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 20 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 21 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 22 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 23 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 24 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 25 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 26 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 27 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 28 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 29 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 30 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":169:7:169:11|Bit 31 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":166:7:166:10|gpti.wdogen is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":160:7:160:9|wpo.wprothit is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|memi.edac is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 0 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 1 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 2 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 3 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 4 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 5 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 6 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 7 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 8 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 9 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 10 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 11 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 12 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 13 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 14 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 15 of signal memi.scb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 0 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 1 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 2 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 3 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 4 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 5 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 6 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 7 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 8 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 9 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 10 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 11 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 12 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 13 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 14 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 15 of signal memi.cb is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 0 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 1 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 2 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 3 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 4 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 5 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 6 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 7 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 8 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 9 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 10 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 11 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 12 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 13 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 14 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 15 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 16 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 17 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 18 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 19 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 20 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 21 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 22 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 23 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 24 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 25 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 26 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 27 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 28 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 29 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 30 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 31 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 32 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 33 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 34 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 35 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 36 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 37 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 38 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 39 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 40 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 41 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 42 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 43 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 44 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 45 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 46 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 47 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 48 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 49 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 50 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 51 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 52 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 53 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 54 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 55 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 56 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 57 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 58 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 59 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 60 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 61 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 62 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":158:7:158:10|Bit 63 of signal memi.sd is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":153:7:153:14|ahbuarti.extclk is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":153:7:153:14|ahbuarti.ctsn is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":143:7:143:9|Bit 0 of signal cgi.clksel is floating - a simulation mismatch is possible | ||||
| @W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":143:7:143:9|Bit 1 of signal cgi.clksel is floating - a simulation mismatch is possible | ||||
| @W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":143:7:143:9|cgi.pllref is not assigned a value (floating) - a simulation mismatch is possible | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 32 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 33 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 34 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 35 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 36 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 37 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 38 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 39 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 40 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 41 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 42 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 43 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 44 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 45 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 46 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 47 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 48 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 49 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 50 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 51 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 52 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 53 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 54 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 55 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 56 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 57 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 58 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 59 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 60 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 61 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 62 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 63 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 64 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 65 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 66 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 67 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 68 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 69 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 70 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 71 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 72 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 73 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 74 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 75 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 76 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 77 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 78 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 79 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 80 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 81 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 82 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 83 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 84 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 85 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 86 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 87 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 88 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 89 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 90 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 91 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 92 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 93 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 94 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":540:4:540:10|Bit 95 of input gpioi of instance grgpio0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":524:4:524:8|Bit 1 of input uarti of instance uart1 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":524:4:524:8|Bit 2 of input uarti of instance uart1 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":508:4:508:9|Bit 2 of input gpti of instance timer0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":486:4:486:8|Bit 1 of input uarti of instance dcom0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":486:4:486:8|Bit 2 of input uarti of instance dcom0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 41 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 42 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 43 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 44 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 45 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 46 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 47 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 48 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 49 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 50 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 51 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 52 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 53 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 54 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 55 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 56 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 57 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 58 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 59 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 60 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 61 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 62 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 63 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 64 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 65 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 66 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 67 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 68 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 69 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 70 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 71 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 72 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 73 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 74 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 75 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 76 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 77 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 78 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 79 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 80 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 81 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 82 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 83 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 84 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 85 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 86 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 87 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 88 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 89 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 90 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 91 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 92 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 93 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 94 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 95 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 96 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 97 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 98 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 99 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 100 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 101 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 102 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 103 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 104 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 105 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 106 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 107 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 108 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 109 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 110 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 111 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 112 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 113 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 114 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 115 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 116 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 117 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 118 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 119 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 120 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 121 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 122 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 123 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 124 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 125 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 126 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 127 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 128 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 129 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 130 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 131 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 132 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 133 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 134 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 135 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 136 of input memi of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Bit 137 of input memi of instance memctrlr is floating | ||||
| @W: CL167 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":449:4:449:11|Input wpo of instance memctrlr is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":386:2:386:8|Bit 0 of input cgi of instance clkgen0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":386:2:386:8|Bit 4 of input cgi of instance clkgen0 is floating | ||||
| @W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":386:2:386:8|Bit 5 of input cgi of instance clkgen0 is floating | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Optimizing register bit cnv_cycle_counter(31) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(6) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(7) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(8) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(9) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(10) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(11) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(12) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(13) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(14) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(15) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(16) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(17) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(18) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(19) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(20) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(21) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(22) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(23) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(24) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(25) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(26) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(27) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(28) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(29) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(30) to a constant 0 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Optimizing register bit sample_bit_counter(31) to a constant 0 | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 31 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 30 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 29 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 28 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 27 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 26 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 25 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 24 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 23 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 22 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 21 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 20 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 19 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 18 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 17 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 16 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 15 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 14 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 13 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 12 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 11 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 10 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 9 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 8 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 7 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":153:4:153:5|Pruning Register bit 6 of sample_bit_counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 31 of cnv_cycle_counter(31 downto 0) | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(30) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(29) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(28) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(27) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(26) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(25) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(24) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(23) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(22) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(21) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(20) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(19) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(18) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(17) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(16) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(15) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(14) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(13) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(12) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(11) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(10) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Register bit cnv_cycle_counter(9) is always 0, optimizing ... | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 30 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 29 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 28 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 27 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 26 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 25 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 24 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 23 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 22 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 21 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 20 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 19 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 18 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 17 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 16 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 15 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 14 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 13 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 12 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 11 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 10 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":83:4:83:5|Pruning Register bit 9 of cnv_cycle_counter(30 downto 0) | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":120:4:120:7|Input rclk is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":41:4:41:10|Input renable is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC.vhd":44:4:44:10|Input Comp_2C is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd":81:4:81:5|Trying to extract state machine for register IIR_CEL_STATE | ||||
| Extracted state machine for register IIR_CEL_STATE | ||||
| State machine has 10 reachable states with original encodings of: | ||||
| 0000000001 | ||||
| 0000000010 | ||||
| 0000000100 | ||||
| 0000001000 | ||||
| 0000010000 | ||||
| 0000100000 | ||||
| 0001000000 | ||||
| 0010000000 | ||||
| 0100000000 | ||||
| 1000000000 | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Optimizing register bit counter(31) to a constant 0 | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 31 of counter(31 downto 0) | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Optimizing register bit counter(30) to a constant 0 | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 30 of counter(30 downto 0) | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Optimizing register bit counter(29) to a constant 0 | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 29 of counter(29 downto 0) | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Optimizing register bit counter(28) to a constant 0 | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 28 of counter(28 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 31 of counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 30 of counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 29 of counter(29 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 28 of counter(28 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 31 of counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 30 of counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 29 of counter(29 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 28 of counter(28 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 31 of counter(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 30 of counter(30 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 29 of counter(29 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd":53:4:53:5|Pruning Register bit 28 of counter(28 downto 0) | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":120:4:120:7|Input rclk is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":41:4:41:10|Input renable is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":41:4:41:8|Input ReUse is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":41:4:41:8|Input ReUse is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_demux\DEMUX.vhd":68:8:68:9|Trying to extract state machine for register ect | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_demux\DEMUX.vhd":68:8:68:9|Pruning Register bit 0 of ect(0 to 4) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_demux\DEMUX.vhd":68:8:68:9|Pruning Register bit 4 of ect(0 to 4) | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":59:8:59:9|Trying to extract state machine for register ect | ||||
| Extracted state machine for register ect | ||||
| State machine has 4 reachable states with original encodings of: | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":413:13:413:17|Input clkEn is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":318:4:318:6|Input rEn is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":454:9:454:13|Input clkEn is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":105:9:105:13|Input clkEn is unused | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":620:4:620:5|Register bit ldMonitor is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":620:4:620:5|Register bit bflyMonitor is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":620:4:620:5|Register bit upScale_xhdl1 is always 0, optimizing ... | ||||
| @W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":614:2:614:8|Pruning instance fedge_0 - not in use ... | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":595:4:595:6|Input clk is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":595:9:595:13|Input clkEn is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":595:16:595:25|Input wLastStage is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":596:4:596:11|Input ldRiskOV is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":596:14:596:23|Input bflyRiskOV is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":597:4:597:12|Input startLoad is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":597:15:597:24|Input ifo_loadOn is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":598:4:598:15|Input bflyOutValid is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":598:18:598:25|Input startFFT is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":599:4:599:11|Input wEn_even is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":599:14:599:20|Input wEn_odd is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":63:8:63:9|Trying to extract state machine for register ect | ||||
| Extracted state machine for register ect | ||||
| State machine has 2 reachable states with original encodings of: | ||||
| 01 | ||||
| 10 | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":120:4:120:7|Input rclk is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":41:4:41:10|Input renable is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd":59:8:59:9|Trying to extract state machine for register ect | ||||
| Extracted state machine for register ect | ||||
| State machine has 3 reachable states with original encodings of: | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\DriveInputs.vhd":50:8:50:9|Trying to extract state machine for register ect | ||||
| Extracted state machine for register ect | ||||
| State machine has 7 reachable states with original encodings of: | ||||
| 0000001 | ||||
| 0000010 | ||||
| 0000100 | ||||
| 0001000 | ||||
| 0010000 | ||||
| 0100000 | ||||
| 1000000 | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Trying to extract state machine for register st | ||||
| Extracted state machine for register st | ||||
| State machine has 8 reachable states with original encodings of: | ||||
| 0000000001 | ||||
| 0000000010 | ||||
| 0000000100 | ||||
| 0000001000 | ||||
| 0000010000 | ||||
| 0000100000 | ||||
| 0001000000 | ||||
| 0010000000 | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":72:8:72:9|Trying to extract state machine for register ect | ||||
| Extracted state machine for register ect | ||||
| State machine has 10 reachable states with original encodings of: | ||||
| 0000000001 | ||||
| 0000000010 | ||||
| 0000000100 | ||||
| 0000001000 | ||||
| 0000010000 | ||||
| 0000100000 | ||||
| 0001000000 | ||||
| 0010000000 | ||||
| 0100000000 | ||||
| 1000000000 | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\GetResult.vhd":54:8:54:9|Trying to extract state machine for register ect | ||||
| Extracted state machine for register ect | ||||
| State machine has 4 reachable states with original encodings of: | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\Dispatch.vhd":54:8:54:9|Trying to extract state machine for register ect | ||||
| Extracted state machine for register ect | ||||
| State machine has 2 reachable states with original encodings of: | ||||
| 01 | ||||
| 10 | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":41:4:41:8|Input ReUse is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 117 to 52 of apbi(117 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bit 50 of apbi(117 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 15 to 8 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 6 to 0 of apbi(117 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":57:4:57:7|Input rclk is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":60:4:60:6|Input REN is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 117 to 66 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 15 to 11 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Input port bits 9 to 0 of apbi(117 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":58:4:58:7|Input wclk is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":59:4:59:8|Input ReUse is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":61:4:61:6|Input WEN is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd":65:4:65:8|Input WDATA is unused | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\ClkSetting.vhd":47:8:47:9|Pruning Register bit 7 of clockint(7 downto 0) | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Gene_SYNC.vhd":52:8:52:9|Trying to extract state machine for register ect | ||||
| Extracted state machine for register ect | ||||
| State machine has 4 reachable states with original encodings of: | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(1) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(2) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(3) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(7) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(8) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(9) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(10) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(11) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(12) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(13) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(14) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(15) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(16) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(17) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(18) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(19) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(20) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(21) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(22) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(23) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(24) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(25) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(26) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(27) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(28) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(29) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(30) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Register bit Rdata(31) is always 0, optimizing ... | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 31 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 30 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 29 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 28 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 27 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 26 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 25 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 24 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 23 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 22 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 21 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 20 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 19 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 18 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 17 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 16 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 15 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 14 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 13 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 12 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 11 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 10 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 9 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 8 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 7 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 3 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 2 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":107:8:107:9|Pruning Register bit 1 of Rdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 31 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 30 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 29 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 28 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 27 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 26 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 25 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 24 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 23 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 22 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 21 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 20 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 19 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 18 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 17 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 16 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 15 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 14 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 13 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 12 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 11 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 10 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 9 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 8 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 7 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 3 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":141:16:141:17|Pruning Register bit 2 of apbo.prdata(31 downto 0) | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":48:4:48:7|Input port bits 117 to 57 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":48:4:48:7|Input port bits 53 to 51 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":48:4:48:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":48:4:48:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":48:4:48:7|Input port bits 15 to 10 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd":48:4:48:7|Input port bits 8 to 0 of apbi(117 downto 0) are unused | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 16 of apbo.prdata(31 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 11 of Rdata(11 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 10 of Rdata(11 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 19 of Rdata(31 downto 17) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 18 of Rdata(31 downto 17) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 15 of Rdata(15 downto 13) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 14 of Rdata(15 downto 13) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 15 of apbo.prdata(15 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 14 of apbo.prdata(15 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 11 of apbo.prdata(15 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 10 of apbo.prdata(15 downto 0) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 19 of apbo.prdata(31 downto 17) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 18 of apbo.prdata(31 downto 17) | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 117 to 58 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 15 to 12 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 10 to 0 of apbi(117 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\rstgen.vhd":40:4:40:10|Input testrst is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\rstgen.vhd":41:4:41:9|Input testen is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkpad.vhd":36:49:36:52|Input rstn is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":56:4:56:6|Input cgi is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Trying to extract state machine for register r.d.cnt | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Trying to extract state machine for register r.x.rstate | ||||
| Extracted state machine for register r.x.rstate | ||||
| State machine has 4 reachable states with original encodings of: | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 203 to 200 of ico(203 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 198 to 167 of ico(203 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 165 to 134 of ico(203 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 132 to 131 of ico(203 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 129 to 128 of ico(203 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 95 to 0 of ico(203 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bits 207 to 134 of dco(210 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bit 131 of dco(210 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bits 129 to 128 of dco(210 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bits 95 to 0 of dco(210 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":77:4:77:7|Input port bits 30 to 4 of irqi(30 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":79:4:79:7|Input port bits 97 to 66 of dbgi(97 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":85:4:85:6|Input port bit 37 of fpo(69 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":85:4:85:6|Input port bits 35 to 0 of fpo(69 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":82:4:82:7|Input mulo is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":84:4:84:7|Input divo is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":87:4:87:6|Input cpo is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":89:4:89:6|Input tbo is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Trying to extract state machine for register r.istate | ||||
| Extracted state machine for register r.istate | ||||
| State machine has 3 reachable states with original encodings of: | ||||
| 00 | ||||
| 10 | ||||
| 11 | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 131 to 101 of ici(131 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 95 to 64 of ici(131 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 33 to 22 of ici(131 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 1 to 0 of ici(131 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":55:4:55:6|Input port bits 117 to 40 of dci(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":55:4:55:6|Input port bits 7 to 0 of dci(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 210 to 207 of dco(210 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 205 to 180 of dco(210 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 177 to 173 of dco(210 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bit 169 of dco(210 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 165 to 156 of dco(210 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 135 to 132 of dco(210 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 130 to 0 of dco(210 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":58:4:58:7|Input port bits 41 to 37 of mcio(41 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":60:4:60:9|Input port bits 319 to 256 of icramo(319 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":60:4:60:9|Input port bits 95 to 0 of icramo(319 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":62:4:62:9|Input port bits 117 to 85 of mmudci(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":62:4:62:9|Input port bits 76 to 0 of mmudci(117 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":64:4:64:9|Input mmuico is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Trying to extract state machine for register r.dstate | ||||
| Extracted state machine for register r.dstate | ||||
| State machine has 6 reachable states with original encodings of: | ||||
| 000000001 | ||||
| 000000010 | ||||
| 000001000 | ||||
| 001000000 | ||||
| 010000000 | ||||
| 100000000 | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bit 116 of dci(117 downto 0) is unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bit 113 of dci(117 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bits 71 to 52 of dci(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bits 41 to 40 of dci(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bits 7 to 5 of dci(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":70:4:70:6|Input port bits 203 to 199 of ico(203 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":70:4:70:6|Input port bit 166 of ico(203 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":70:4:70:6|Input port bits 130 to 0 of ico(203 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":72:4:72:7|Input port bits 43 to 38 of mcdo(45 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":73:4:73:8|Input port bits 139 to 28 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":73:4:73:8|Input port bits 19 to 0 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":75:4:75:9|Input port bits 451 to 384 of dcramo(451 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":75:4:75:9|Input port bits 363 to 256 of dcramo(451 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":78:4:78:9|Input port bits 110 to 2 of mmudco(110 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":79:4:79:7|Input sclk is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":355:4:355:5|Trying to extract state machine for register r.bo | ||||
| Extracted state machine for register r.bo | ||||
| State machine has 4 reachable states with original encodings of: | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":50:4:50:7|Input port bit 35 of mcii(35 downto 0) is unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":54:4:54:8|Input port bit 66 of mcmmi(69 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":56:4:56:7|Input port bits 87 to 85 of ahbi(87 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":56:4:56:7|Input port bits 83 to 51 of ahbi(87 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":56:4:56:7|Input port bits 14 to 0 of ahbi(87 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5503 to 5372 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5359 to 5357 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5343 to 5340 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5327 to 5325 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5311 to 5308 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5295 to 5293 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5279 to 5276 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5263 to 5261 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5247 to 5028 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5015 to 5013 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4999 to 4996 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4983 to 4981 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4967 to 4964 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4951 to 4949 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4935 to 4932 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4919 to 4917 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4903 to 4684 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4671 to 4669 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4655 to 4652 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4639 to 4637 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4623 to 4620 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4607 to 4605 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4591 to 4588 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4575 to 4573 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4559 to 4340 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4327 to 4325 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4311 to 4308 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4295 to 4293 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4279 to 4276 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4263 to 4261 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4247 to 4244 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4231 to 4229 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4215 to 3996 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3983 to 3981 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3967 to 3964 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3951 to 3949 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3935 to 3932 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3919 to 3917 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3903 to 3900 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3887 to 3885 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3871 to 3652 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3639 to 3637 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3623 to 3620 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3607 to 3605 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3591 to 3588 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3575 to 3573 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3559 to 3556 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3543 to 3541 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3527 to 3308 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3295 to 3293 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3279 to 3276 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3263 to 3261 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3247 to 3244 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3231 to 3229 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3215 to 3212 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3199 to 3197 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3183 to 2964 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2951 to 2949 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2935 to 2932 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2919 to 2917 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2903 to 2900 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2887 to 2885 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2871 to 2868 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2855 to 2853 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2839 to 2620 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2607 to 2605 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2591 to 2588 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2575 to 2573 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2559 to 2556 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2543 to 2541 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2527 to 2524 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2511 to 2509 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2495 to 2276 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2263 to 2261 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2247 to 2244 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2231 to 2229 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2215 to 2212 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2199 to 2197 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2183 to 2180 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2167 to 2165 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2151 to 1932 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1919 to 1917 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1903 to 1900 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1887 to 1885 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1871 to 1868 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1855 to 1853 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1839 to 1836 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1823 to 1821 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1807 to 1588 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1575 to 1573 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1559 to 1556 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1543 to 1541 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1527 to 1524 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1511 to 1509 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1495 to 1492 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1479 to 1477 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1463 to 1244 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1231 to 1229 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1215 to 1212 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1199 to 1197 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1183 to 1180 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1167 to 1165 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1151 to 1148 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1135 to 1133 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1119 to 900 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 887 to 885 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 871 to 868 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 855 to 853 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 839 to 836 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 823 to 821 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 807 to 804 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 791 to 789 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 775 to 556 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 543 to 541 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 527 to 524 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 511 to 509 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 495 to 492 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 479 to 477 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 463 to 460 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 447 to 445 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 431 to 212 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 199 to 197 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 183 to 180 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 167 to 165 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 151 to 148 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 135 to 133 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 119 to 116 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 103 to 101 of ahbso(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 87 to 0 of ahbso(5503 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":59:4:59:9|Input hclken is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_cache.vhd":88:4:88:7|Input hclk is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":127:4:127:6|Input wea is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":44:4:44:9|Input testin is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":188:4:188:11|Input address2 is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":189:4:189:10|Input datain2 is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd":44:4:44:9|Input testin is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 796 to 647 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 645 to 643 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 641 to 639 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 606 to 511 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 508 to 502 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 500 to 370 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 349 to 342 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 337 to 232 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 221 to 191 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 189 to 187 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 150 to 148 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 127 to 120 of crami(796 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 115 to 10 of crami(796 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":64:8:64:11|Input sclk is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 139 to 94 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 92 to 89 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 56 to 51 of ahbsi(139 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bit 49 of ahbsi(139 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 47 to 41 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 17 to 14 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 12 to 0 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":57:4:57:7|Input port bits 0 to 18 of dbgi(0 to 58) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":52:4:52:7|Input hclk is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":54:4:54:8|Input ahbmi is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 117 to 98 of apbi(117 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bit 82 of apbi(117 downto 0) is unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bit 66 of apbi(117 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 15 to 14 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 12 to 0 of apbi(117 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":56:4:56:7|Input port bit 0 of irqi(0 to 6) is unused | ||||
| @W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramoen(4) to a constant 1 | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 4 of r.ramoen(4 downto 0) | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bwrite16) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bread16) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bwrite8) is always 0, optimizing ... | ||||
| @W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bread8) is always 0, optimizing ... | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 0 of r.bstate(0 to 7) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 1 of r.bstate(0 to 7) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 2 of r.bstate(0 to 7) | ||||
| @W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 3 of r.bstate(0 to 7) | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":79:4:79:7|Input port bits 137 to 41 of memi(137 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":79:4:79:7|Input port bits 38 to 34 of memi(137 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 139 to 103 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 99 to 94 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 92 to 89 of ahbsi(139 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bit 53 of ahbsi(139 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 14 to 0 of ahbsi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 117 to 79 of apbi(117 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bit 74 of apbi(117 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 68 to 63 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 48 to 23 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 14 to 0 of apbi(117 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":85:4:85:6|Input wpo is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":89:4:89:5|Trying to extract state machine for register state | ||||
| Extracted state machine for register state | ||||
| State machine has 5 reachable states with original encodings of: | ||||
| 00001 | ||||
| 00010 | ||||
| 00100 | ||||
| 01000 | ||||
| 10000 | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":39:6:39:16|Input port bits 347 to 165 of mem_ctrlr_o(347 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":39:6:39:16|Input port bits 159 to 129 of mem_ctrlr_o(347 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":39:6:39:16|Input port bits 127 to 32 of mem_ctrlr_o(347 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":39:6:39:16|Input port bits 19 to 0 of mem_ctrlr_o(347 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 5935 to 738 of msto(5935 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 705 to 482 of msto(5935 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 370 to 367 of msto(5935 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 334 to 111 of msto(5935 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 5503 to 2748 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2458 to 2443 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2407 to 2404 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2114 to 2099 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2063 to 2060 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1770 to 1755 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1719 to 1716 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1426 to 1411 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1375 to 1372 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1082 to 1067 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1031 to 1028 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 738 to 723 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 687 to 684 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 394 to 379 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 343 to 340 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 50 to 35 of slvo(5503 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":49:6:49:9|Input port bits 87 to 51 of ahbi(87 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":49:6:49:9|Input port bit 15 of ahbi(87 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":49:6:49:9|Input port bits 13 to 0 of ahbi(87 downto 0) are unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Trying to extract state machine for register r.txstate | ||||
| Extracted state machine for register r.txstate | ||||
| State machine has 3 reachable states with original encodings of: | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Trying to extract state machine for register r.rxstate | ||||
| Extracted state machine for register r.rxstate | ||||
| State machine has 4 reachable states with original encodings of: | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":48:4:48:5|Input port bits 2 to 1 of ui(2 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 117 to 68 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 48 to 21 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 15 to 9 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 7 to 0 of apbi(117 downto 0) are unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":147:8:147:9|Trying to extract state machine for register r.state | ||||
| Extracted state machine for register r.state | ||||
| State machine has 6 reachable states with original encodings of: | ||||
| 000001 | ||||
| 000010 | ||||
| 000100 | ||||
| 001000 | ||||
| 010000 | ||||
| 100000 | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":40:6:40:9|Input port bits 14 to 3 of dmao(46 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":40:6:40:9|Input port bit 0 of dmao(46 downto 0) is unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":42:6:42:10|Input port bit 4 of uarto(12 downto 0) is unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":42:6:42:10|Input port bit 1 of uarto(12 downto 0) is unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":43:6:43:9|Input ahbi is unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":222:8:222:9|Trying to extract state machine for register r.state | ||||
| Extracted state machine for register r.state | ||||
| State machine has 3 reachable states with original encodings of: | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 103 to 94 of ahbi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 92 to 89 of ahbi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 56 to 51 of ahbi(139 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bit 49 of ahbi(139 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 47 to 36 of ahbi(139 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bit 15 of ahbi(139 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 13 to 0 of ahbi(139 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 0 to 3 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 132 to 135 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 264 to 267 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 396 to 399 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 528 to 531 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 660 to 663 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 792 to 795 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 924 to 927 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1056 to 1059 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1188 to 1191 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1320 to 1323 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1452 to 1455 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1584 to 1587 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1716 to 1719 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1848 to 1851 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1980 to 1983 of apbo(0 to 2111) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 117 to 82 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 48 to 24 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 15 to 13 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 11 to 0 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":65:4:65:7|Input port bits 2 to 1 of gpti(2 downto 0) are unused | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Trying to extract state machine for register r.txstate | ||||
| Extracted state machine for register r.txstate | ||||
| State machine has 4 reachable states with original encodings of: | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| @N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Trying to extract state machine for register r.rxstate | ||||
| Extracted state machine for register r.rxstate | ||||
| State machine has 5 reachable states with original encodings of: | ||||
| 00001 | ||||
| 00010 | ||||
| 00100 | ||||
| 01000 | ||||
| 10000 | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 117 to 65 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bit 15 of apbi(117 downto 0) is unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 13 to 0 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 117 to 57 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 48 to 23 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 15 to 5 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 3 to 0 of apbi(117 downto 0) are unused | ||||
| @W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":65:4:65:8|Input port bits 95 to 7 of gpioi(95 downto 0) are unused | ||||
| @W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":73:4:73:8|Input urxd1 is unused | ||||
| @END | ||||
| Process took 0h:00m:37s realtime, 0h:00m:36s cputime | ||||
| # Thu Dec 19 12:48:58 2013 | ||||
| ###########################################################] | ||||
| Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 | ||||
| Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved | ||||
| Product Version E-2010.09A-1 | ||||
| @N: MF249 |Running in 32-bit mode. | ||||
| @N: MF258 |Gated clock conversion disabled | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Sequential instance MemCal.apbo\.prdata_e has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Sequential instance MemCal.apbo\.prdata_e_1 has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Sequential instance MemCal.apbo\.prdata_e_2 has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Sequential instance MemCal.apbo\.prdata_e_3 has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Sequential instance MemCal.apbo\.prdata[12] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Sequential instance MemCal.apbo\.prdata[13] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Sequential instance MemCal.apbo\.prdata[14] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Sequential instance MemCal.apbo\.prdata[15] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":226:16:226:17|Sequential instance MemCal.apbo\.prdata[2] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":226:16:226:17|Sequential instance MemCal.apbo\.prdata[3] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":226:16:226:17|Sequential instance MemCal.apbo\.prdata[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":226:16:226:17|Sequential instance MemCal.apbo\.prdata[18] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|tristate driver apbo\.prdata_tri[28] on net apbo\.prdata_tri[28] has its enable tied to GND (module APB_FIFOZ0) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|tristate driver apbo\.prdata_tri[30] on net apbo\.prdata_tri[30] has its enable tied to GND (module APB_FIFOZ0) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|tristate driver apbo\.prdata_tri[31] on net apbo\.prdata_tri[31] has its enable tied to GND (module APB_FIFOZ0) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|tristate driver apbo\.prdata_tri[29] on net apbo\.prdata_tri[29] has its enable tied to GND (module APB_FIFOZ0) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri31 on net gpioi_tri31 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri30 on net gpioi_tri30 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri29 on net gpioi_tri29 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri28 on net gpioi_tri28 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri27 on net gpioi_tri27 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri26 on net gpioi_tri26 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri25 on net gpioi_tri25 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri24 on net gpioi_tri24 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri23 on net gpioi_tri23 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri22 on net gpioi_tri22 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri21 on net gpioi_tri21 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri20 on net gpioi_tri20 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri19 on net gpioi_tri19 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri18 on net gpioi_tri18 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri17 on net gpioi_tri17 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri16 on net gpioi_tri16 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri15 on net gpioi_tri15 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri14 on net gpioi_tri14 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri13 on net gpioi_tri13 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri12 on net gpioi_tri12 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri11 on net gpioi_tri11 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri10 on net gpioi_tri10 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri9 on net gpioi_tri9 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri8 on net gpioi_tri8 has its enable tied to GND (module leon3mp) | ||||
| @W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\leon3mp.vhd":395:20:395:23|tristate driver gpioi_tri7 on net gpioi_tri7 has its enable tied to GND (module leon3mp) | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Sequential instance ua1.uart1.r\.extclk has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Sequential instance memctrlr.r\.bexcn has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Sequential instance memctrlr.r\.brdyn has been reduced to a combinational gate by constant propagation | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":2193:4:2193:19|Removing sequential instance actar_0.DFN1_Mult_0_inst of view:pa3l.DFN1(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\actar.vhd":469:4:469:11|Removing sequential instance actar_0.DFN1_117 of view:pa3l.DFN1(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.echeck of view:PrimLib.sdffr(prim) because there are no references to its outputs | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\apb_uart.vhd":101:12:101:13|Removing sequential instance COM0.Rdata[17], because it is equivalent to instance COM0.Rdata[13] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata_cl_8[31], because it is equivalent to instance MemCal.PRdata_cl_7[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata_cl_9[31], because it is equivalent to instance MemCal.PRdata_cl_6[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata_cl_6[31], because it is equivalent to instance MemCal.PRdata_cl_5[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata[31], because it is equivalent to instance MemCal.PRdata[30] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata[30], because it is equivalent to instance MemCal.PRdata[28] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata_cl_3[31], because it is equivalent to instance MemCal.PRdata_cl[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata[29], because it is equivalent to instance MemCal.PRdata[28] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata_cl_5[31], because it is equivalent to instance MemCal.PRdata_cl_4[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata_cl_1[31], because it is equivalent to instance MemCal.PRdata_cl_2[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata_e_13, because it is equivalent to instance MemCal.apbo.prdata_e_12 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata[31], because it is equivalent to instance MemCal.apbo.prdata[30] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata[30], because it is equivalent to instance MemCal.apbo.prdata[29] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata[29], because it is equivalent to instance MemCal.apbo.prdata[28] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata_e_11, because it is equivalent to instance MemCal.apbo.prdata_e_10 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata_e_9, because it is equivalent to instance MemCal.apbo.prdata_e_10 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata_e_8, because it is equivalent to instance MemCal.apbo.prdata_e_10 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata_e_6, because it is equivalent to instance MemCal.apbo.prdata_e_4 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata_e_7, because it is equivalent to instance MemCal.apbo.prdata_e_5 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata_cl_2[31], because it is equivalent to instance MemCal.PRdata_cl[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo.prdata_e_5, because it is equivalent to instance MemCal.apbo.prdata_e_4 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.15.loop_all_chanel.4.sample_in_buf[56], because it is equivalent to instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.16.loop_all_chanel.4.sample_in_buf[55] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.15.loop_all_chanel.3.sample_in_buf[74], because it is equivalent to instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.16.loop_all_chanel.3.sample_in_buf[73] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.15.loop_all_chanel.2.sample_in_buf[92], because it is equivalent to instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.16.loop_all_chanel.2.sample_in_buf[91] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.15.loop_all_chanel.1.sample_in_buf[110], because it is equivalent to instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.16.loop_all_chanel.1.sample_in_buf[109] | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance loop_all_sample\.15\.loop_all_chanel\.5\.sample_in_buf[38] of view:PrimLib.dffre(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance loop_all_sample\.15\.loop_all_chanel\.6\.sample_in_buf[20] of view:PrimLib.dffre(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance loop_all_sample\.15\.loop_all_chanel\.7\.sample_in_buf[2] of view:PrimLib.dffre(prim) because there are no references to its outputs | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.16.loop_all_chanel.0.sample_in_buf[127], because it is equivalent to instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.15.loop_all_chanel.0.sample_in_buf[128] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.16.loop_all_chanel.1.sample_in_buf[109], because it is equivalent to instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.17.loop_all_chanel.1.sample_in_buf[108] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.15.loop_all_chanel.0.sample_in_buf[128], because it is equivalent to instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.17.loop_all_chanel.0.sample_in_buf[126] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.16.loop_all_chanel.7.sample_in_buf[1], because it is equivalent to instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.17.loop_all_chanel.7.sample_in_buf[0] | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance loop_all_sample\.16\.loop_all_chanel\.2\.sample_in_buf[91] of view:PrimLib.dffre(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance loop_all_sample\.16\.loop_all_chanel\.3\.sample_in_buf[73] of view:PrimLib.dffre(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance loop_all_sample\.16\.loop_all_chanel\.4\.sample_in_buf[55] of view:PrimLib.dffre(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance loop_all_sample\.16\.loop_all_chanel\.5\.sample_in_buf[37] of view:PrimLib.dffre(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":200:10:200:11|Removing sequential instance loop_all_sample\.16\.loop_all_chanel\.6\.sample_in_buf[19] of view:PrimLib.dffre(prim) because there are no references to its outputs | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_11[31], because it is equivalent to instance MemOut.PRdata_cl_10[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_3[31], because it is equivalent to instance MemOut.PRdata_cl_2[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_9[31], because it is equivalent to instance MemOut.PRdata_cl_8[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_8[31], because it is equivalent to instance MemOut.PRdata_cl_6[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_7[31], because it is equivalent to instance MemOut.PRdata_cl_5[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_6[31], because it is equivalent to instance MemOut.PRdata_cl_4[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_4[31], because it is equivalent to instance MemOut.PRdata_cl_5[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_9, because it is equivalent to instance MemOut.apbo.prdata_e_8 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_8, because it is equivalent to instance MemOut.apbo.prdata_e_6 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_7, because it is equivalent to instance MemOut.apbo.prdata_e_5 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_6, because it is equivalent to instance MemOut.apbo.prdata_e_4 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_12, because it is equivalent to instance MemOut.apbo.prdata_e_10 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_3, because it is equivalent to instance MemOut.apbo.prdata_e | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_5, because it is equivalent to instance MemOut.apbo.prdata_e_4 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_1[31], because it is equivalent to instance MemOut.PRdata_cl[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_2[31], because it is equivalent to instance MemOut.PRdata_cl[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_13[31], because it is equivalent to instance MemOut.PRdata_cl_12[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":196:24:196:25|Removing sequential instance MemOut.PRdata_cl_12[31], because it is equivalent to instance MemOut.PRdata_cl_10[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_1, because it is equivalent to instance MemOut.apbo.prdata_e | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_2, because it is equivalent to instance MemOut.apbo.prdata_e | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_13, because it is equivalent to instance MemOut.apbo.prdata_e_11 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemOut.apbo.prdata_e_11, because it is equivalent to instance MemOut.apbo.prdata_e_10 | ||||
| Available hyper_sources - for debug and ip models | ||||
| None Found | ||||
| Finished RTL optimizations (Time elapsed 0h:00m:07s; Memory used current: 91MB peak: 100MB) | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF176 |Default generator successful | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[0] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[1] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[2] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[3] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[4] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[5] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[6] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[7] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[8] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[9] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[10] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[11] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[15] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[18] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[19] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[20] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[21] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[22] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[23] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[25] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[26] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[27] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[28] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[29] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[30] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[31] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Sequential instance memctrlr.r.hresp[1] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\apb_uart.vhd":142:20:142:21|Sequential instance COM0.apbo.prdata[12] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit memctrlr.r\.hburst[2] is always 0, optimizing ... | ||||
| @W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit memctrlr.r\.hburst[1] is always 0, optimizing ... | ||||
| @N: BN115 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Removing instance memctrlr.un1_v\.ws_1_sqmuxa_2_0 of view:VhdlGenLib.ADD__const_cin_w4_0(verilog) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r\.hmasterlockd of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":209:18:209:55|Removing sequential instance MemCal.apbo\.prdata[28] of view:PrimLib.lat(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\apb_fifo.vhd":194:12:194:13|Removing sequential instance MemCal.PRdata[28] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[0] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[18] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[19] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[20] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[21] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[22] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[23] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[25] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[27] has been reduced to a combinational gate by constant propagation | ||||
| @N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":68:28:68:36|Found 28 bit decrementor, 'Downsampling_f3.un3_counter[5:32]' | ||||
| @N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":68:28:68:36|Found 28 bit decrementor, 'Downsampling_f2.un3_counter[5:32]' | ||||
| @N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":68:28:68:36|Found 28 bit decrementor, 'Downsampling_f1.un2_counter[5:32]' | ||||
| @N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":68:28:68:36|Found 28 bit decrementor, 'Downsampling_f0.un2_counter[5:32]' | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[18] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[19] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[36] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[37] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[38] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[39] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[40] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[41] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[42] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[43] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[44] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[45] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[46] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[47] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[48] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[49] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[50] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[51] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[52] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[53] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[54] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[55] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[56] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[57] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[58] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[59] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[60] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[61] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[62] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[63] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[64] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[65] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[66] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[67] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[68] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[69] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[70] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[71] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[72] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[73] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[74] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[75] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[76] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[77] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[78] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[79] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[80] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[81] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[82] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[83] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[84] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[85] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[86] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[87] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[88] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[89] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[90] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[91] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[108] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[109] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[126] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f2.sample_out[127] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[18] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[19] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[36] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[37] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[38] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[39] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[40] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[41] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[42] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[43] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[44] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[45] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[46] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[47] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[48] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[49] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[50] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[51] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[52] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[53] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[54] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[55] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[56] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[57] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[58] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[59] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[60] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[61] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[62] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[63] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[64] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[65] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[66] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[67] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[68] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[69] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[70] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[71] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[72] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[73] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[74] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[75] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[76] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[77] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[78] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[79] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[80] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[81] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[82] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[83] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[84] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[85] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[86] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[87] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[88] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[89] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[90] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[91] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[108] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[109] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[126] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f3.sample_out[127] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[18] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[19] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[36] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[37] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[38] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[39] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[40] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[41] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[42] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[43] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[44] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[45] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[46] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[47] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[48] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[49] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[50] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[51] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[52] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[53] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[54] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[55] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[56] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[57] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[58] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[59] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[60] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[61] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[62] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[63] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[64] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[65] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[66] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[67] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[68] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[69] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[70] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[71] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[72] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[73] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[74] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[75] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[76] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[77] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[78] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[79] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[80] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[81] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[82] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[83] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[84] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[85] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[86] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[87] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[88] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[89] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[90] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[91] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[108] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[109] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[126] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f0.sample_out[127] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[18] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[19] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[36] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[37] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[38] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[39] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[40] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[41] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[42] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[43] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[44] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[45] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[46] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[47] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[48] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[49] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[50] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[51] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[52] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[53] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[54] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[55] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[56] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[57] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[58] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[59] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[60] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[61] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[62] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[63] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[64] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[65] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[66] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[67] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[68] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[69] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[70] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[71] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[72] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[73] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[74] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[75] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[76] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[77] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[78] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[79] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[80] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[81] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[82] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[83] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[84] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[85] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[86] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[87] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[88] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[89] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[90] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[91] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[108] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[109] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[126] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance Downsampling_f1.sample_out[127] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_ad_conv\ad7688_drvr.vhd":153:4:153:5|Found counter in view:lpp.AD7688_drvr(ar_ad7688_drvr) inst sample_bit_counter[5:0] | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_ad_conv\ad7688_drvr.vhd":83:4:83:5|Found counter in view:lpp.AD7688_drvr(ar_ad7688_drvr) inst cnv_cycle_counter[8:0] | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[17:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF176 |Default generator successful | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2_control.vhd":81:4:81:5|Found counter in view:lpp.IIR_CEL_CTRLR_v2_CONTROL(ar_iir_cel_ctrlr_v2_control) inst Chanel_ongoing[31:0] | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2_control.vhd":81:4:81:5|Found counter in view:lpp.IIR_CEL_CTRLR_v2_CONTROL(ar_iir_cel_ctrlr_v2_control) inst alu_selected_coeff[4:0] | ||||
| Encoding state machine lpp.IIR_CEL_CTRLR_v2_CONTROL(ar_iir_cel_ctrlr_v2_control)-IIR_CEL_STATE[0:9] | ||||
| original code -> new code | ||||
| 0000000001 -> 0000000001 | ||||
| 0000000010 -> 0000000010 | ||||
| 0000000100 -> 0000000100 | ||||
| 0000001000 -> 0000001000 | ||||
| 0000010000 -> 0000010000 | ||||
| 0000100000 -> 0000100000 | ||||
| 0001000000 -> 0001000000 | ||||
| 0010000000 -> 0010000000 | ||||
| 0100000000 -> 0100000000 | ||||
| 1000000000 -> 1000000000 | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 9 bit incrementor, 'un2_raddr_vect_s[8:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 9 bit incrementor, 'un2_waddr_vect_s[8:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 9 bit incrementor, 'un2_raddr_vect_s[8:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 9 bit incrementor, 'un2_waddr_vect_s[8:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 9 bit incrementor, 'un2_raddr_vect_s[8:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 9 bit incrementor, 'un2_waddr_vect_s[8:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 9 bit incrementor, 'un2_raddr_vect_s[8:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 9 bit incrementor, 'un2_waddr_vect_s[8:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 9 bit incrementor, 'un2_raddr_vect_s[8:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 9 bit incrementor, 'un2_waddr_vect_s[8:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_demux\demux.vhd":102:37:102:39|Found 32 bit incrementor, 'i_1[1:32]' | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\driver_fft.vhd":59:8:59:9|Found counter in view:lpp.Driver_FFT(ar_driver) inst DataCount[7:0] | ||||
| Encoding state machine lpp.Driver_FFT(ar_driver)-ect[0:3] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 01 -> 01 | ||||
| 10 -> 10 | ||||
| 11 -> 11 | ||||
| @N: MO106 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\twiddle.vhd":37:4:37:7|Found ROM, 'lut_0.t_int1[30:0]', 128 words by 31 bits | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_8_139(translated) inst Q_out[7:0] | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_3_7(translated) inst Q_out[2:0] | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_7_127(translated) inst Q_out[6:0] | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_8_255_ldCount(translated) inst Q_out[7:0] | ||||
| @N: MF176 |Default generator successful | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":82:4:82:5|Found counter in view:lpp.bcounter(translated) inst Q_out[9:0] | ||||
| @N: MF176 |Default generator successful | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_8_255_outBuf_rA_0(translated) inst Q_out[7:0] | ||||
| @N: MF184 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":277:44:277:54|Found 16 by 16 bit subtractor, 'outQ_xhdl2_1_0[15:0]' | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF184 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":278:39:278:49|Found 16 by 16 bit subtractor, 'outQ_xhdl2_2_0_0[15:0]' | ||||
| @N: MF184 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":272:10:272:24|Found 16 by 16 bit subtractor, 'Hi_w_0_0[15:0]' | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":104:24:104:47|Found 17 bit incrementor, 'un5_int_outp[16:0]' | ||||
| Encoding state machine lpp.Linker_FFT(ar_linker)-ect[0:1] | ||||
| original code -> new code | ||||
| 01 -> 0 | ||||
| 10 -> 1 | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| Ram Decomposition Statistics for memRAM\.SRAM.inf\.x0.rfd[15:0] | ||||
| RAM 512x9 : 0 | ||||
| RAM 512x9 : 0 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| Encoding state machine lpp.TopSpecMatrix(ar_topspecmatrix)-ect[0:2] | ||||
| original code -> new code | ||||
| 01 -> 00 | ||||
| 10 -> 01 | ||||
| 11 -> 10 | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF176 |Default generator successful | ||||
| Encoding state machine lpp.DriveInputs(ar_driveinputs)-ect[0:6] | ||||
| original code -> new code | ||||
| 0000001 -> 0000001 | ||||
| 0000010 -> 0000010 | ||||
| 0000100 -> 0000100 | ||||
| 0001000 -> 0001000 | ||||
| 0010000 -> 0010000 | ||||
| 0100000 -> 0100000 | ||||
| 1000000 -> 1000000 | ||||
| @N: MF176 |Default generator successful | ||||
| Encoding state machine lpp.ALU_Driver(ar_alu_driver)-st[0:7] | ||||
| original code -> new code | ||||
| 0000000001 -> 00000001 | ||||
| 0000000010 -> 00000010 | ||||
| 0000000100 -> 00000100 | ||||
| 0000001000 -> 00001000 | ||||
| 0000010000 -> 00010000 | ||||
| 0000100000 -> 00100000 | ||||
| 0001000000 -> 01000000 | ||||
| 0010000000 -> 10000000 | ||||
| Encoding state machine lpp.ALU_Driver(ar_alu_driver)-ect[0:9] | ||||
| original code -> new code | ||||
| 0000000001 -> 0000000001 | ||||
| 0000000010 -> 0000000010 | ||||
| 0000000100 -> 0000000100 | ||||
| 0000001000 -> 0000001000 | ||||
| 0000010000 -> 0000010000 | ||||
| 0000100000 -> 0000100000 | ||||
| 0001000000 -> 0001000000 | ||||
| 0010000000 -> 0010000000 | ||||
| 0100000000 -> 0100000000 | ||||
| 1000000000 -> 1000000000 | ||||
| @W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_matrix\alu_driver.vhd":72:8:72:9|Register bit CTRL[1] is always 0, optimizing ... | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\twocomplementer.vhd":52:40:52:49|Found 16 bit incrementor, 'rescomp_1[15:0]' | ||||
| Encoding state machine lpp.GetResult(ar_getresult)-ect[0:3] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 01 -> 01 | ||||
| 10 -> 10 | ||||
| 11 -> 11 | ||||
| Encoding state machine lpp.Dispatch(ar_dispatch)-ect[0:1] | ||||
| original code -> new code | ||||
| 01 -> 0 | ||||
| 10 -> 1 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":103:35:103:57|Found 8 bit incrementor, 'un2_raddr_vect_s[7:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\lpp_fifo.vhd":131:35:131:57|Found 8 bit incrementor, 'un2_waddr_vect_s[7:0]' | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_cna\apb_dac.vhd":141:16:141:17|Sequential instance CAL0.apbo.prdata[1] has been reduced to a combinational gate by constant propagation | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\clock_divider.vhd":53:28:53:37|Found 8 bit incrementor, 'un10_countint[25:32]' | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_cna\clksetting.vhd":47:8:47:9|Found counter in view:lpp.ClkSetting(ar_clksetting) inst clockint[6:0] | ||||
| Encoding state machine lpp.Gene_SYNC(ar_gene_sync)-ect[0:3] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 01 -> 01 | ||||
| 10 -> 10 | ||||
| 11 -> 11 | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_cna\serialize.vhd":96:8:96:9|Found counter in view:lpp.Serialize(ar_serialize) inst N[4:0] | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\baudgen.vhd":58:4:58:5|Found counter in view:lpp.BaudGen(ar_baudgen) inst cpt[11:0] | ||||
| @W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Register bit REG[9] is always 1, optimizing ... | ||||
| @W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Register bit Q_1[9] is always 1, optimizing ... | ||||
| Encoding state machine gaisler.iu3(rtl)-r\.x\.rstate[0:3] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 01 -> 01 | ||||
| 10 -> 10 | ||||
| 11 -> 11 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un6_fe_npc_2[29:0]' | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un6_fe_npc_0[29:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un6_fe_npc_1[29:0]' | ||||
| @N: MF176 |Default generator successful | ||||
| @N: MF179 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":392:9:392:30|Found 4 bit by 4 bit '<' comparator, 'comb\.irq_trap\.op_gt\.un2_irl' | ||||
| Encoding state machine gaisler.mmu_icache(rtl)-r\.istate[0:2] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 10 -> 01 | ||||
| 11 -> 10 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 8 bit incrementor, 'un1_r\.faddr[1:8]' | ||||
| Encoding state machine gaisler.mmu_dcache(rtl)-r\.dstate[0:5] | ||||
| original code -> new code | ||||
| 000000001 -> 000001 | ||||
| 000000010 -> 000010 | ||||
| 000001000 -> 000100 | ||||
| 001000000 -> 001000 | ||||
| 010000000 -> 010000 | ||||
| 100000000 -> 100000 | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 8 bit incrementor, 'un1_r\.faddr[1:8]' | ||||
| Encoding state machine gaisler.mmu_acache(rtl)-r\.bo[0:3] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 01 -> 01 | ||||
| 10 -> 10 | ||||
| 11 -> 11 | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Found counter in view:gaisler.dsu3x(rtl) inst r\.cnt[2:0] | ||||
| @N: MF176 |Default generator successful | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Sequential instance l3.dsugen.dsu0.x0.r.dsuen[0] has been reduced to a combinational gate by constant propagation | ||||
| Encoding state machine lpp.ssram_plugin(ar_ssram_plugin)-state[0:4] | ||||
| original code -> new code | ||||
| 00001 -> 00001 | ||||
| 00010 -> 00010 | ||||
| 00100 -> 00100 | ||||
| 01000 -> 01000 | ||||
| 10000 -> 10000 | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_memory\ssram_plugin.vhd":101:8:101:18|Removing sequential instance state[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| Encoding state machine gaisler.dcom_uart(rtl)-r\.txstate[0:2] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 01 -> 01 | ||||
| 10 -> 10 | ||||
| Encoding state machine gaisler.dcom_uart(rtl)-r\.rxstate[0:3] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 01 -> 01 | ||||
| 10 -> 10 | ||||
| 11 -> 11 | ||||
| @N: MF179 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":392:9:392:30|Found 14 bit by 14 bit '<' comparator, 'uartop\.op_gt\.v\.brate2' | ||||
| Encoding state machine gaisler.dcom(struct)-r\.state[0:5] | ||||
| original code -> new code | ||||
| 000001 -> 000001 | ||||
| 000010 -> 000010 | ||||
| 000100 -> 000100 | ||||
| 001000 -> 001000 | ||||
| 010000 -> 010000 | ||||
| 100000 -> 100000 | ||||
| @N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 6 bit decrementor, 'un5_newlen[5:0]' | ||||
| @N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un5_newaddr[29:0]' | ||||
| Encoding state machine grlib.apbctrl(rtl)-r\.state[0:2] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 01 -> 01 | ||||
| 10 -> 10 | ||||
| @N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 9 bit decrementor, 'un6_scaler[8:0]' | ||||
| @N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 32 bit decrementor, 'un12_res[31:0]' | ||||
| @N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Found counter in view:gaisler.apbuart(rtl) inst r\.irqcnt[5:0] | ||||
| Encoding state machine gaisler.apbuart(rtl)-r\.txstate[0:3] | ||||
| original code -> new code | ||||
| 00 -> 00 | ||||
| 01 -> 01 | ||||
| 10 -> 10 | ||||
| 11 -> 11 | ||||
| Encoding state machine gaisler.apbuart(rtl)-r\.rxstate[0:4] | ||||
| original code -> new code | ||||
| 00001 -> 00001 | ||||
| 00010 -> 00010 | ||||
| 00100 -> 00100 | ||||
| 01000 -> 01000 | ||||
| 10000 -> 10000 | ||||
| @N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 12 bit decrementor, 'un4_scaler[11:0]' | ||||
| @W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Sequential instance ua1.uart1.r.ctsn[0] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[7] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[8] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[7] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[8] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[7] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[8] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[7] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[8] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[7] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance memRAM.SRAM.inf.x0.rfd_tile_0.DIN_REG1[8] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Sequential instance ALU0.arith.MACinst.MACMUXselREG.Q[0] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Sequential instance ALU0.arith.MACinst.MACMUX2selREG.Q[0] has been reduced to a combinational gate by constant propagation | ||||
| @W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac.vhd":129:4:129:5|Sequential instance ALU0.arith.MACinst.load_mult_result_D has been reduced to a combinational gate by constant propagation | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PrT1_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PrT1_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PiT1_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PiT1_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PiT2_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PiT2_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PrT2_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PrT2_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PiT3_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PiT3_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PiT4_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PiT4_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PrT3_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PrT3_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PrT4_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PrT4_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PiT5_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PiT5_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PiT6_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PiT6_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PrT5_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PrT5_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.PrT6_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.PrT6_r[14] | ||||
| Auto Dissolve of gen_comp\.TWO_COMPLEMENTER1 (inst of view:lpp.TwoComplementer_gen_comp\.TWO_COMPLEMENTER1(ar_twocomplementer)) | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[31] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[30] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[29] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[28] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[27] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[26] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[25] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[24] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[23] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[22] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[21] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[20] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[19] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[18] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[17] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[16] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[15] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[14] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[13] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[12] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[11] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[10] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[9] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[8] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[7] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[6] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[5] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance MULToutREG.Q[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| Auto Dissolve of SM (inst of view:lpp.SpectralMatrix(ar_spectralmatrix)) | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.iosn[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.iosn[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[31] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[30] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[29] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[28] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[27] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[26] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[25] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[24] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[23] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[22] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[21] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[20] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[19] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[18] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[17] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[16] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[15] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[14] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[13] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[12] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[11] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[10] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[9] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[8] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[7] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[6] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[5] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[4] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[3] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[2] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.romsn[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.romsn[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramsn[3] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Boundary register memctrlr.r\.ramsn[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramsn[2] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Boundary register memctrlr.r\.ramsn[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramsn[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Boundary register memctrlr.r\.ramsn[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramoen[3] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramoen[2] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramoen[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramoen[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.mben[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.mben[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.mben[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.mben[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\apb_uart.vhd":142:20:142:21|Removing sequential instance COM0.apbo.prdata[17], because it is equivalent to instance COM0.apbo.prdata[13] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[6], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[7], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[8], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[9], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[11], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[10], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[3], because it is equivalent to instance ahb0.r.hrdatas[2] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatam[24], because it is equivalent to instance ahb0.r.hrdatam[13] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatam[13], because it is equivalent to instance ahb0.r.hrdatam[12] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[17], because it is equivalent to instance ahb0.r.hrdatas[16] | ||||
| Auto Dissolve of l3\.cpu\.0\.u0 (inst of view:gaisler.leon3s(rtl)) | ||||
| Auto Dissolve of SM0 (inst of view:lpp.MatriceSpectrale(ar_matricespectrale)) | ||||
| Finished factoring (Time elapsed 0h:00m:35s; Memory used current: 171MB peak: 171MB) | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Removing sequential instance ua1\.uart1.r\.rtsn of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\misc\gptimer.vhd":282:8:282:9|Removing sequential instance gpt\.timer0.r\.wdog of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\misc\gptimer.vhd":282:8:282:9|Removing sequential instance gpt\.timer0.r\.wdogn of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\apbctrl.vhd":222:8:222:9|Removing sequential instance apb0.r\.haddr[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\grlib\amba\apbctrl.vhd":222:8:222:9|Removing sequential instance apb0.r\.haddr[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":166:10:166:11|Removing sequential instance dcomgen\.dcom0.ahbmst0.r\.start of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":316:8:316:9|Removing sequential instance irqctrl\.irqctrl0.r\.cpurst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":316:8:316:9|Boundary register irqctrl\.irqctrl0.r\.cpurst[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Removing sequential instance l3\.dsugen\.dsu0.x0.r\.pwd[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[31] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[30] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[29] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[28] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[27] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[26] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[25] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[24] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[23] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[22] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[21] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[20] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[19] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[18] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[17] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[14] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[9] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[8] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.asi[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.asi[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.diag_op of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dlock of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.su of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.icache0.r\.su of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[31] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[30] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[29] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[28] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[27] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[26] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[25] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[24] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[23] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[22] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[21] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[20] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[19] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[18] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[17] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[14] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[9] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[8] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.dci\.asi[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.dci\.asi[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.dci\.asi[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[18] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[17] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[14] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[9] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[8] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.cnt[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.cnt[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[18] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[17] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[14] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[9] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[8] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.su of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[8] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[8] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[7] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[6] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[5] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[4] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[3] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[2] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[1] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[0] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.RX_REG.Q_1[9] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.RX_REG.Q_1[9] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.RX_REG.Q_1[0] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.RX_REG.Q_1[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.RX_REG.SOUT of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.RX_REG.SOUT has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.RX_REG.REG[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
| @A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.RX_REG.REG[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[15] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[14] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[13] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[12] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[11] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[10] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[9] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[8] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[7] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[6] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[5] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP2REG.Q[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[15] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[14] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[13] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[12] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[11] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[10] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[9] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[8] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[7] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[6] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[5] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance SM0.SM.CALC0.ALU0.arith\.MACinst.OP1REG.Q[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT0.FFT0.postBflySw_0.validOut_xhdl3 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT0.FFT0.postBflySw_0.pipe1 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.pipe6[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.pipe4[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.pipe2[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.pipe5[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.pipe3[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.pipe1[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.validOut_xhdl3 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT0.FFT0.preBflySw_0.outP_xhdl1[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT0.FFT0.preBflySw_0.outP_xhdl1[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT0.FFT0.preBflySw_0.rightP_r[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT0.FFT0.preBflySw_0.rightP_r[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT0.FFT0.preBflySw_0.validOut_xhdl3 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT0.FFT0.preBflySw_0.pipe1 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftsm.vhd":338:4:338:5|Removing sequential instance FFT0.FFT0.smTop_0.inBuf_wA_0.fftDone_int of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftsm.vhd":338:4:338:5|Removing sequential instance FFT0.FFT0.smTop_0.inBuf_wA_0.swCross_int of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Removing sequential instance FFT0.FFT0.smTop_0.wrFFTtimer_0.stage_timer.tc_out of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftsm.vhd":112:4:112:5|Removing sequential instance FFT0.FFT0.smTop_0.rdFFTtimer_0.preRdValid of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftsm.vhd":136:4:136:5|Removing sequential instance FFT0.FFT0.smTop_0.rdFFTtimer_0.pipe2 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftsm.vhd":136:4:136:5|Removing sequential instance FFT0.FFT0.smTop_0.rdFFTtimer_0.rdValid_xhdl5 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftsm.vhd":136:4:136:5|Removing sequential instance FFT0.FFT0.smTop_0.rdFFTtimer_0.pipe1 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[5] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[6] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[7] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[8] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[9] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[10] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[11] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[12] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[13] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[14] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[15] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[16] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[17] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[20] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[21] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[22] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[23] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[24] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[25] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[26] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[27] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[28] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[29] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[30] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[31] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[32] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[33] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[34] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[35] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[92] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[93] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[94] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[95] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[96] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[97] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[98] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[99] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[100] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[101] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[102] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[103] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[104] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[105] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[106] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[107] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[110] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[111] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[112] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[113] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[114] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[115] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[116] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[117] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[118] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[119] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[120] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[121] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[122] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[123] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[124] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[125] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[128] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[129] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[130] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[131] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[132] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[133] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[134] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[135] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[136] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[137] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[138] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[139] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[140] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[141] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[142] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out[143] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[27] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[26] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[25] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[24] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[23] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[22] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[21] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[20] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[19] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[18] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[17] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[16] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[15] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[14] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[13] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[12] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[11] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[10] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[9] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[8] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[7] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[6] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[5] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.counter[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_downsampling\downsampling.vhd":53:4:53:5|Removing sequential instance ACQ0.Downsampling_f2.sample_out_val of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":233:8:233:9|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_HIGH\.17\.sample_out_s2[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":233:8:233:9|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_HIGH\.16\.sample_out_s2[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.7\.all_bit\.17\.sample_out_s2[18] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.7\.all_bit\.16\.sample_out_s2[19] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.6\.all_bit\.17\.sample_out_s2[36] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.6\.all_bit\.16\.sample_out_s2[37] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.5\.all_bit\.17\.sample_out_s2[54] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.5\.all_bit\.16\.sample_out_s2[55] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.4\.all_bit\.17\.sample_out_s2[72] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.4\.all_bit\.16\.sample_out_s2[73] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.3\.all_bit\.17\.sample_out_s2[90] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.3\.all_bit\.16\.sample_out_s2[91] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.2\.all_bit\.17\.sample_out_s2[108] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.2\.all_bit\.16\.sample_out_s2[109] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.1\.all_bit\.17\.sample_out_s2[126] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2.vhd":248:12:248:13|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.chanel_more\.all_chanel\.1\.all_bit\.16\.sample_out_s2[127] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\iir_filter\iir_cel_ctrlr_v2_control.vhd":81:4:81:5|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.ram_read of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.MULToutREG.Q[26] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.MULToutREG.Q[25] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.MULToutREG.Q[6] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.MULToutREG.Q[5] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.MULToutREG.Q[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.MULToutREG.Q[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.MULToutREG.Q[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.MULToutREG.Q[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac_reg.vhd":42:0:42:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.MULToutREG.Q[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\adder.vhd":59:4:59:5|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.adder_inst.REG[26] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\adder.vhd":59:4:59:5|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.adder_inst.REG[25] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\multiplier.vhd":58:0:58:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.Multiplieri_nst.REG[26] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\multiplier.vhd":58:0:58:1|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith\.MACinst.Multiplieri_nst.REG[25] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd":127:4:127:5|Removing sequential instance FFT0.FFT0.smTop_0.outBufA_0.fedge_0.in_t1, because it is equivalent to instance FFT0.FFT0.outBuff_0.wEn_r | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[0], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[0] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[1], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[1] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[2], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[2] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[3], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[3] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[4], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[5], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[5] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[6], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[6] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[7], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[7] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[8], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[8] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[9], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[9] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[10], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[10] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[11], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[11] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[12], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[12] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[13], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[13] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[14], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.a_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QrTi.a_r[15] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[0], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[0] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[1], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[1] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[2], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[2] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[3], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[3] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[4], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[5], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[5] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[6], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[6] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[7], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[7] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[8], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[8] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[9], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[9] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[10], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[10] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[11], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[11] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[12], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[12] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[13], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[13] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[14], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QiTr.a_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.a_r[15] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[0], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[0] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[1], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[1] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[2], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[2] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[3], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[3] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[4], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[5], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[5] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[6], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[6] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[7], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[7] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[8], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[8] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[9], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[9] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[10], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[10] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[11], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[11] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[12], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[12] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[13], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[13] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[14], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTr.t_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTr.t_r[15] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[0], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[0] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[1], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[1] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[2], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[2] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[3], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[3] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[4], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[5], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[5] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[6], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[6] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[7], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[7] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[8], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[8] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[9], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[9] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[10], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[10] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[11], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[11] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[12], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[12] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[13], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[13] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[14], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT0.FFT0.bfly_0.am3QrTi.t_r[15], because it is equivalent to instance FFT0.FFT0.bfly_0.am3QiTi.t_r[15] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\general_purpose\mac.vhd":129:4:129:5|Removing sequential instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.load_mult_result_D, because it is equivalent to instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.MACMUX2selREG.Q[0] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Removing sequential instance dcomgen.dcom0.dcom_uart0.r.rxf[0], because it is equivalent to instance ua1.uart1.r.rxf[0] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[0], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[0] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[1], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[1] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[2], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[2] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[3], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[3] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[4], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[5], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[5] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[6], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[6] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[0], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[0] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[1], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[1] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[2], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[2] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[3], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[3] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[4], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[5], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[5] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[6], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[6] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[0], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[0] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[1], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[1] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[2], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[2] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[3], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[3] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[4], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[4] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[5], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[5] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[6], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[6] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[7], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[7] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[8], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[8] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[9], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[9] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[10], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[10] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[11], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[11] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[12], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[12] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[13], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[13] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[14], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[14] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[15], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[15] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[16], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[16] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[17], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[17] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[18], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[18] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[19], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[19] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[20], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[20] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[21], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[21] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[22], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[22] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[23], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[23] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[24], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[24] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[25], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[25] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[26], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[26] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[27], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[27] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[28], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[28] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[29], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[29] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[30], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[30] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[31], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[31] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.renable, because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfe2 | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.write, because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.write | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Removing sequential instance ua1.uart1.r.rxf[1], because it is equivalent to instance dcomgen.dcom0.dcom_uart0.r.rxf[1] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\driver_fft.vhd":59:8:59:9|Removing sequential instance FFT0.DRIVE.sLoad, because it is equivalent to instance DMUX0.load_reg | ||||
| Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:36s; Memory used current: 175MB peak: 182MB) | ||||
| Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:51s; Memory used current: 168MB peak: 189MB) | ||||
| Starting Early Timing Optimization (Time elapsed 0h:00m:54s; Memory used current: 173MB peak: 189MB) | ||||
| Finished Early Timing Optimization (Time elapsed 0h:02m:07s; Memory used current: 162MB peak: 189MB) | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.outQ_xhdl2[16], because it is equivalent to instance FFT0.FFT0.bfly_0.outP_xhdl1[16] | ||||
| @W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3pe3kl-sheldon\..\..\lib\..\..\vhd_lib\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT0.FFT0.bfly_0.outQ_xhdl2[0], because it is equivalent to instance FFT0.FFT0.bfly_0.outP_xhdl1[0] | ||||
| Finished generic timing optimizations - Pass 2 (Time elapsed 0h:02m:09s; Memory used current: 158MB peak: 189MB) | ||||
| Finished preparing to map (Time elapsed 0h:02m:31s; Memory used current: 242MB peak: 244MB) | ||||
| High Fanout Net Report | ||||
| ********************** | ||||
| Driver Instance / Pin Name Fanout, notes | ||||
| ----------------------------------------------------------------------------------------------------------------------------------------------- | ||||
| rst0.rstoutl / Q 2088 : 1815 asynchronous set/reset | ||||
| ahb0.r.hmaster[0] / Q 45 | ||||
| dcomgen.dcom0.dcom_uart0.uartop.tmp / Y 59 | ||||
| apb0.r.haddr[2] / Q 93 | ||||
| apb0.r.haddr[3] / Q 41 | ||||
| apb0.r.haddr[4] / Q 52 | ||||
| apb0.r.pwdata[1] / Q 31 | ||||
| apb0.r.pwdata[2] / Q 28 | ||||
| apb0.r.pwdata[3] / Q 29 | ||||
| apb0.r.pwdata[4] / Q 31 | ||||
| apb0.r.pwdata[5] / Q 29 | ||||
| apb0.r.pwdata[6] / Q 27 | ||||
| ahb0.r.hslave[0] / Q 38 | ||||
| ahb0.r.hmasterd[0] / Q 32 | ||||
| COM0.Send / Q 29 : 13 asynchronous set/reset | ||||
| ahb0.comb.hready_1_iv / Y 47 | ||||
| COM0.COM0.Take / Q 36 : 20 asynchronous set/reset | ||||
| COM0.COM0.RX_REG.Serialized_int / Q 25 | ||||
| memctrlr.v.writedata_0_sqmuxa_i / Y 32 | ||||
| MemCal.prdata13_1_0_a2_0_a3 / Y 36 | ||||
| l3.cpu.0.u0.rst / Q 164 | ||||
| l3.cpu.0.u0.p0.holdn / Y 809 | ||||
| l3.cpu.0.u0.p0.c0mmu.icache0.r.flush2 / Q 34 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.r.flush / Q 37 | ||||
| l3.cpu.0.u0.p0.iu0.r.d.inst_0[12] / Q 27 | ||||
| l3.cpu.0.u0.p0.iu0.r.d.inst_0[21] / Q 36 | ||||
| l3.cpu.0.u0.p0.iu0.r.d.inst_0[22] / Q 25 | ||||
| SM0.SM.RES0.un1_Received_0_sqmuxa_0_a2_0 / Y 33 | ||||
| SM0.SM.Conjugate_int_0 / Y 25 | ||||
| SM0.SM.RaZ_i_s / Y 181 : 180 asynchronous set/reset | ||||
| MemCal.PRdata_cl_24_i_0_a3[31] / Y 26 | ||||
| gpt.timer0.r.tsel[0] / Q 37 | ||||
| gpt.timer0.comb.1.readdata_9_sn_m3 / Y 32 | ||||
| gpt.timer0.v.timers_2.value_0_sqmuxa / Y 33 | ||||
| gpt.timer0.readdata_1_sqmuxa_1 / Y 33 | ||||
| apb0.comb.v.prdata_1_0_0_a2_2[31] / Y 27 | ||||
| apb0.comb.v.prdata_1_0_0_a2_3[31] / Y 27 | ||||
| dcomgen.dcom0.dcom0.r.state[4] / Q 38 | ||||
| dcomgen.dcom0.dcom0.r.state[3] / Q 36 | ||||
| dcomgen.dcom0.dcom0.un1_v.data_0_sqmuxa_0_0 / Y 32 | ||||
| l3.dsugen.dsu0.x0.un1_v.cnt3_2_1 / Y 32 | ||||
| l3.dsugen.dsu0.x0.comb.v.slv.hready33_0_o3 / Y 33 | ||||
| l3.dsugen.dsu0.x0.v.slv.hwrite_0_sqmuxa_i_0_o2 / Y 30 | ||||
| l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp / Y 32 | ||||
| l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.r.m.dci.asi[3] / Q 27 | ||||
| l3.cpu.0.u0.p0.iu0.r.m.dci.asi[4] / Q 25 | ||||
| l3.cpu.0.u0.p0.iu0.r.m.dci.dsuen / Q 25 | ||||
| l3.cpu.0.u0.p0.c0mmu.icache0.r.istate_tr3_1 / Y 38 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.read_1 / Y 40 | ||||
| l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[0] / Y 39 | ||||
| l3.cpu.0.u0.p0.c0mmu.a0.r.bo_s2_0_a2 / Y 33 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate[4] / Q 73 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.v.hit2 / Y 39 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.read_0_sqmuxa / Y 38 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.mexc_0_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.read_0_sqmuxa_1 / Y 36 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.wb.data2_0_sqmuxa / Y 69 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_5_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_1_sqmuxa_1 / Y 32 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s0 / Y 32 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s1 / Y 32 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_tr0_0_0_a3 / Y 38 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_i[5] / Q 43 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.data1_0_sqmuxa_i_o2 / Y 33 | ||||
| l3.cpu.0.u0.p0.c0mmu.icache0.diagen_0_sqmuxa / Y 40 | ||||
| l3.cpu.0.u0.p0.c0mmu.icache0.r.istate[0] / Q 46 | ||||
| l3.cpu.0.u0.p0.c0mmu.icache0.v.vaddress_0_sqmuxa_0_a2 / Y 60 | ||||
| l3.cpu.0.u0.p0.iu0.r.x.npc[0] / Q 35 | ||||
| l3.cpu.0.u0.p0.iu0.r.x.npc[1] / Q 65 | ||||
| l3.cpu.0.u0.p0.iu0.r.a.rsel1[0] / Q 33 | ||||
| l3.cpu.0.u0.p0.iu0.r.a.rsel1[1] / Q 65 | ||||
| l3.cpu.0.u0.p0.iu0.r.a.rsel1[2] / Q 97 | ||||
| l3.cpu.0.u0.p0.iu0.r.e.aluop[0] / Q 39 | ||||
| l3.cpu.0.u0.p0.iu0.r.e.aluop[1] / Q 72 | ||||
| l3.cpu.0.u0.p0.iu0.r.e.aluop[2] / Q 42 | ||||
| l3.cpu.0.u0.p0.iu0.r.a.rsel2[0] / Q 33 | ||||
| l3.cpu.0.u0.p0.iu0.r.a.rsel2[1] / Q 65 | ||||
| l3.cpu.0.u0.p0.iu0.r.a.rsel2[2] / Q 97 | ||||
| l3.cpu.0.u0.p0.iu0.r.e.ldbp2 / Q 71 | ||||
| l3.cpu.0.u0.p0.iu0.r.e.invop2 / Q 64 | ||||
| l3.cpu.0.u0.p0.iu0.comb.diagread.un497_dbgunit / Y 35 | ||||
| l3.cpu.0.u0.p0.iu0.comb.logic_op.un1_r.e.mulstep / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.r.x.ctrl.ld / Q 33 | ||||
| l3.cpu.0.u0.p0.iu0.r.e.ldbp1 / Q 159 | ||||
| l3.cpu.0.u0.p0.iu0.comb.lock_gen.call_hold5 / Y 38 | ||||
| l3.cpu.0.u0.p0.iu0.comb.alu_op.y08 / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.un1_r.x.ctrl.wy_1 / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.un1_r.e.ctrl.wy_1 / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.vir.addr_3_sqmuxa / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.data_0_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.comb.logic_op.y14 / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.aluresult_0_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.aluresult_3_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.vir.addr_1_sqmuxa / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.vir.addr_2_sqmuxa / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.aluresult_7_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.aop1_1_sqmuxa / Y 34 | ||||
| l3.cpu.0.u0.p0.iu0.aluresult_10_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.comb.misc_op.bpdata6 / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.r.e.shleft / Q 63 | ||||
| l3.cpu.0.u0.p0.iu0.aluresult_12_sqmuxa / Y 28 | ||||
| l3.cpu.0.u0.p0.iu0.un1_r.e.jmpl / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.edata_3_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.fpcwr_6_sqmuxa / Y 28 | ||||
| l3.cpu.0.u0.p0.iu0.data_0_sqmuxa_2 / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.data_3_sqmuxa_1 / Y 28 | ||||
| l3.cpu.0.u0.p0.iu0.data_4_sqmuxa_1 / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.data_5_sqmuxa_1 / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.mresult2_1_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_3 / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.mresult2_2_sqmuxa_1 / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.aluresult_1_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.fpcwr_3_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.fpcwr_8_sqmuxa / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.aluresult_2_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.un1_aop2_1_sqmuxa / Y 33 | ||||
| l3.cpu.0.u0.p0.iu0.xc_trap_address_2_sqmuxa / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.xc_trap_address_1_sqmuxa / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.comb.ex_bpmiss / Y 43 | ||||
| l3.cpu.0.u0.p0.iu0.comb.ra_bpmiss_1 / Y 37 | ||||
| l3.cpu.0.u0.p0.iu0.comb.dcache_gen.jump / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.un1_vir.addr_0_sqmuxa / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_6 / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.comb.xc_exception_1_0_a4_3 / Y 41 | ||||
| l3.cpu.0.u0.p0.iu0.v.w.s.y_1_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.v.w.s.y_2_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_8 / Y 39 | ||||
| l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_10 / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.comb.un6_xc_exception / Y 31 | ||||
| l3.cpu.0.u0.p0.iu0.un1_ico / Y 33 | ||||
| l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_2_s3 / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_0_s1 / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.un1_de_branch_1 / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.un1_de_hold_pc_2 / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_1_s2 / Y 30 | ||||
| l3.cpu.0.u0.p0.iu0.comb.dbg_cache.dci2.asis_sn_i0_i_0 / Y 64 | ||||
| l3.cpu.0.u0.p0.iu0.r.x.rstate[1] / Q 31 | ||||
| l3.cpu.0.u0.p0.iu0.r.x.rstate_s1_0_a2 / Y 38 | ||||
| l3.cpu.0.u0.p0.iu0.aop2_2_sqmuxa / Y 33 | ||||
| l3.cpu.0.u0.p0.iu0.comb.logic_op.logicout_4_0_e[0] / Y 30 | ||||
| SM0.SM.CALC0.DRIVE.CTRL[0] / Q 33 | ||||
| SM0.SM.CALC0.DRIVE.CTRL[2] / Q 33 | ||||
| SM0.SM.CALC0.ALU0.arith.MACinst.clr_MACREG1.Q[0] / Q 33 | ||||
| SM0.SM.CALC0.DRIVE.OP1im_1_sqmuxa / Y 32 | ||||
| SM0.SM.CALC0.DRIVE.OP1re_1_sqmuxa / Y 32 | ||||
| SM0.SM.CALC0.DRIVE.un1_reset_inv / Y 32 | ||||
| FFT0.FFT0.smTop_0.smPong_xhdl14 / Q 211 | ||||
| FFT0.LINK.FifoCpt[0] / Q 121 | ||||
| FFT0.LINK.FifoCpt[1] / Q 146 | ||||
| FFT0.LINK.FifoCpt[2] / Q 148 | ||||
| FFT0.LINK.ect[0] / Q 154 | ||||
| FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[3] / Q 100 | ||||
| FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[4] / Q 87 | ||||
| FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[5] / Q 84 | ||||
| FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[6] / Q 128 | ||||
| FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[7] / Q 79 | ||||
| FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[8] / Q 50 | ||||
| FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[9] / Q 36 | ||||
| FFT0.FFT0.smTop_0.inBuf_rA_0.swCross_int / Q 63 | ||||
| FFT0.FFT0.bfly_0.swCrossOut_xhdl4 / Q 64 | ||||
| FFT0.FFT0.outBuff_0.rAmsb_r2 / Q 32 | ||||
| FFT0.FFT0.bfly_0.am3QiTr.t_r[0] / Q 44 | ||||
| FFT0.FFT0.bfly_0.am3QiTr.t_r[3] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTr.t_r[5] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTr.t_r[7] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTr.t_r[9] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTr.t_r[11] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTr.t_r[13] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTi.t_r[0] / Q 44 | ||||
| FFT0.FFT0.bfly_0.am3QiTi.t_r[3] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTi.t_r[5] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTi.t_r[7] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTi.t_r[9] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTi.t_r[11] / Q 26 | ||||
| FFT0.FFT0.bfly_0.am3QiTi.t_r[13] / Q 26 | ||||
| FFT0.FFT0.smTop_0.nGrst / Y 50 : 50 asynchronous set/reset | ||||
| FFT0.DRIVE.FifoCpt[0] / Q 72 | ||||
| FFT0.DRIVE.FifoCpt[1] / Q 39 | ||||
| DMUX0.ect[2] / Q 98 | ||||
| DMUX0.ect[1] / Q 99 | ||||
| ACQ0.sample_val_delay / Q 147 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.sample_out_val / Q 29 | ||||
| ACQ0.Downsampling_f0.sample_out_val / Q 73 | ||||
| ACQ0.Downsampling_f3.sample_out_0_sqmuxa / Y 81 | ||||
| ACQ0.Downsampling_f1.sample_out_0_sqmuxa / Y 81 | ||||
| ACQ0.Downsampling_f0.sample_out_0_sqmuxa / Y 81 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.alu_selected_coeff[0] / Q 26 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.alu_selected_coeff[2] / Q 25 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.sample_out_rot / Q 128 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.clr_MACREG1.Q[0] / Q 26 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.addREG.Q[0] / Q 26 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.MACMUXselREG.Q[0] / Q 50 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.adder_inst.un1_clr_1 / Y 25 | ||||
| ACQ0.DIGITAL_acquisition.sample_bit_counter[0] / Q 124 | ||||
| ACQ0.DIGITAL_acquisition.un12_sample_bit_counter_0_a2 / Y 129 | ||||
| SM0.SM.CALC0.ALU0.arith.MACinst.adder_inst.un1_clr_1 / Y 32 | ||||
| FFT0.LINK.un1_rstn_inv_0 / Y 80 | ||||
| FFT0.LINK.un28_data[16] / Y 36 | ||||
| FFT0.LINK.un28_data[0] / Y 49 | ||||
| FFT0.LINK.un26_data.un19_data_488 / Y 37 | ||||
| FFT0.LINK.Write_4_i_o3[2] / Y 35 | ||||
| l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[1] / Y 37 | ||||
| dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_2[2] / Y 30 | ||||
| dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_3[2] / Y 30 | ||||
| dcomgen.dcom0.dcom0.un1_r.state_4_0_0_0 / Y 31 | ||||
| l3.cpu.0.u0.p0.iu0.comb.un1_r.m.ctrl.ld / Y 38 | ||||
| l3.cpu.0.u0.p0.iu0.r.x.mexc_1_sqmuxa / Y 34 | ||||
| memctrlr.v.address_1_sqmuxa_i / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.comb.ex_sari_1_1 / Y 31 | ||||
| MemOut.un1_rst_inv_i_0_a3 / Y 32 | ||||
| l3.dsugen.dsu0.x0.v.bmsk_1_sqmuxa_2_i_o2 / Y 35 | ||||
| apb0.v.pwdata_1_sqmuxa_i_i_a2 / Y 32 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.Chanel_ongoinglde_0_0 / Y 32 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.un1_alu_sel_input_0_sqmuxa_1_i_0_s_0 / Y 32 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.MAC_CONTROLER1.un2_mult_i_x2 / Y 25 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.Chanel_ongoinglde_0_0_o2 / Y 37 | ||||
| ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.17.loop_all_chanel.7.un1_sample_in_rotate / Y 128 | ||||
| DMUX0.un1_ect_1_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.r.x.rstate_ns_i_a5_0_0[1] / Y 26 | ||||
| l3.cpu.0.u0.p0.iu0.comb.un16_casaen_0 / Y 73 | ||||
| l3.cpu.0.u0.p0.c0mmu.icache0.un1_ici_1_stt_0_m2 / Y 31 | ||||
| l3.dsugen.dsu0.x0.un1_v.cnt3_i_a2 / Y 31 | ||||
| gpt.timer0.comb.v.timers_2.value_1_sn_m1_0_a2 / Y 32 | ||||
| l3.cpu.0.u0.p0.c0mmu.icache0.cdwrite_0_sqmuxa / Y 32 | ||||
| l3.cpu.0.u0.p0.c0mmu.dcache0.rdatasel_1_1_i_o3 / Y 32 | ||||
| l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[1] / Y 33 | ||||
| l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[2] / Y 35 | ||||
| l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[3] / Y 39 | ||||
| l3.cpu.0.u0.p0.iu0.aluresult_8_sqmuxa / Y 27 | ||||
| l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[4] / Y 47 | ||||
| l3.cpu.0.u0.p0.iu0.r.d.pc_1198_e / Y 30 | ||||
| gpt.timer0.comb.v.timers_1.value_1_sn_m1_0_a2 / Y 32 | ||||
| DMUX0.Data_sn_m2 / Y 69 | ||||
| ACQ0.Downsampling_f1.un10_sample_in_val_24 / Y 27 | ||||
| ACQ0.Downsampling_f1.un10_sample_in_val_25 / Y 27 | ||||
| ACQ0.Downsampling_f0.un14_sample_in_val_24 / Y 27 | ||||
| ACQ0.Downsampling_f0.un14_sample_in_val_25 / Y 27 | ||||
| =============================================================================================================================================== | ||||
| @N: FP130 |Promoting Net lclk_c_c_c on CLKINT lclk_inferred_clock | ||||
| @N: FP130 |Promoting Net rstn on CLKINT I_1726 | ||||
| @N: FP130 |Promoting Net l3\.cpu\.0\.u0.holdn on CLKINT I_1727 | ||||
| @N: FP130 |Promoting Net FFT0.un1_FFT0 on CLKINT I_1728 | ||||
| @N: FP130 |Promoting Net N_202 on CLKINT I_1729 | ||||
| @N: FP130 |Promoting Net l3\.cpu\.0\.u0.rst on CLKINT I_1730 | ||||
| Replicating Combinational Instance ACQ0.Downsampling_f0.un14_sample_in_val_25, fanout 27 segments 2 | ||||
| Replicating Combinational Instance ACQ0.Downsampling_f0.un14_sample_in_val_24, fanout 27 segments 2 | ||||
| Replicating Combinational Instance ACQ0.Downsampling_f1.un10_sample_in_val_25, fanout 27 segments 2 | ||||
| Replicating Combinational Instance ACQ0.Downsampling_f1.un10_sample_in_val_24, fanout 27 segments 2 | ||||
| Replicating Combinational Instance DMUX0.Data_sn_m2, fanout 69 segments 3 | ||||
| Replicating Combinational Instance gpt.timer0.comb.v.timers_1.value_1_sn_m1_0_a2, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.d.pc_1198_e, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[4], fanout 47 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_8_sqmuxa, fanout 27 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[3], fanout 39 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[2], fanout 35 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[1], fanout 33 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.rdatasel_1_1_i_o3, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.cdwrite_0_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.comb.v.timers_2.value_1_sn_m1_0_a2, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.dsugen.dsu0.x0.un1_v.cnt3_i_a2, fanout 31 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.un1_ici_1_stt_0_m2, fanout 31 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un16_casaen_0, fanout 73 segments 4 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.rstate_ns_i_a5_0_0[1], fanout 26 segments 2 | ||||
| Replicating Combinational Instance DMUX0.un1_ect_1_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance ACQ0.IIR_CEL_CTRLR_v2_1.loop_all_sample.17.loop_all_chanel.7.un1_sample_in_rotate, fanout 128 segments 6 | ||||
| Replicating Combinational Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.Chanel_ongoinglde_0_0_o2, fanout 37 segments 2 | ||||
| Replicating Combinational Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.MAC_CONTROLER1.un2_mult_i_x2, fanout 25 segments 2 | ||||
| Replicating Combinational Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.un1_alu_sel_input_0_sqmuxa_1_i_0_s_0, fanout 32 segments 2 | ||||
| Replicating Combinational Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.Chanel_ongoinglde_0_0, fanout 32 segments 2 | ||||
| Replicating Combinational Instance ua1.uart1.v.brate_1_sqmuxa_0_o2, fanout 25 segments 2 | ||||
| Replicating Combinational Instance irqctrl.irqctrl0.v.ipend_1_sqmuxa_i_o2_0_o2, fanout 25 segments 2 | ||||
| Replicating Combinational Instance apb0.v.pwdata_1_sqmuxa_i_i_a2, fanout 32 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.v.timers_2.value_1_sqmuxa, fanout 33 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.v.timers_1.value_1_sqmuxa, fanout 33 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.v.timers_2.value_2_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.v.timers_1.value_2_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.v.timers_2.reload_1_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.v.timers_1.reload_1_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.dsugen.dsu0.x0.v.bmsk_1_sqmuxa_2_i_o2, fanout 35 segments 2 | ||||
| Replicating Combinational Instance MemOut.un1_rst_inv_i_0_a3, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_sari_1_1, fanout 31 segments 2 | ||||
| Replicating Combinational Instance memctrlr.v.address_1_sqmuxa_i, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.mexc_1_sqmuxa, fanout 34 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un1_r.m.ctrl.ld, fanout 38 segments 2 | ||||
| Replicating Combinational Instance dcomgen.dcom0.dcom0.un1_r.state_4_0_0_0, fanout 31 segments 2 | ||||
| Replicating Combinational Instance dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_3[2], fanout 30 segments 2 | ||||
| Replicating Combinational Instance dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_2[2], fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[1], fanout 37 segments 2 | ||||
| Replicating Combinational Instance FFT0.LINK.Write_4_i_o3[2], fanout 35 segments 2 | ||||
| Replicating Combinational Instance FFT0.LINK.un26_data.un19_data_488, fanout 37 segments 2 | ||||
| Replicating Combinational Instance FFT0.LINK.un28_data[0], fanout 49 segments 3 | ||||
| Replicating Combinational Instance FFT0.LINK.un28_data[16], fanout 36 segments 2 | ||||
| Replicating Combinational Instance FFT0.LINK.un1_rstn_inv_0, fanout 80 segments 4 | ||||
| Replicating Combinational Instance SM0.SM.CALC0.ALU0.arith.MACinst.adder_inst.un1_clr_1, fanout 32 segments 2 | ||||
| Replicating Combinational Instance ACQ0.DIGITAL_acquisition.un12_sample_bit_counter_0_a2, fanout 129 segments 6 | ||||
| Replicating Sequential Instance ACQ0.DIGITAL_acquisition.sample_bit_counter[0], fanout 124 segments 6 | ||||
| Replicating Combinational Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.adder_inst.un1_clr_1, fanout 25 segments 2 | ||||
| Replicating Sequential Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.MACMUXselREG.Q[0], fanout 50 segments 3 | ||||
| Replicating Sequential Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.addREG.Q[0], fanout 27 segments 2 | ||||
| Replicating Sequential Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_DATAFLOW_1.ALU_1.arith.MACinst.clr_MACREG1.Q[0], fanout 27 segments 2 | ||||
| Replicating Sequential Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.sample_out_rot, fanout 128 segments 6 | ||||
| Replicating Sequential Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.alu_selected_coeff[2], fanout 25 segments 2 | ||||
| Replicating Sequential Instance ACQ0.IIR_CEL_CTRLR_v2_1.IIR_CEL_CTRLR_v2_CONTROL_1.alu_selected_coeff[0], fanout 26 segments 2 | ||||
| Replicating Combinational Instance ACQ0.Downsampling_f0.sample_out_0_sqmuxa, fanout 81 segments 4 | ||||
| Replicating Combinational Instance ACQ0.Downsampling_f1.sample_out_0_sqmuxa, fanout 81 segments 4 | ||||
| Replicating Combinational Instance ACQ0.Downsampling_f3.sample_out_0_sqmuxa, fanout 81 segments 4 | ||||
| Replicating Sequential Instance ACQ0.Downsampling_f0.sample_out_val, fanout 79 segments 4 | ||||
| Replicating Sequential Instance ACQ0.IIR_CEL_CTRLR_v2_1.sample_out_val, fanout 32 segments 2 | ||||
| Replicating Sequential Instance ACQ0.sample_val_delay, fanout 152 segments 7 | ||||
| Replicating Sequential Instance DMUX0.ect[1], fanout 100 segments 5 | ||||
| Replicating Sequential Instance DMUX0.ect[2], fanout 100 segments 5 | ||||
| Replicating Sequential Instance FFT0.DRIVE.FifoCpt[1], fanout 39 segments 2 | ||||
| Replicating Sequential Instance FFT0.DRIVE.FifoCpt[0], fanout 72 segments 3 | ||||
| Replicating Combinational Instance FFT0.FFT0.smTop_0.nGrst, fanout 50 segments 3 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTi.t_r[13], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTi.t_r[11], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTi.t_r[9], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTi.t_r[7], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTi.t_r[5], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTi.t_r[3], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTi.t_r[0], fanout 44 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTr.t_r[13], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTr.t_r[11], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTr.t_r[9], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTr.t_r[7], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTr.t_r[5], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTr.t_r[3], fanout 26 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.am3QiTr.t_r[0], fanout 44 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.outBuff_0.rAmsb_r2, fanout 32 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.bfly_0.swCrossOut_xhdl4, fanout 64 segments 3 | ||||
| Replicating Sequential Instance FFT0.FFT0.smTop_0.inBuf_rA_0.swCross_int, fanout 63 segments 3 | ||||
| Replicating Sequential Instance FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[9], fanout 36 segments 2 | ||||
| Replicating Sequential Instance FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[8], fanout 50 segments 3 | ||||
| Replicating Sequential Instance FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[7], fanout 79 segments 4 | ||||
| Replicating Sequential Instance FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[6], fanout 128 segments 6 | ||||
| Replicating Sequential Instance FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[5], fanout 84 segments 4 | ||||
| Replicating Sequential Instance FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[4], fanout 87 segments 4 | ||||
| Replicating Sequential Instance FFT0.FFT0.smTop_0.twid_wA_0.slowTimer.Q_out[3], fanout 100 segments 5 | ||||
| Replicating Sequential Instance FFT0.LINK.ect[0], fanout 157 segments 7 | ||||
| Replicating Sequential Instance FFT0.LINK.FifoCpt[2], fanout 153 segments 7 | ||||
| Replicating Sequential Instance FFT0.LINK.FifoCpt[1], fanout 148 segments 7 | ||||
| Replicating Sequential Instance FFT0.LINK.FifoCpt[0], fanout 123 segments 6 | ||||
| Replicating Combinational Instance SM0.SM.CALC0.DRIVE.un1_reset_inv, fanout 32 segments 2 | ||||
| Replicating Combinational Instance SM0.SM.CALC0.DRIVE.OP1re_1_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance SM0.SM.CALC0.DRIVE.OP1im_1_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Sequential Instance SM0.SM.CALC0.ALU0.arith.MACinst.clr_MACREG1.Q[0], fanout 34 segments 2 | ||||
| Replicating Sequential Instance SM0.SM.CALC0.DRIVE.CTRL[2], fanout 34 segments 2 | ||||
| Replicating Sequential Instance SM0.SM.CALC0.DRIVE.CTRL[0], fanout 33 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.logic_op.logicout_4_0_e[0], fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aop2_2_sqmuxa, fanout 33 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.rstate_s1_0_a2, fanout 38 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.rstate[1], fanout 33 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.dbg_cache.dci2.asis_sn_i0_i_0, fanout 64 segments 3 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_1_s2, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_de_hold_pc_2, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_de_branch_1, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_0_s1, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_2_s3, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_ico, fanout 33 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un6_xc_exception, fanout 31 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_10, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_8, fanout 39 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.v.w.s.y_2_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.v.w.s.y_1_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.xc_exception_1_0_a4_3, fanout 41 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_6, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_vir.addr_0_sqmuxa, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.dcache_gen.jump, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ra_bpmiss_1, fanout 37 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_bpmiss, fanout 44 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.xc_trap_address_1_sqmuxa, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.xc_trap_address_2_sqmuxa, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_aop2_1_sqmuxa, fanout 33 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_2_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_8_sqmuxa, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_3_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_1_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.mresult2_2_sqmuxa_1, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_3, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.mresult2_1_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_5_sqmuxa_1, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_4_sqmuxa_1, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_3_sqmuxa_1, fanout 28 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_0_sqmuxa_2, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_6_sqmuxa, fanout 28 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.edata_3_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.e.jmpl, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_12_sqmuxa, fanout 28 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.shleft, fanout 63 segments 3 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.misc_op.bpdata6, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_10_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aop1_1_sqmuxa, fanout 35 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_7_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.vir.addr_2_sqmuxa, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.vir.addr_1_sqmuxa, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_3_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_0_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.logic_op.y14, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_0_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.vir.addr_3_sqmuxa, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.e.ctrl.wy_1, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.ctrl.wy_1, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.alu_op.y08, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.lock_gen.call_hold5, fanout 38 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.ldbp1, fanout 160 segments 7 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.ctrl.ld, fanout 33 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.logic_op.un1_r.e.mulstep, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.diagread.un497_dbgunit, fanout 36 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.invop2, fanout 64 segments 3 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.ldbp2, fanout 75 segments 4 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel2[2], fanout 97 segments 5 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel2[1], fanout 65 segments 3 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel2[0], fanout 33 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.aluop[2], fanout 44 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.aluop[1], fanout 73 segments 4 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.aluop[0], fanout 39 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel1[2], fanout 97 segments 5 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel1[1], fanout 65 segments 3 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel1[0], fanout 33 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.npc[1], fanout 68 segments 3 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.npc[0], fanout 38 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.v.vaddress_0_sqmuxa_0_a2, fanout 60 segments 3 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.icache0.r.istate[0], fanout 46 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.diagen_0_sqmuxa, fanout 41 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.data1_0_sqmuxa_i_o2, fanout 33 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_i[5], fanout 43 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_tr0_0_0_a3, fanout 38 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s1, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s0, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_1_sqmuxa_1, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_5_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.wb.data2_0_sqmuxa, fanout 70 segments 3 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.read_0_sqmuxa_1, fanout 38 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.mexc_0_sqmuxa, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.read_0_sqmuxa, fanout 40 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.v.hit2, fanout 39 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate[4], fanout 74 segments 4 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.a0.r.bo_s2_0_a2, fanout 33 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[0], fanout 39 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.read_1, fanout 42 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.r.istate_tr3_1, fanout 41 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.m.dci.dsuen, fanout 25 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.m.dci.asi[4], fanout 25 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.m.dci.asi[3], fanout 27 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp, fanout 32 segments 2 | ||||
| Replicating Combinational Instance l3.dsugen.dsu0.x0.v.slv.hwrite_0_sqmuxa_i_0_o2, fanout 30 segments 2 | ||||
| Replicating Combinational Instance l3.dsugen.dsu0.x0.comb.v.slv.hready33_0_o3, fanout 33 segments 2 | ||||
| Replicating Combinational Instance l3.dsugen.dsu0.x0.un1_v.cnt3_2_1, fanout 32 segments 2 | ||||
| Replicating Combinational Instance irqctrl.irqctrl0.comb.v.iforce_0_6_sn_m2_0, fanout 26 segments 2 | ||||
| Replicating Combinational Instance dcomgen.dcom0.dcom0.un1_v.data_0_sqmuxa_0_0, fanout 32 segments 2 | ||||
| Replicating Sequential Instance dcomgen.dcom0.dcom0.r.state[3], fanout 36 segments 2 | ||||
| Replicating Sequential Instance dcomgen.dcom0.dcom0.r.state[4], fanout 40 segments 2 | ||||
| Replicating Combinational Instance apb0.comb.v.prdata_1_0_0_a2_3[31], fanout 27 segments 2 | ||||
| Replicating Combinational Instance apb0.comb.v.prdata_1_0_0_a2_2[31], fanout 27 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.readdata_1_sqmuxa_1, fanout 34 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.v.timers_2.value_0_sqmuxa, fanout 34 segments 2 | ||||
| Replicating Combinational Instance gpt.timer0.comb.1.readdata_9_sn_m3, fanout 32 segments 2 | ||||
| Replicating Sequential Instance gpt.timer0.r.tsel[0], fanout 37 segments 2 | ||||
| Replicating Combinational Instance MemCal.PRdata_cl_24_i_0_a3[31], fanout 26 segments 2 | ||||
| Replicating Combinational Instance SM0.SM.Conjugate_int_0, fanout 25 segments 2 | ||||
| Replicating Combinational Instance SM0.SM.RES0.un1_Received_0_sqmuxa_0_a2_0, fanout 33 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.d.inst_0[22], fanout 25 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.d.inst_0[21], fanout 36 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.d.inst_0[12], fanout 27 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.flush, fanout 37 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.icache0.r.flush2, fanout 34 segments 2 | ||||
| Replicating Combinational Instance MemCal.prdata13_1_0_a2_0_a3, fanout 38 segments 2 | ||||
| Replicating Combinational Instance memctrlr.v.writedata_0_sqmuxa_i, fanout 32 segments 2 | ||||
| Replicating Sequential Instance COM0.COM0.RX_REG.Serialized_int, fanout 25 segments 2 | ||||
| Replicating Sequential Instance COM0.COM0.Take, fanout 37 segments 2 | ||||
| Buffering COM0.COM0.Bclk, fanout 50 segments 3 | ||||
| Replicating Combinational Instance ahb0.comb.hready_1_iv, fanout 47 segments 2 | ||||
| Replicating Sequential Instance COM0.Send, fanout 29 segments 2 | ||||
| Replicating Sequential Instance ahb0.r.hmasterd[0], fanout 32 segments 2 | ||||
| Replicating Sequential Instance ahb0.r.hslave[0], fanout 38 segments 2 | ||||
| Replicating Sequential Instance apb0.r.pwdata[6], fanout 27 segments 2 | ||||
| Replicating Sequential Instance apb0.r.pwdata[5], fanout 29 segments 2 | ||||
| Replicating Sequential Instance apb0.r.pwdata[4], fanout 31 segments 2 | ||||
| Replicating Sequential Instance apb0.r.pwdata[3], fanout 29 segments 2 | ||||
| Replicating Sequential Instance apb0.r.pwdata[2], fanout 28 segments 2 | ||||
| Replicating Sequential Instance apb0.r.pwdata[1], fanout 31 segments 2 | ||||
| Replicating Sequential Instance apb0.r.haddr[4], fanout 52 segments 3 | ||||
| Replicating Sequential Instance apb0.r.haddr[3], fanout 43 segments 2 | ||||
| Replicating Sequential Instance apb0.r.haddr[2], fanout 95 segments 4 | ||||
| Buffering apbi\.penable, fanout 95 segments 4 | ||||
| Replicating Combinational Instance dcomgen.dcom0.dcom_uart0.uartop.tmp, fanout 59 segments 3 | ||||
| Replicating Sequential Instance ahb0.r.hmaster[0], fanout 46 segments 2 | ||||
| Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.de_hold_pc_m2, fanout 25 segments 2 | ||||
| Replicating Combinational Instance apb0.v.hready_0_sqmuxa_0_a3_0_a2, fanout 28 segments 2 | ||||
| Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.d.inst_0[30], fanout 25 segments 2 | ||||
| Finished technology mapping (Time elapsed 0h:02m:45s; Memory used current: 225MB peak: 273MB) | ||||
| Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:02m:50s; Memory used current: 225MB peak: 273MB) | ||||
| Added 6 Buffers | ||||
| Added 353 Cells via replication | ||||
| Added 175 Sequential Cells via replication | ||||
| Added 178 Combinational Cells via replication | ||||
| Finished restoring hierarchy (Time elapsed 0h:02m:53s; Memory used current: 233MB peak: 273MB) | ||||
| Writing Analyst data base C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\synthesis\leon3mp.srm | ||||
| Finished Writing Netlist Databases (Time elapsed 0h:02m:59s; Memory used current: 214MB peak: 273MB) | ||||
| Writing EDIF Netlist and constraint files | ||||
| E-2010.09A-1 | ||||
| Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:03m:03s; Memory used current: 221MB peak: 273MB) | ||||
| @W: MT420 |Found inferred clock leon3mp|clk50MHz with period 10.00ns. A user-defined clock should be declared on object "p:clk50MHz" | ||||
| @W: MT420 |Found inferred clock leon3mp|lclk_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:lclk" | ||||
| @W: MT420 |Found inferred clock apbctrl|r_penable_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:apb0.r.penable" | ||||
| @W: MT420 |Found inferred clock BaudGen|Bclk_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:COM0.COM0.BaudGenerator.Bclk" | ||||
| @W: MT420 |Found inferred clock Clock_Divider|clockint_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:CAL0.CLK0.clockint" | ||||
| ##### START OF TIMING REPORT #####[ | ||||
| # Timing Report written on Thu Dec 19 12:52:05 2013 | ||||
| # | ||||
| Top view: leon3mp | ||||
| Library name: pa3l | ||||
| Operating conditions: COMWC-1 ( T = 70.0, V = 1.14, P = 1.10, tree_type = balanced_tree ) | ||||
| Requested Frequency: 100.0 MHz | ||||
| Wire load mode: top | ||||
| Wire load model: pa3l | ||||
| Paths requested: 5 | ||||
| Constraint File(s): | ||||
| @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.. | ||||
| @N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.. | ||||
| Performance Summary | ||||
| ******************* | ||||
| Worst slack in design: -15.964 | ||||
| Requested Estimated Requested Estimated Clock Clock | ||||
| Starting Clock Frequency Frequency Period Period Slack Type Group | ||||
| ---------------------------------------------------------------------------------------------------------------------------------------------- | ||||
| BaudGen|Bclk_inferred_clock 100.0 MHz 130.9 MHz 10.000 7.639 2.361 inferred Inferred_clkgroup_3 | ||||
| Clock_Divider|clockint_inferred_clock 100.0 MHz 201.8 MHz 10.000 4.955 5.045 inferred Inferred_clkgroup_4 | ||||
| apbctrl|r_penable_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 | ||||
| leon3mp|clk50MHz 100.0 MHz 133.6 MHz 10.000 7.487 2.513 inferred Inferred_clkgroup_2 | ||||
| leon3mp|lclk_inferred_clock 100.0 MHz 38.5 MHz 10.000 25.965 -15.964 inferred Inferred_clkgroup_0 | ||||
| ============================================================================================================================================== | ||||
| Clock Relationships | ||||
| ******************* | ||||
| Clocks | rise to rise | fall to fall | rise to fall | fall to rise | ||||
| ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ||||
| Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack | ||||
| ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ||||
| leon3mp|lclk_inferred_clock leon3mp|lclk_inferred_clock | 10.000 -15.965 | No paths - | No paths - | No paths - | ||||
| leon3mp|lclk_inferred_clock apbctrl|r_penable_inferred_clock | Diff grp - | No paths - | No paths - | No paths - | ||||
| apbctrl|r_penable_inferred_clock leon3mp|lclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - | ||||
| leon3mp|clk50MHz leon3mp|lclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - | ||||
| leon3mp|clk50MHz leon3mp|clk50MHz | 10.000 2.513 | No paths - | No paths - | No paths - | ||||
| BaudGen|Bclk_inferred_clock leon3mp|lclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - | ||||
| BaudGen|Bclk_inferred_clock BaudGen|Bclk_inferred_clock | 10.000 2.361 | No paths - | No paths - | No paths - | ||||
| Clock_Divider|clockint_inferred_clock leon3mp|lclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - | ||||
| Clock_Divider|clockint_inferred_clock Clock_Divider|clockint_inferred_clock | 10.000 5.045 | No paths - | No paths - | No paths - | ||||
| ====================================================================================================================================================================== | ||||
| Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. | ||||
| 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. | ||||
| Interface Information | ||||
| ********************* | ||||
| No IO constraint found | ||||
| ==================================== | ||||
| Detailed Report for Clock: BaudGen|Bclk_inferred_clock | ||||
| ==================================== | ||||
| Starting Points with Worst Slack | ||||
| ******************************** | ||||
| Starting Arrival | ||||
| Instance Reference Type Pin Net Time Slack | ||||
| Clock | ||||
| --------------------------------------------------------------------------------------------------------------------------- | ||||
| COM0.COM0.RX_REG.CptBits[9] BaudGen|Bclk_inferred_clock DFN1C1 Q CptBits[9] 0.693 2.361 | ||||
| COM0.COM0.RX_REG.CptBits[7] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[7] 0.693 2.593 | ||||
| COM0.COM0.RX_REG.CptBits[1] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[1] 0.693 2.659 | ||||
| COM0.COM0.RX_REG.CptBits[6] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[6] 0.693 2.699 | ||||
| COM0.COM0.RX_REG.CptBits[8] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[8] 0.693 2.732 | ||||
| COM0.COM0.RX_REG.CptBits[3] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[3] 0.693 2.793 | ||||
| COM0.COM0.RX_REG.CptBits[0] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[0] 0.693 2.805 | ||||
| COM0.COM0.RX_REG.CptBits[2] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[2] 0.693 2.899 | ||||
| COM0.COM0.RX_REG.Serialized_int_0 BaudGen|Bclk_inferred_clock DFN1C1 Q Taken_0 0.693 3.336 | ||||
| COM0.COM0.RX_REG.CptBits[4] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[4] 0.693 3.419 | ||||
| =========================================================================================================================== | ||||
| Ending Points with Worst Slack | ||||
| ****************************** | ||||
| Starting Required | ||||
| Instance Reference Type Pin Net Time Slack | ||||
| Clock | ||||
| ---------------------------------------------------------------------------------------------------------------- | ||||
| COM0.COM0.RX_REG.Q_1[1] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[1] 7.460 2.361 | ||||
| COM0.COM0.RX_REG.Q_1[2] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[2] 7.460 2.361 | ||||
| COM0.COM0.RX_REG.Q_1[3] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[3] 7.460 2.361 | ||||
| COM0.COM0.RX_REG.Q_1[4] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[4] 7.460 2.361 | ||||
| COM0.COM0.RX_REG.Q_1[5] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[5] 7.460 2.361 | ||||
| COM0.COM0.RX_REG.Q_1[6] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[6] 7.460 2.361 | ||||
| COM0.COM0.RX_REG.Q_1[7] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[7] 7.460 2.361 | ||||
| COM0.COM0.RX_REG.Q_1[8] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[8] 7.460 2.361 | ||||
| COM0.COM0.TX_REG.REG[1] BaudGen|Bclk_inferred_clock DFN1P1C1 D REG_3[1] 7.460 4.577 | ||||
| COM0.COM0.TX_REG.REG[2] BaudGen|Bclk_inferred_clock DFN1P1C1 D REG_3[2] 7.460 4.577 | ||||
| ================================================================================================================ | ||||
| Worst Path Information | ||||
| *********************** | ||||
| Path information for path number 1: | ||||
| Requested Period: 10.000 | ||||
| - Setup time: 2.540 | ||||
| + Clock delay at ending point: 0.000 (ideal) | ||||
| = Required time: 7.460 | ||||
| - Propagation time: 5.100 | ||||
| - Clock delay at starting point: 0.000 (ideal) | ||||
| = Slack (non-critical) : 2.361 | ||||
| Number of logic level(s): 4 | ||||
| Starting point: COM0.COM0.RX_REG.CptBits[9] / Q | ||||
| Ending point: COM0.COM0.RX_REG.Q_1[1] / D | ||||
| The start point is clocked by BaudGen|Bclk_inferred_clock [rising] on pin CLK | ||||
| The end point is clocked by BaudGen|Bclk_inferred_clock [rising] on pin CLK | ||||
| Instance / Net Pin Pin Arrival No. of | ||||
| Name Type Name Dir Delay Time Fan Out(s) | ||||
| ------------------------------------------------------------------------------------------------------------- | ||||
| COM0.COM0.RX_REG.CptBits[9] DFN1C1 Q Out 0.693 0.693 - | ||||
| CptBits[9] Net - - 0.508 - 3 | ||||
| COM0.COM0.RX_REG.CptBits_RNID3M7[8] NOR2B B In - 1.202 - | ||||
| COM0.COM0.RX_REG.CptBits_RNID3M7[8] NOR2B Y Out 0.590 1.792 - | ||||
| cptbits_flag_4 Net - - 0.203 - 1 | ||||
| COM0.COM0.RX_REG.CptBits_RNIB92N[0] NOR3C C In - 1.995 - | ||||
| COM0.COM0.RX_REG.CptBits_RNIB92N[0] NOR3C Y Out 0.603 2.598 - | ||||
| cptbits_flag_7 Net - - 0.243 - 2 | ||||
| COM0.COM0.RX_REG.Serialized_int_0_RNIT3S81 NOR3B B In - 2.842 - | ||||
| COM0.COM0.RX_REG.Serialized_int_0_RNIT3S81 NOR3B Y Out 0.571 3.412 - | ||||
| Serialized_int_0_sqmuxa Net - - 1.034 - 8 | ||||
| COM0.COM0.RX_REG.Q_1_RNO_0[1] MX2 S In - 4.446 - | ||||
| COM0.COM0.RX_REG.Q_1_RNO_0[1] MX2 Y Out 0.451 4.897 - | ||||
| Q_3[1] Net - - 0.203 - 1 | ||||
| COM0.COM0.RX_REG.Q_1[1] DFN1P1C1 D In - 5.100 - | ||||
| ============================================================================================================= | ||||
| Total path delay (propagation time + setup) of 7.639 is 5.448(71.3%) logic and 2.191(28.7%) route. | ||||
| Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
| ==================================== | ||||
| Detailed Report for Clock: Clock_Divider|clockint_inferred_clock | ||||
| ==================================== | ||||
| Starting Points with Worst Slack | ||||
| ******************************** | ||||
| Starting Arrival | ||||
| Instance Reference Type Pin Net Time Slack | ||||
| Clock | ||||
| -------------------------------------------------------------------------------------------------------------------------- | ||||
| CAL0.CLKSET.clockint[1] Clock_Divider|clockint_inferred_clock DFN1C0 Q clockint[1] 0.693 5.045 | ||||
| CAL0.CLKSET.clockint[0] Clock_Divider|clockint_inferred_clock DFN1C0 Q clockint[0] 0.693 5.119 | ||||
| CAL0.CLKSET.clockint[2] Clock_Divider|clockint_inferred_clock DFN1C0 Q clockint[2] 0.693 5.250 | ||||
| CAL0.CLKSET.clockint[3] Clock_Divider|clockint_inferred_clock DFN1C0 Q clockint[3] 0.693 6.258 | ||||
| CAL0.CLKSET.clockint[4] Clock_Divider|clockint_inferred_clock DFN1C0 Q clockint[4] 0.693 6.329 | ||||
| CAL0.CLKSET.clockint[5] Clock_Divider|clockint_inferred_clock DFN1C0 Q clockint[5] 0.693 7.201 | ||||
| CAL0.CLKSET.clockint[6] Clock_Divider|clockint_inferred_clock DFN1C0 Q clockint[6] 0.693 7.894 | ||||
| ========================================================================================================================== | ||||
| Ending Points with Worst Slack | ||||
| ****************************** | ||||
| Starting Required | ||||
| Instance Reference Type Pin Net Time Slack | ||||
| Clock | ||||
| ----------------------------------------------------------------------------------------------------------------------------- | ||||
| CAL0.CLKSET.clockint[6] Clock_Divider|clockint_inferred_clock DFN1C0 D clockint_n6 9.493 5.045 | ||||
| CAL0.CLKSET.clockint[5] Clock_Divider|clockint_inferred_clock DFN1C0 D clockint_n5 9.493 5.498 | ||||
| CAL0.CLKSET.clockint[4] Clock_Divider|clockint_inferred_clock DFN1C0 D clockint_n4 9.493 5.859 | ||||
| CAL0.CLKSET.clockint[3] Clock_Divider|clockint_inferred_clock DFN1C0 D clockint_n3 9.493 6.312 | ||||
| CAL0.CLKSET.clockint[2] Clock_Divider|clockint_inferred_clock DFN1C0 D clockint_n2 9.493 6.902 | ||||
| CAL0.CLKSET.clockint[1] Clock_Divider|clockint_inferred_clock DFN1C0 D clockint_n1 9.493 6.909 | ||||
| CAL0.CLKSET.clockint[0] Clock_Divider|clockint_inferred_clock DFN1C0 D clockint_i[0] 9.493 7.313 | ||||
| ============================================================================================================================= | ||||
| Worst Path Information | ||||
| *********************** | ||||
| Path information for path number 1: | ||||
| Requested Period: 10.000 | ||||
| - Setup time: 0.507 | ||||
| + Clock delay at ending point: 0.000 (ideal) | ||||
| = Required time: 9.493 | ||||
| - Propagation time: 4.448 | ||||
| - Clock delay at starting point: 0.000 (ideal) | ||||
| = Slack (non-critical) : 5.045 | ||||
| Number of logic level(s): 3 | ||||
| Starting point: CAL0.CLKSET.clockint[1] / Q | ||||
| Ending point: CAL0.CLKSET.clockint[6] / D | ||||
| The start point is clocked by Clock_Divider|clockint_inferred_clock [rising] on pin CLK | ||||
| The end point is clocked by Clock_Divider|clockint_inferred_clock [rising] on pin CLK | ||||
| Instance / Net Pin Pin Arrival No. of | ||||
| Name Type Name Dir Delay Time Fan Out(s) | ||||
| ------------------------------------------------------------------------------------------------ | ||||
| CAL0.CLKSET.clockint[1] DFN1C0 Q Out 0.693 0.693 - | ||||
| clockint[1] Net - - 0.746 - 4 | ||||
| CAL0.CLKSET.clockint_RNISCN[2] NOR3C B In - 1.440 - | ||||
| CAL0.CLKSET.clockint_RNISCN[2] NOR3C Y Out 0.571 2.010 - | ||||
| clockint_c2 Net - - 0.508 - 3 | ||||
| CAL0.CLKSET.clockint_RNI9071[4] NOR3C B In - 2.519 - | ||||
| CAL0.CLKSET.clockint_RNI9071[4] NOR3C Y Out 0.571 3.089 - | ||||
| clockint_c4 Net - - 0.243 - 2 | ||||
| CAL0.CLKSET.clockint_RNO[6] AX1C B In - 3.333 - | ||||
| CAL0.CLKSET.clockint_RNO[6] AX1C Y Out 0.912 4.245 - | ||||
| clockint_n6 Net - - 0.203 - 1 | ||||
| CAL0.CLKSET.clockint[6] DFN1C0 D In - 4.448 - | ||||
| ================================================================================================ | ||||
| Total path delay (propagation time + setup) of 4.955 is 3.254(65.7%) logic and 1.701(34.3%) route. | ||||
| Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
| ==================================== | ||||
| Detailed Report for Clock: leon3mp|clk50MHz | ||||
| ==================================== | ||||
| Starting Points with Worst Slack | ||||
| ******************************** | ||||
| Starting Arrival | ||||
| Instance Reference Type Pin Net Time Slack | ||||
| Clock | ||||
| ------------------------------------------------------------------------------------------------------------------------------------ | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[0] leon3mp|clk50MHz DFN1C0 Q cnv_cycle_counter[0] 0.693 2.513 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[1] leon3mp|clk50MHz DFN1C0 Q cnv_cycle_counter[1] 0.693 2.884 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[2] leon3mp|clk50MHz DFN1C0 Q cnv_cycle_counter[2] 0.693 3.240 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[7] leon3mp|clk50MHz DFN1C0 Q cnv_cycle_counter[7] 0.693 3.722 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[3] leon3mp|clk50MHz DFN1C0 Q cnv_cycle_counter[3] 0.546 3.757 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[4] leon3mp|clk50MHz DFN1C0 Q cnv_cycle_counter[4] 0.693 3.791 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[6] leon3mp|clk50MHz DFN1C0 Q cnv_cycle_counter[6] 0.693 3.925 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[5] leon3mp|clk50MHz DFN1C0 Q cnv_cycle_counter[5] 0.693 4.031 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[8] leon3mp|clk50MHz DFN1C0 Q cnv_cycle_counter[8] 0.693 4.135 | ||||
| SSRAM_0.state[3] leon3mp|clk50MHz DFN1C1 Q state[3] 0.693 7.084 | ||||
| ==================================================================================================================================== | ||||
| Ending Points with Worst Slack | ||||
| ****************************** | ||||
| Starting Required | ||||
| Instance Reference Type Pin Net Time Slack | ||||
| Clock | ||||
| ------------------------------------------------------------------------------------------------------------------------------------- | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[7] leon3mp|clk50MHz DFN1C0 D cnv_cycle_counter_n7 9.460 2.513 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[8] leon3mp|clk50MHz DFN1C0 D cnv_cycle_counter_n8 9.493 2.562 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[6] leon3mp|clk50MHz DFN1C0 D cnv_cycle_counter_n6 9.493 3.196 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[5] leon3mp|clk50MHz DFN1C0 D cnv_cycle_counter_n5 9.460 3.846 | ||||
| ACQ0.DIGITAL_acquisition.cnv_s leon3mp|clk50MHz DFN1C0 D cnv_s_RNO 9.493 4.281 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[4] leon3mp|clk50MHz DFN1C0 D cnv_cycle_counter_n4 9.460 4.574 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[1] leon3mp|clk50MHz DFN1C0 D cnv_cycle_counter_n1 9.460 4.658 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[2] leon3mp|clk50MHz DFN1C0 D cnv_cycle_counter_n2 9.460 4.658 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[3] leon3mp|clk50MHz DFN1C0 D cnv_cycle_counter_n3 9.460 4.658 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[0] leon3mp|clk50MHz DFN1C0 D cnv_cycle_counter_n0 9.460 4.738 | ||||
| ===================================================================================================================================== | ||||
| Worst Path Information | ||||
| *********************** | ||||
| Path information for path number 1: | ||||
| Requested Period: 10.000 | ||||
| - Setup time: 0.540 | ||||
| + Clock delay at ending point: 0.000 (ideal) | ||||
| = Required time: 9.460 | ||||
| - Propagation time: 6.948 | ||||
| - Clock delay at starting point: 0.000 (ideal) | ||||
| = Slack (non-critical) : 2.513 | ||||
| Number of logic level(s): 7 | ||||
| Starting point: ACQ0.DIGITAL_acquisition.cnv_cycle_counter[0] / Q | ||||
| Ending point: ACQ0.DIGITAL_acquisition.cnv_cycle_counter[7] / D | ||||
| The start point is clocked by leon3mp|clk50MHz [rising] on pin CLK | ||||
| The end point is clocked by leon3mp|clk50MHz [rising] on pin CLK | ||||
| Instance / Net Pin Pin Arrival No. of | ||||
| Name Type Name Dir Delay Time Fan Out(s) | ||||
| ----------------------------------------------------------------------------------------------------------------------- | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[0] DFN1C0 Q Out 0.693 0.693 - | ||||
| cnv_cycle_counter[0] Net - - 0.508 - 3 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNI5SUF[1] NOR2B B In - 1.202 - | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNI5SUF[1] NOR2B Y Out 0.590 1.792 - | ||||
| cnv_cycle_counter_c1 Net - - 0.243 - 2 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNI9AUN[2] NOR2B A In - 2.035 - | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNI9AUN[2] NOR2B Y Out 0.484 2.519 - | ||||
| cnv_cycle_counter_c2 Net - - 0.243 - 2 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNIEOTV[3] NOR2B A In - 2.763 - | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNIEOTV[3] NOR2B Y Out 0.484 3.247 - | ||||
| cnv_cycle_counter_c3 Net - - 0.508 - 3 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNIK6T71[4] NOR2B A In - 3.755 - | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNIK6T71[4] NOR2B Y Out 0.484 4.239 - | ||||
| cnv_cycle_counter_c4 Net - - 0.243 - 2 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNIRKSF1[5] OR2B A In - 4.482 - | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNIRKSF1[5] OR2B Y Out 0.484 4.966 - | ||||
| cnv_cycle_counter_c5 Net - - 0.243 - 2 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNI33SN1[6] NOR2A B In - 5.210 - | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNI33SN1[6] NOR2A Y Out 0.363 5.573 - | ||||
| cnv_cycle_counter_c6 Net - - 0.243 - 2 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNO[7] XA1 B In - 5.816 - | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter_RNO[7] XA1 Y Out 0.929 6.745 - | ||||
| cnv_cycle_counter_n7 Net - - 0.203 - 1 | ||||
| ACQ0.DIGITAL_acquisition.cnv_cycle_counter[7] DFN1C0 D In - 6.948 - | ||||
| ======================================================================================================================= | ||||
| Total path delay (propagation time + setup) of 7.487 is 5.051(67.5%) logic and 2.436(32.5%) route. | ||||
| Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
| ==================================== | ||||
| Detailed Report for Clock: leon3mp|lclk_inferred_clock | ||||
| ==================================== | ||||
| Starting Points with Worst Slack | ||||
| ******************************** | ||||
| Starting Arrival | ||||
| Instance Reference Type Pin Net Time Slack | ||||
| Clock | ||||
| -------------------------------------------------------------------------------------------------------------------------------- | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_3 leon3mp|lclk_inferred_clock DFN1E0 Q ldbp1_3 0.693 -15.964 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 leon3mp|lclk_inferred_clock DFN1E0 Q ldbp1 0.693 -15.762 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[0] leon3mp|lclk_inferred_clock DFN1E1 Q data_0[0] 0.693 -15.749 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 leon3mp|lclk_inferred_clock DFN1E0 Q ldbp1_4 0.693 -15.701 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[9] leon3mp|lclk_inferred_clock DFN1E1 Q data_0_0[9] 0.693 -15.670 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[8] leon3mp|lclk_inferred_clock DFN1E1 Q data_0[8] 0.693 -15.668 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_5 leon3mp|lclk_inferred_clock DFN1E0 Q ldbp1_5 0.693 -15.650 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[1] leon3mp|lclk_inferred_clock DFN1E1 Q data_0[1] 0.693 -15.614 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[7] leon3mp|lclk_inferred_clock DFN1E1 Q data_0[7] 0.693 -15.563 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1[9] leon3mp|lclk_inferred_clock DFN1E0 Q op1[9] 0.693 -15.562 | ||||
| ================================================================================================================================ | ||||
| Ending Points with Worst Slack | ||||
| ****************************** | ||||
| Starting Required | ||||
| Instance Reference Type Pin Net Time Slack | ||||
| Clock | ||||
| ---------------------------------------------------------------------------------------------------------------------------------------------- | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] leon3mp|lclk_inferred_clock DFN1 D N_26 9.493 -15.964 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.burst leon3mp|lclk_inferred_clock DFN1 D burst_RNO_0 9.460 -15.504 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.req leon3mp|lclk_inferred_clock DFN1 D req_RNO_0 9.493 -15.332 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate[3] leon3mp|lclk_inferred_clock DFN1 D dstate_nss[2] 9.460 -15.271 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.stpend leon3mp|lclk_inferred_clock DFN1 D stpend_RNO 9.493 -15.267 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[0] leon3mp|lclk_inferred_clock DFN1E0 D valid_0_1[0] 9.460 -15.215 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[1] leon3mp|lclk_inferred_clock DFN1E0 D valid_0_1[1] 9.460 -15.215 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[2] leon3mp|lclk_inferred_clock DFN1E0 D valid_0_1[2] 9.460 -15.215 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[3] leon3mp|lclk_inferred_clock DFN1E0 D valid_0_1[3] 9.460 -15.215 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate[2] leon3mp|lclk_inferred_clock DFN1 D dstate_nss[3] 9.493 -15.100 | ||||
| ============================================================================================================================================== | ||||
| Worst Path Information | ||||
| *********************** | ||||
| Path information for path number 1: | ||||
| Requested Period: 10.000 | ||||
| - Setup time: 0.507 | ||||
| + Clock delay at ending point: 0.000 (ideal) | ||||
| = Required time: 9.493 | ||||
| - Propagation time: 25.458 | ||||
| - Clock delay at starting point: 0.000 (ideal) | ||||
| = Slack (critical) : -15.964 | ||||
| Number of logic level(s): 23 | ||||
| Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_3 / Q | ||||
| Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] / D | ||||
| The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| Instance / Net Pin Pin Arrival No. of | ||||
| Name Type Name Dir Delay Time Fan Out(s) | ||||
| ---------------------------------------------------------------------------------------------------------------------------------- | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_3 DFN1E0 Q Out 0.693 0.693 - | ||||
| ldbp1_3 Net - - 1.537 - 23 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIONO8[9] MX2 S In - 2.230 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIONO8[9] MX2 Y Out 0.373 2.603 - | ||||
| op1_RNIONO8[9] Net - - 1.285 - 13 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I10_P0N OR2 A In - 3.887 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I10_P0N OR2 Y Out 0.477 4.365 - | ||||
| N425_0 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I74_Y NOR2B B In - 4.873 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I74_Y NOR2B Y Out 0.590 5.463 - | ||||
| N533_1 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I136_Y OR2B B In - 5.972 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I136_Y OR2B Y Out 0.590 6.562 - | ||||
| N599_2 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I196_Y NOR3B C In - 7.071 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I196_Y NOR3B Y Out 0.338 7.409 - | ||||
| N665_1 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_un1_Y NOR2B A In - 7.652 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_un1_Y NOR2B Y Out 0.484 8.136 - | ||||
| I247_un1_Y Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_Y OR2 B In - 8.339 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_Y OR2 Y Out 0.608 8.947 - | ||||
| N808 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_un1_Y OR3C C In - 9.456 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_un1_Y OR3C Y Out 0.603 10.059 - | ||||
| I263_un1_Y Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_Y NAND2 A In - 10.262 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_Y NAND2 Y Out 0.460 10.722 - | ||||
| N772 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I318_Y_0 XNOR2 A In - 10.925 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I318_Y_0 XNOR2 Y Out 0.460 11.384 - | ||||
| un6_ex_add_res_s1_i[28] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI0O29E4 MX2C A In - 11.587 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI0O29E4 MX2C Y Out 0.535 12.121 - | ||||
| eaddress[27] Net - - 0.746 - 4 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI3M0HLA NOR3 C In - 12.868 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI3M0HLA NOR3 Y Out 0.706 13.574 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_15 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIJ1NQAL NOR3B B In - 13.777 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIJ1NQAL NOR3B Y Out 0.587 14.364 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_19 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B B In - 14.567 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B Y Out 0.587 15.154 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_22 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B A In - 15.357 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B Y Out 0.460 15.816 - | ||||
| un1_nullify_0_sqmuxa_2_a0_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A C In - 16.714 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A Y Out 0.674 17.387 - | ||||
| ldbp2_1_RNI7LHBO92 Net - - 1.484 - 20 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A B In - 18.872 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A Y Out 0.484 19.355 - | ||||
| flush_0tt_N_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B B In - 20.253 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B Y Out 0.486 20.739 - | ||||
| flush_0_sqmuxa_2_tz Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A B In - 20.942 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A Y Out 0.363 21.305 - | ||||
| flush_0_sqmuxa_2 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 A In - 21.548 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 Y Out 0.477 22.025 - | ||||
| flush_0_sqmuxa_0 Net - - 1.034 - 8 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B B In - 23.059 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B Y Out 0.590 23.649 - | ||||
| N_64 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A C In - 23.852 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A Y Out 0.706 24.558 - | ||||
| ics_0_i_1[1] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C C In - 24.761 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C Y Out 0.494 25.255 - | ||||
| N_26 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] DFN1 D In - 25.458 - | ||||
| ================================================================================================================================== | ||||
| Total path delay (propagation time + setup) of 25.965 is 13.333(51.4%) logic and 12.632(48.6%) route. | ||||
| Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
| Path information for path number 2: | ||||
| Requested Period: 10.000 | ||||
| - Setup time: 0.507 | ||||
| + Clock delay at ending point: 0.000 (ideal) | ||||
| = Required time: 9.493 | ||||
| - Propagation time: 25.456 | ||||
| - Clock delay at starting point: 0.000 (ideal) | ||||
| = Slack (non-critical) : -15.962 | ||||
| Number of logic level(s): 23 | ||||
| Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_3 / Q | ||||
| Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] / D | ||||
| The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| Instance / Net Pin Pin Arrival No. of | ||||
| Name Type Name Dir Delay Time Fan Out(s) | ||||
| ---------------------------------------------------------------------------------------------------------------------------------- | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_3 DFN1E0 Q Out 0.693 0.693 - | ||||
| ldbp1_3 Net - - 1.537 - 23 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIMJO8[8] MX2 S In - 2.230 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIMJO8[8] MX2 Y Out 0.373 2.603 - | ||||
| op1_RNIMJO8[8] Net - - 1.257 - 12 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I9_P0N OR2 A In - 3.860 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I9_P0N OR2 Y Out 0.477 4.337 - | ||||
| N422_0 Net - - 0.746 - 4 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I78_Y NOR2B A In - 5.084 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I78_Y NOR2B Y Out 0.484 5.568 - | ||||
| N537_2 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I136_Y OR2B A In - 6.076 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I136_Y OR2B Y Out 0.484 6.560 - | ||||
| N599_2 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I196_Y NOR3B C In - 7.069 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I196_Y NOR3B Y Out 0.338 7.407 - | ||||
| N665_1 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_un1_Y NOR2B A In - 7.650 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_un1_Y NOR2B Y Out 0.484 8.134 - | ||||
| I247_un1_Y Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_Y OR2 B In - 8.337 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_Y OR2 Y Out 0.608 8.945 - | ||||
| N808 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_un1_Y OR3C C In - 9.454 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_un1_Y OR3C Y Out 0.603 10.057 - | ||||
| I263_un1_Y Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_Y NAND2 A In - 10.260 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_Y NAND2 Y Out 0.460 10.720 - | ||||
| N772 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I318_Y_0 XNOR2 A In - 10.922 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I318_Y_0 XNOR2 Y Out 0.460 11.382 - | ||||
| un6_ex_add_res_s1_i[28] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI0O29E4 MX2C A In - 11.585 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI0O29E4 MX2C Y Out 0.535 12.119 - | ||||
| eaddress[27] Net - - 0.746 - 4 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI3M0HLA NOR3 C In - 12.866 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI3M0HLA NOR3 Y Out 0.706 13.572 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_15 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIJ1NQAL NOR3B B In - 13.775 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIJ1NQAL NOR3B Y Out 0.587 14.362 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_19 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B B In - 14.565 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B Y Out 0.587 15.152 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_22 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B A In - 15.355 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B Y Out 0.460 15.814 - | ||||
| un1_nullify_0_sqmuxa_2_a0_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A C In - 16.712 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A Y Out 0.674 17.385 - | ||||
| ldbp2_1_RNI7LHBO92 Net - - 1.484 - 20 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A B In - 18.869 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A Y Out 0.484 19.353 - | ||||
| flush_0tt_N_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B B In - 20.251 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B Y Out 0.486 20.737 - | ||||
| flush_0_sqmuxa_2_tz Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A B In - 20.939 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A Y Out 0.363 21.302 - | ||||
| flush_0_sqmuxa_2 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 A In - 21.546 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 Y Out 0.477 22.023 - | ||||
| flush_0_sqmuxa_0 Net - - 1.034 - 8 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B B In - 23.057 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B Y Out 0.590 23.647 - | ||||
| N_64 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A C In - 23.850 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A Y Out 0.706 24.556 - | ||||
| ics_0_i_1[1] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C C In - 24.759 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C Y Out 0.494 25.253 - | ||||
| N_26 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] DFN1 D In - 25.456 - | ||||
| ================================================================================================================================== | ||||
| Total path delay (propagation time + setup) of 25.962 is 13.120(50.5%) logic and 12.842(49.5%) route. | ||||
| Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
| Path information for path number 3: | ||||
| Requested Period: 10.000 | ||||
| - Setup time: 0.507 | ||||
| + Clock delay at ending point: 0.000 (ideal) | ||||
| = Required time: 9.493 | ||||
| - Propagation time: 25.255 | ||||
| - Clock delay at starting point: 0.000 (ideal) | ||||
| = Slack (non-critical) : -15.762 | ||||
| Number of logic level(s): 22 | ||||
| Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 / Q | ||||
| Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] / D | ||||
| The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| Instance / Net Pin Pin Arrival No. of | ||||
| Name Type Name Dir Delay Time Fan Out(s) | ||||
| --------------------------------------------------------------------------------------------------------------------------------------- | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 DFN1E0 Q Out 0.693 0.693 - | ||||
| ldbp1 Net - - 1.519 - 22 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI2VA4[0] MX2 S In - 2.212 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI2VA4[0] MX2 Y Out 0.373 2.585 - | ||||
| un1_iu0_6[0] Net - - 1.285 - 13 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I91_un1_Y_0 NOR2B B In - 3.870 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I91_un1_Y_0 NOR2B Y Out 0.590 4.460 - | ||||
| ADD_33x33_fast_I91_un1_Y_0 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1_0 MIN3 C In - 4.663 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1_0 MIN3 Y Out 0.664 5.327 - | ||||
| ADD_33x33_fast_I206_Y_0_o3_1_0 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2B A In - 5.529 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2B Y Out 0.460 5.989 - | ||||
| N616_0 Net - - 0.746 - 4 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR3C C In - 6.735 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR3C Y Out 0.603 7.339 - | ||||
| I204_un1_Y_0 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR3B C In - 7.542 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR3B Y Out 0.706 8.248 - | ||||
| N674 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I244_un1_Y AND2 B In - 8.757 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I244_un1_Y AND2 Y Out 0.590 9.347 - | ||||
| I244_un1_Y_0 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I244_Y OR2 A In - 9.550 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I244_Y OR2 Y Out 0.477 10.027 - | ||||
| N799_1 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I260_un1_Y OR3B B In - 10.270 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I260_un1_Y OR3B Y Out 0.571 10.841 - | ||||
| I260_un1_Y_1 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I321_Y_0 AX1C A In - 11.044 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I321_Y_0 AX1C Y Out 0.888 11.932 - | ||||
| un6_ex_add_res_s1_i[31] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIIIKJ45 MX2C A In - 12.134 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIIIKJ45 MX2C Y Out 0.535 12.669 - | ||||
| eaddress[30] Net - - 0.746 - 4 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIT92NSC NOR3 C In - 13.416 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIT92NSC NOR3 Y Out 0.706 14.122 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_16 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B A In - 14.325 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B Y Out 0.626 14.951 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_22 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B A In - 15.154 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B Y Out 0.460 15.613 - | ||||
| un1_nullify_0_sqmuxa_2_a0_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A C In - 16.511 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A Y Out 0.674 17.185 - | ||||
| ldbp2_1_RNI7LHBO92 Net - - 1.484 - 20 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A B In - 18.669 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A Y Out 0.484 19.153 - | ||||
| flush_0tt_N_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B B In - 20.050 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B Y Out 0.486 20.536 - | ||||
| flush_0_sqmuxa_2_tz Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A B In - 20.738 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A Y Out 0.363 21.102 - | ||||
| flush_0_sqmuxa_2 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 A In - 21.345 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 Y Out 0.477 21.822 - | ||||
| flush_0_sqmuxa_0 Net - - 1.034 - 8 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B B In - 22.856 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B Y Out 0.590 23.446 - | ||||
| N_64 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A C In - 23.649 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A Y Out 0.706 24.355 - | ||||
| ics_0_i_1[1] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C C In - 24.558 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C Y Out 0.494 25.052 - | ||||
| N_26 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] DFN1 D In - 25.255 - | ||||
| ======================================================================================================================================= | ||||
| Total path delay (propagation time + setup) of 25.761 is 13.724(53.3%) logic and 12.038(46.7%) route. | ||||
| Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
| Path information for path number 4: | ||||
| Requested Period: 10.000 | ||||
| - Setup time: 0.507 | ||||
| + Clock delay at ending point: 0.000 (ideal) | ||||
| = Required time: 9.493 | ||||
| - Propagation time: 25.247 | ||||
| - Clock delay at starting point: 0.000 (ideal) | ||||
| = Slack (non-critical) : -15.754 | ||||
| Number of logic level(s): 23 | ||||
| Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_3 / Q | ||||
| Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] / D | ||||
| The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| Instance / Net Pin Pin Arrival No. of | ||||
| Name Type Name Dir Delay Time Fan Out(s) | ||||
| ---------------------------------------------------------------------------------------------------------------------------------- | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_3 DFN1E0 Q Out 0.693 0.693 - | ||||
| ldbp1_3 Net - - 1.537 - 23 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIMJO8[8] MX2 S In - 2.230 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIMJO8[8] MX2 Y Out 0.373 2.603 - | ||||
| op1_RNIMJO8[8] Net - - 1.257 - 12 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I9_P0N OR2 A In - 3.860 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I9_P0N OR2 Y Out 0.477 4.337 - | ||||
| N422_0 Net - - 0.746 - 4 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I77_un1_Y NOR3C C In - 5.084 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I77_un1_Y NOR3C Y Out 0.603 5.687 - | ||||
| I77_un1_Y Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I77_Y OR2 B In - 5.890 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I77_Y OR2 Y Out 0.608 6.498 - | ||||
| N536_1 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I135_Y AO1 A In - 6.741 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I135_Y AO1 Y Out 0.437 7.178 - | ||||
| N598_2 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I195_Y AO1A C In - 7.421 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I195_Y AO1A Y Out 0.595 8.017 - | ||||
| N664 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_Y OR2 A In - 8.260 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I247_Y OR2 Y Out 0.477 8.737 - | ||||
| N808 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_un1_Y OR3C C In - 9.246 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_un1_Y OR3C Y Out 0.603 9.849 - | ||||
| I263_un1_Y Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_Y NAND2 A In - 10.052 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I263_Y NAND2 Y Out 0.460 10.511 - | ||||
| N772 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I318_Y_0 XNOR2 A In - 10.714 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I318_Y_0 XNOR2 Y Out 0.460 11.174 - | ||||
| un6_ex_add_res_s1_i[28] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI0O29E4 MX2C A In - 11.377 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI0O29E4 MX2C Y Out 0.535 11.911 - | ||||
| eaddress[27] Net - - 0.746 - 4 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI3M0HLA NOR3 C In - 12.658 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI3M0HLA NOR3 Y Out 0.706 13.364 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_15 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIJ1NQAL NOR3B B In - 13.567 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIJ1NQAL NOR3B Y Out 0.587 14.154 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_19 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B B In - 14.357 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B Y Out 0.587 14.944 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_22 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B A In - 15.146 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B Y Out 0.460 15.606 - | ||||
| un1_nullify_0_sqmuxa_2_a0_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A C In - 16.503 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A Y Out 0.674 17.177 - | ||||
| ldbp2_1_RNI7LHBO92 Net - - 1.484 - 20 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A B In - 18.661 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A Y Out 0.484 19.145 - | ||||
| flush_0tt_N_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B B In - 20.043 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B Y Out 0.486 20.528 - | ||||
| flush_0_sqmuxa_2_tz Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A B In - 20.731 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A Y Out 0.363 21.094 - | ||||
| flush_0_sqmuxa_2 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 A In - 21.337 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 Y Out 0.477 21.815 - | ||||
| flush_0_sqmuxa_0 Net - - 1.034 - 8 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B B In - 22.848 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B Y Out 0.590 23.439 - | ||||
| N_64 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A C In - 23.642 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A Y Out 0.706 24.348 - | ||||
| ics_0_i_1[1] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C C In - 24.551 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C Y Out 0.494 25.044 - | ||||
| N_26 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] DFN1 D In - 25.247 - | ||||
| ================================================================================================================================== | ||||
| Total path delay (propagation time + setup) of 25.754 is 13.442(52.2%) logic and 12.312(47.8%) route. | ||||
| Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
| Path information for path number 5: | ||||
| Requested Period: 10.000 | ||||
| - Setup time: 0.507 | ||||
| + Clock delay at ending point: 0.000 (ideal) | ||||
| = Required time: 9.493 | ||||
| - Propagation time: 25.242 | ||||
| - Clock delay at starting point: 0.000 (ideal) | ||||
| = Slack (non-critical) : -15.749 | ||||
| Number of logic level(s): 22 | ||||
| Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[0] / Q | ||||
| Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] / D | ||||
| The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
| Instance / Net Pin Pin Arrival No. of | ||||
| Name Type Name Dir Delay Time Fan Out(s) | ||||
| --------------------------------------------------------------------------------------------------------------------------------------- | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[0] DFN1E1 Q Out 0.693 0.693 - | ||||
| data_0[0] Net - - 1.341 - 15 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI2VA4[0] MX2 B In - 2.035 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI2VA4[0] MX2 Y Out 0.538 2.573 - | ||||
| un1_iu0_6[0] Net - - 1.285 - 13 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I91_un1_Y_0 NOR2B B In - 3.857 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I91_un1_Y_0 NOR2B Y Out 0.590 4.447 - | ||||
| ADD_33x33_fast_I91_un1_Y_0 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1_0 MIN3 C In - 4.650 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1_0 MIN3 Y Out 0.664 5.314 - | ||||
| ADD_33x33_fast_I206_Y_0_o3_1_0 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2B A In - 5.517 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2B Y Out 0.460 5.976 - | ||||
| N616_0 Net - - 0.746 - 4 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR3C C In - 6.723 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR3C Y Out 0.603 7.326 - | ||||
| I204_un1_Y_0 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR3B C In - 7.529 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR3B Y Out 0.706 8.236 - | ||||
| N674 Net - - 0.508 - 3 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I244_un1_Y AND2 B In - 8.744 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I244_un1_Y AND2 Y Out 0.590 9.334 - | ||||
| I244_un1_Y_0 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I244_Y OR2 A In - 9.537 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I244_Y OR2 Y Out 0.477 10.015 - | ||||
| N799_1 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I260_un1_Y OR3B B In - 10.258 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I260_un1_Y OR3B Y Out 0.571 10.828 - | ||||
| I260_un1_Y_1 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I321_Y_0 AX1C A In - 11.031 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I321_Y_0 AX1C Y Out 0.888 11.919 - | ||||
| un6_ex_add_res_s1_i[31] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIIIKJ45 MX2C A In - 12.122 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIIIKJ45 MX2C Y Out 0.535 12.657 - | ||||
| eaddress[30] Net - - 0.746 - 4 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIT92NSC NOR3 C In - 13.403 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIT92NSC NOR3 Y Out 0.706 14.109 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_16 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B A In - 14.312 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIBH3T461 NOR3B Y Out 0.626 14.938 - | ||||
| nullify_1_sqmuxa_2_m6_0_a3_0_1_22 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B A In - 15.141 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIEBCLTP1 OR2B Y Out 0.460 15.601 - | ||||
| un1_nullify_0_sqmuxa_2_a0_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A C In - 16.498 - | ||||
| l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI7LHBO92 NOR3A Y Out 0.674 17.172 - | ||||
| ldbp2_1_RNI7LHBO92 Net - - 1.484 - 20 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A B In - 18.656 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.dwrite_1_ivtt_m2_0_a3 OR2A Y Out 0.484 19.140 - | ||||
| flush_0tt_N_4 Net - - 0.898 - 6 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B B In - 20.038 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3_tz NOR2B Y Out 0.486 20.523 - | ||||
| flush_0_sqmuxa_2_tz Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A B In - 20.726 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.flush_0_sqmuxa_3 NOR2A Y Out 0.363 21.089 - | ||||
| flush_0_sqmuxa_2 Net - - 0.243 - 2 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 A In - 21.332 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNI9ITC533[2] OR2 Y Out 0.477 21.810 - | ||||
| flush_0_sqmuxa_0 Net - - 1.034 - 8 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B B In - 22.843 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_2[1] NOR2B Y Out 0.590 23.433 - | ||||
| N_64 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A C In - 23.636 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO_0[1] OR3A Y Out 0.706 24.343 - | ||||
| ics_0_i_1[1] Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C C In - 24.546 - | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics_RNO[1] OA1C Y Out 0.494 25.039 - | ||||
| N_26 Net - - 0.203 - 1 | ||||
| l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.cctrl\.ics[1] DFN1 D In - 25.242 - | ||||
| ======================================================================================================================================= | ||||
| Total path delay (propagation time + setup) of 25.749 is 13.889(53.9%) logic and 11.860(46.1%) route. | ||||
| Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
| ##### END OF TIMING REPORT #####] | ||||
| -------------------------------------------------------------------------------- | ||||
| Target Part: A3PE3000L_PQFP208_-1 | ||||
| Report for cell leon3mp.behavioral | ||||
| Core Cell usage: | ||||
| cell count area count*area | ||||
| AND2 1306 1.0 1306.0 | ||||
| AND2A 17 1.0 17.0 | ||||
| AND3 639 1.0 639.0 | ||||
| AND3A 1 1.0 1.0 | ||||
| AO1 545 1.0 545.0 | ||||
| AO13 96 1.0 96.0 | ||||
| AO14 2 1.0 2.0 | ||||
| AO15 1 1.0 1.0 | ||||
| AO16 6 1.0 6.0 | ||||
| AO17 3 1.0 3.0 | ||||
| AO18 68 1.0 68.0 | ||||
| AO1A 166 1.0 166.0 | ||||
| AO1B 262 1.0 262.0 | ||||
| AO1C 126 1.0 126.0 | ||||
| AO1D 120 1.0 120.0 | ||||
| AOI1 153 1.0 153.0 | ||||
| AOI1A 8 1.0 8.0 | ||||
| AOI1B 685 1.0 685.0 | ||||
| AX1 18 1.0 18.0 | ||||
| AX1A 30 1.0 30.0 | ||||
| AX1B 17 1.0 17.0 | ||||
| AX1C 32 1.0 32.0 | ||||
| AX1D 63 1.0 63.0 | ||||
| AX1E 38 1.0 38.0 | ||||
| AXO1 1 1.0 1.0 | ||||
| AXO2 4 1.0 4.0 | ||||
| AXO3 4 1.0 4.0 | ||||
| AXO5 7 1.0 7.0 | ||||
| AXO6 1 1.0 1.0 | ||||
| AXO7 3 1.0 3.0 | ||||
| AXOI1 3 1.0 3.0 | ||||
| AXOI2 1 1.0 1.0 | ||||
| AXOI3 3 1.0 3.0 | ||||
| AXOI4 7 1.0 7.0 | ||||
| AXOI5 9 1.0 9.0 | ||||
| AXOI7 1 1.0 1.0 | ||||
| BUFF 230 1.0 230.0 | ||||
| CLKINT 6 0.0 0.0 | ||||
| GND 263 0.0 0.0 | ||||
| INV 115 1.0 115.0 | ||||
| MAJ3 652 1.0 652.0 | ||||
| MAJ3X 3 1.0 3.0 | ||||
| MIN3 79 1.0 79.0 | ||||
| MIN3X 1 1.0 1.0 | ||||
| MX2 2867 1.0 2867.0 | ||||
| MX2A 262 1.0 262.0 | ||||
| MX2B 163 1.0 163.0 | ||||
| MX2C 1654 1.0 1654.0 | ||||
| NAND2 113 1.0 113.0 | ||||
| NOR2 870 1.0 870.0 | ||||
| NOR2A 918 1.0 918.0 | ||||
| NOR2B 1346 1.0 1346.0 | ||||
| NOR3 264 1.0 264.0 | ||||
| NOR3A 360 1.0 360.0 | ||||
| NOR3B 324 1.0 324.0 | ||||
| NOR3C 858 1.0 858.0 | ||||
| OA1 182 1.0 182.0 | ||||
| OA1A 278 1.0 278.0 | ||||
| OA1B 74 1.0 74.0 | ||||
| OA1C 123 1.0 123.0 | ||||
| OAI1 130 1.0 130.0 | ||||
| OR2 622 1.0 622.0 | ||||
| OR2A 1429 1.0 1429.0 | ||||
| OR2B 2295 1.0 2295.0 | ||||
| OR3 326 1.0 326.0 | ||||
| OR3A 177 1.0 177.0 | ||||
| OR3B 214 1.0 214.0 | ||||
| OR3C 565 1.0 565.0 | ||||
| VCC 263 0.0 0.0 | ||||
| XA1 75 1.0 75.0 | ||||
| XA1A 272 1.0 272.0 | ||||
| XA1B 104 1.0 104.0 | ||||
| XA1C 47 1.0 47.0 | ||||
| XAI1 17 1.0 17.0 | ||||
| XAI1A 12 1.0 12.0 | ||||
| XNOR2 785 1.0 785.0 | ||||
| XNOR3 174 1.0 174.0 | ||||
| XO1 8 1.0 8.0 | ||||
| XO1A 9 1.0 9.0 | ||||
| XOR2 2057 1.0 2057.0 | ||||
| XOR3 634 1.0 634.0 | ||||
| ZOR3 1 1.0 1.0 | ||||
| DFN1 3073 1.0 3073.0 | ||||
| DFN1C0 337 1.0 337.0 | ||||
| DFN1C1 75 1.0 75.0 | ||||
| DFN1E0 1327 1.0 1327.0 | ||||
| DFN1E0C0 141 1.0 141.0 | ||||
| DFN1E0C1 87 1.0 87.0 | ||||
| DFN1E0P0 23 1.0 23.0 | ||||
| DFN1E0P1 9 1.0 9.0 | ||||
| DFN1E1 629 1.0 629.0 | ||||
| DFN1E1C0 1393 1.0 1393.0 | ||||
| DFN1E1C1 39 1.0 39.0 | ||||
| DFN1E1P0 23 1.0 23.0 | ||||
| DFN1E1P1 2 1.0 2.0 | ||||
| DFN1P0 37 1.0 37.0 | ||||
| DFN1P1 9 1.0 9.0 | ||||
| DFN1P1C1 19 4.0 76.0 | ||||
| DLN1 85 1.0 85.0 | ||||
| DLN1P1C1 1 2.0 2.0 | ||||
| RAM4K9 16 0.0 0.0 | ||||
| RAM512X18 53 0.0 0.0 | ||||
| ----- ---------- | ||||
| TOTAL 34045 33502.0 | ||||
| IO Cell usage: | ||||
| cell count | ||||
| BIBUF 39 | ||||
| INBUF 13 | ||||
| OUTBUF 56 | ||||
| ----- | ||||
| TOTAL 108 | ||||
| Core Cells : 33502 of 75264 (45%) | ||||
| IO Cells : 108 | ||||
| RAM/ROM Usage Summary | ||||
| Block Rams : 69 of 112 (61%) | ||||
| Mapper successful! | ||||
| Process took 0h:03m:06s realtime, 0h:03m:05s cputime | ||||
| # Thu Dec 19 12:52:06 2013 | ||||
| ###########################################################] | ||||