leon3mp_synplify_win32.npl
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r80 | JDF G | ||
PROJECT leon3mp | ||||
DESIGN leon3mp | ||||
DEVFAM PROASIC3 | ||||
DEVICE PROASIC3 | ||||
DEVSPEED Std | ||||
DEVPKG "" | ||||
DEVTOPLEVELMODULETYPE EDIF | ||||
DEVSIMULATOR Modelsim | ||||
DEVGENERATEDSIMULATIONMODEL VHDL | ||||
SOURCE synplify\leon3mp.edf | ||||
DEPASSOC leon3mp ..\..\boards\Projet-Blanc-LPP-M7A3P1000\leon3mp.ucf | ||||
[Normal] | ||||
xilxMapAllowLogicOpt=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True | ||||
xilxMapCoverMode=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Speed | ||||
xilxNgdbld_AUL=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True | ||||
xilxPAReffortLevel=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Medium | ||||
xilxNgdbldMacro=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1105378344, ..\..\netlists\xilinx\PROASIC3 | ||||