HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · boards/LFR-EQM/Makefile.inc

Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...

Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards Renamed LFR-em-WFP_MS designs in SOLO_LFR_LFR-EM designs Updated LFR-EM boards constraints => PDC file => SDC file for the place and route Updated SOLO_LFR_LFR-EM designs => added DATA_SHAPING_SATURATION in LPP_FILTER => changed boards number : LPP_LFR_BOARD_LFR_EM & X"015B"

pellion - - Load All Authors

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r569:64f72d322da8 JC


                r662:f19abbf47ea7

SOLO_LFR_01-5B (LFR-EM) default

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             Makefile.inc
        
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        pellion
    
LFR-EQM-2.1.63

              r545
            
      PACKAGE=\"\"

      SPEED=Std

      SYNFREQ=50

        pellion
    
EQM debug

              r569
            
      TECHNOLOGY=ProASIC3L

      LIBERO_DIE=A3PE3000L

      PART=A3PE3000L

        pellion
    
LFR-EQM-2.1.63

              r545
            
      DESIGNER_VOLTAGE=COM

      DESIGNER_TEMP=COM

      DESIGNER_PACKAGE=FBGA

      DESIGNER_PINS=324

      MANUFACTURER=Actel

        pellion
    
EQM debug

              r569
            
      MGCTECHNOLOGY=ProASIC3L

        pellion
    
LFR-EQM-2.1.63

              r545
            
      MGCPART=$(PART)

      MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}

      LIBERO_PACKAGE=fg$(DESIGNER_PINS)

        pellion
    
EQM debug

              r569

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pellion LFR-EQM-2.1.63	r545	PACKAGE=\"\"
		SPEED=Std
		SYNFREQ=50

pellion EQM debug	r569	TECHNOLOGY=ProASIC3L
		LIBERO_DIE=A3PE3000L
		PART=A3PE3000L
pellion LFR-EQM-2.1.63	r545
		DESIGNER_VOLTAGE=COM
		DESIGNER_TEMP=COM
		DESIGNER_PACKAGE=FBGA
		DESIGNER_PINS=324

		MANUFACTURER=Actel
pellion EQM debug	r569	MGCTECHNOLOGY=ProASIC3L
pellion LFR-EQM-2.1.63	r545	MGCPART=$(PART)
		MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
		LIBERO_PACKAGE=fg$(DESIGNER_PINS)

pellion EQM debug	r569