HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · boards/LFR-EM/Makefile.inc

Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...

Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards Renamed LFR-em-WFP_MS designs in SOLO_LFR_LFR-EM designs Updated LFR-EM boards constraints => PDC file => SDC file for the place and route Updated SOLO_LFR_LFR-EM designs => added DATA_SHAPING_SATURATION in LPP_FILTER => changed boards number : LPP_LFR_BOARD_LFR_EM & X"015B"

Alexis Jeandet - - Load All Authors

File last commit:

r662:f19abbf47ea7 SOLO_LFR_01-5B (LFR-EM) default


                r662:f19abbf47ea7

SOLO_LFR_01-5B (LFR-EM) default

Download file

             Makefile.inc
        
                    19 lines
            
             | 316 B
            
                | text/x-povray
            
             |
                MakefileLexer
            
             / boards / LFR-EM / Makefile.inc
          
                    History
                
                 |
                  Source
                 | Raw
                 |Copy content
                 |Copy permalink

        Alexis Jeandet
    
Sync

              r181
            
      PACKAGE=\"\"

      SPEED=Std

      SYNFREQ=50

        Alexis Jeandet
    
Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...

              r662
            
      TECHNOLOGY=ProASIC3E

      LIBERO_DIE=IT14X14M4

      PART=A3PE3000

      DESIGNER_VOLTAGE=COM

      DESIGNER_TEMP=COM

        Alexis Jeandet
    
Sync

              r181
            
      DESIGNER_PACKAGE=FBGA

      DESIGNER_PINS=324

      MANUFACTURER=Actel

        Alexis Jeandet
    
Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...

              r662
            
      MGCTECHNOLOGY=Proasic3

        Alexis Jeandet
    
Sync

              r181
            
      MGCPART=$(PART)

      MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}

      LIBERO_PACKAGE=fg$(DESIGNER_PINS)

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

Alexis Jeandet Sync	r181	PACKAGE=\"\"
		SPEED=Std
		SYNFREQ=50

Alexis Jeandet Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...	r662	TECHNOLOGY=ProASIC3E
		LIBERO_DIE=IT14X14M4
		PART=A3PE3000

		DESIGNER_VOLTAGE=COM
		DESIGNER_TEMP=COM
Alexis Jeandet Sync	r181	DESIGNER_PACKAGE=FBGA
		DESIGNER_PINS=324

		MANUFACTURER=Actel
Alexis Jeandet Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...	r662	MGCTECHNOLOGY=Proasic3
Alexis Jeandet Sync	r181	MGCPART=$(PART)
		MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
		LIBERO_PACKAGE=fg$(DESIGNER_PINS)