general_counter.vhd
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r330 | LIBRARY IEEE; | ||
USE IEEE.STD_LOGIC_1164.ALL; | ||||
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r547 | USE IEEE.NUMERIC_STD.ALL; | ||
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r330 | |||
ENTITY general_counter IS | ||||
GENERIC ( | ||||
CYCLIC : STD_LOGIC := '1'; | ||||
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r547 | NB_BITS_COUNTER : INTEGER := 9; | ||
RST_VALUE : INTEGER := 0 | ||||
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r330 | ); | ||
PORT ( | ||||
clk : IN STD_LOGIC; | ||||
rstn : IN STD_LOGIC; | ||||
-- | ||||
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r547 | MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1'); | ||
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r330 | -- | ||
set : IN STD_LOGIC; | ||||
set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); | ||||
add1 : IN STD_LOGIC; | ||||
counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) | ||||
); | ||||
END general_counter; | ||||
ARCHITECTURE beh OF general_counter IS | ||||
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r547 | CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER)); | ||
SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); | ||||
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r330 | |||
BEGIN -- beh | ||||
PROCESS (clk, rstn) | ||||
BEGIN -- PROCESS | ||||
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r547 | IF rstn = '0' THEN -- asynchronous reset (active low) | ||
counter_s <= RST_VALUE_v; | ||||
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | ||||
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r330 | IF set = '1' THEN | ||
counter_s <= set_value; | ||||
ELSIF add1 = '1' THEN | ||||
IF counter_s < MAX_VALUE THEN | ||||
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r547 | counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1)); | ||
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r330 | ELSE | ||
IF CYCLIC = '1' THEN | ||||
counter_s <= (OTHERS => '0'); | ||||
END IF; | ||||
END IF; | ||||
END IF; | ||||
END IF; | ||||
END PROCESS; | ||||
counter <= counter_s; | ||||
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r547 | |||
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r330 | END beh; | ||