LFR_EM_synthesis.sdc
61 lines
| 748 B
| application/vnd.stardivision.calc
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TextLexer
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r421 | # Synplicity, Inc. constraint file | ||
# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc | ||||
# Written on Wed Aug 1 19:29:24 2007 | ||||
# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor | ||||
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# Collections | ||||
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# Clocks | ||||
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r561 | define_clock -name {clk100MHz} -freq 100 -clockgroup default_clkgroup_50 -route 5 | ||
define_clock -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_49 -route 5 | ||||
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r421 | |||
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# Clock to Clock | ||||
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# Inputs/Outputs | ||||
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# Registers | ||||
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# Multicycle Path | ||||
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# False Path | ||||
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r561 | set_false_path -from reset | ||
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r421 | # | ||
# Path Delay | ||||
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# Attributes | ||||
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r561 | |||
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r421 | define_global_attribute syn_useioff {1} | ||
define_global_attribute -disable syn_netlist_hierarchy {0} | ||||
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# I/O standards | ||||
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# Compile Points | ||||
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# Other Constraints | ||||
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