top_synplify.npl
20 lines
| 694 B
| text/plain
|
TextLexer
martin
|
r100 | JDF G | ||
PROJECT top | ||||
DESIGN top | ||||
DEVFAM PROASIC3 | ||||
DEVICE PROASIC3 | ||||
DEVSPEED Std | ||||
DEVPKG "" | ||||
DEVTOPLEVELMODULETYPE EDIF | ||||
DEVSIMULATOR Modelsim | ||||
DEVGENERATEDSIMULATIONMODEL VHDL | ||||
SOURCE synplify\top.edf | ||||
DEPASSOC top ..\..\boards\Projet-Blanc-M7A3P1K\top.ucf | ||||
[Normal] | ||||
xilxMapAllowLogicOpt=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True | ||||
xilxMapCoverMode=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Speed | ||||
xilxNgdbld_AUL=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True | ||||
xilxPAReffortLevel=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Medium | ||||
xilxNgdbldMacro=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1105378344, ..\..\netlists\xilinx\PROASIC3 | ||||
[STRATEGY-LIST] | ||||
Normal=True | ||||