lpp_cna.vhd
126 lines
| 4.3 KiB
| text/x-vhdl
|
VhdlLexer
martin
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r261 | ------------------------------------------------------------------------------ | ||
-- This file is a part of the LPP VHDL IP LIBRARY | ||||
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | ||||
-- | ||||
-- This program is free software; you can redistribute it and/or modify | ||||
-- it under the terms of the GNU General Public License as published by | ||||
-- the Free Software Foundation; either version 3 of the License, or | ||||
-- (at your option) any later version. | ||||
-- | ||||
-- This program is distributed in the hope that it will be useful, | ||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||||
-- GNU General Public License for more details. | ||||
-- | ||||
-- You should have received a copy of the GNU General Public License | ||||
-- along with this program; if not, write to the Free Software | ||||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||||
------------------------------------------------------------------------------ | ||||
-- Author : Martin Morlot | ||||
-- Mail : martin.morlot@lpp.polytechnique.fr | ||||
------------------------------------------------------------------------------ | ||||
library ieee; | ||||
use ieee.std_logic_1164.all; | ||||
library grlib; | ||||
use grlib.amba.all; | ||||
use std.textio.all; | ||||
library lpp; | ||||
use lpp.lpp_amba.all; | ||||
Jeandet Alexis
|
r271 | --! Package contenant tous les programmes qui forment le composant intgr dans le lon | ||
package lpp_cna is | ||||
TYPE CNA_16bit_T IS ARRAY(NATURAL RANGE <>,NATURAL RANGE <>) of std_logic; | ||||
martin
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r261 | |||
Jeandet Alexis
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r271 | component DAC8581 is | ||
generic( | ||||
clkfreq : integer := 100; | ||||
ChanCount : integer := 8 | ||||
); | ||||
Port ( clk : in STD_LOGIC; | ||||
rstn : in STD_LOGIC; | ||||
smpclk : in STD_LOGIC; | ||||
sclk : out STD_LOGIC; | ||||
csn : out STD_LOGIC; | ||||
sdo : out STD_LOGIC_VECTOR (ChanCount-1 downto 0); | ||||
smp_in : in CNA_16bit_T(ChanCount-1 downto 0,15 downto 0) | ||||
); | ||||
end component; | ||||
martin
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r261 | |||
component APB_DAC is | ||||
generic ( | ||||
pindex : integer := 0; | ||||
paddr : integer := 0; | ||||
pmask : integer := 16#fff#; | ||||
pirq : integer := 0; | ||||
martin
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r262 | abits : integer := 8; | ||
cpt_serial : integer := 6); | ||||
martin
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r261 | port ( | ||
clk : in std_logic; | ||||
rst : in std_logic; | ||||
apbi : in apb_slv_in_type; | ||||
apbo : out apb_slv_out_type; | ||||
martin
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r262 | DataIN : in std_logic_vector(15 downto 0); | ||
Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL | ||||
Readn : out std_logic; | ||||
SYNC : out std_logic; --! Signal de synchronisation du convertisseur | ||||
SCLK : out std_logic; --! Horloge systeme du convertisseur | ||||
martin
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r261 | DATA : out std_logic | ||
); | ||||
end component; | ||||
component DacDriver is | ||||
Jeandet Alexis
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r271 | generic(cpt_serial : integer := 6); --! Gnrique contenant le rsultat de la division clk/sclk !!! clk=25Mhz | ||
martin
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r261 | port( | ||
clk : in std_logic; | ||||
rst : in std_logic; | ||||
enable : in std_logic; | ||||
Jeandet Alexis
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r271 | Data_IN : in std_logic_vector(15 downto 0); --! Donne Numrique d'entre sur 16 bits | ||
martin
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r262 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur | ||
SCLK : out std_logic; --! Horloge systeme du convertisseur | ||||
Readn : out std_logic; | ||||
martin
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r261 | Ready : out std_logic; | ||
Data : out std_logic | ||||
); | ||||
end component; | ||||
component Systeme_Clock is | ||||
generic(N :integer := 695); | ||||
port( | ||||
clk, raz : in std_logic ; | ||||
sclk : out std_logic); | ||||
end component; | ||||
component Gene_SYNC is | ||||
port( | ||||
SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant | ||||
enable : in std_logic; --! Autorise ou non l'utilisation du composant | ||||
Jeandet Alexis
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r271 | Send : out std_logic; --! Flag, Autorise l'envoi (srialisation) d'une nouvelle donne | ||
SYNC : out std_logic); --! Signal de synchronisation du convertisseur gnr | ||||
martin
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r261 | end component; | ||
component Serialize is | ||||
port( | ||||
clk,raz : in std_logic; | ||||
sclk : in std_logic; | ||||
vectin : in std_logic_vector(15 downto 0); | ||||
send : in std_logic; | ||||
sended : out std_logic; | ||||
Data : out std_logic); | ||||
end component; | ||||
martin
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r262 | component ReadFifo_GEN is | ||
port( | ||||
clk,raz : in std_logic; --! Horloge et Reset du composant | ||||
SYNC : in std_logic; | ||||
Readn : out std_logic | ||||
); | ||||
end component; | ||||
Jeandet Alexis
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r271 | end; | ||