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debug lpp_uart and comment lpp_cna
debug lpp_uart and comment lpp_cna

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lpp_amba.vhd
82 lines | 2.5 KiB | text/x-vhdl | VhdlLexer
Alexis
aded GRLIB Automated patcher
r1 ------------------------------------------------------------------------------
-- This file is a part of the LPP VHDL IP LIBRARY
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
r19 -- the Free Software Foundation; either version 3 of the License, or
Alexis
aded GRLIB Automated patcher
r1 -- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
Alexis
Minor changes
r38 -- Author : Alexis Jeandet
-- Mail : alexis.jeandet@lpp.polytechnique.fr
----------------------------------------------------------------------------
Alexis
aded GRLIB Automated patcher
r1 library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use std.textio.all;
martin
APB_MULTI_DIODE added
r5
Alexis
aded GRLIB Automated patcher
r1
package lpp_amba is
yannic
Fixed Makefile (C drivers) for mingw users
r34 component APB_CHENILLARD is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
RegLed : in std_logic_vector (7 downto 0);
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
Leds : out std_logic_vector (7 downto 0)
);
end component;
Alexis
aded GRLIB Automated patcher
r1
component APB_SIMPLE_DIODE is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
LED : out std_ulogic
);
end component;
martin
APB_MULTI_DIODE added
r5 component APB_MULTI_DIODE is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
LED : out std_logic_vector(2 downto 0)
);
end component;
Alexis
aded GRLIB Automated patcher
r1 end;