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debug lpp_uart and comment lpp_cna
debug lpp_uart and comment lpp_cna
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IIR_CEL_FILTER.vhd
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/ lib / lpp / dsp / iir_filter / IIR_CEL_FILTER.vhd
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Alexis
aded GRLIB Automated patcher
 r1 ------------------------------------------------------------------------------
-- This file is a part of the LPP VHDL IP LIBRARY
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 -- the Free Software Foundation; either version 3 of the License, or
Alexis
aded GRLIB Automated patcher
 r1 -- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
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 r38 -- Author : Alexis Jeandet
-- Mail : alexis.jeandet@lpp.polytechnique.fr
-------------------------------------------------------------------------------
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 r19 library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
library lpp;
use lpp.iir_filter.all;
use lpp.general_purpose.all;
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 r35 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
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 r19
entity IIR_CEL_FILTER is
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 r35 generic(Sample_SZ : integer := 16;
ChanelsCount : integer := 1;
Coef_SZ : integer := 9;
CoefCntPerCel: integer := 3;
Cels_count : integer := 5;
Mem_use : integer := use_RAM);
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 r19 port(
reset : in std_logic;
clk : in std_logic;
sample_clk : in std_logic;
regs_in : in in_IIR_CEL_reg;
regs_out : in out_IIR_CEL_reg;
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 r35 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
Alexis
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 r19
);
end IIR_CEL_FILTER;
architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
signal virg_pos : integer;
begin
virg_pos <= to_integer(unsigned(regs_in.virgPos));
CTRLR : IIR_CEL_CTRLR
Alexis
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 r35 generic map (Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 port map(
reset => reset,
clk => clk,
sample_clk => sample_clk,
sample_in => sample_in,
sample_out => sample_out,
virg_pos => virg_pos,
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 r35 coefs => coefs
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 r19 );
end ar_IIR_CEL_FILTER;