FX2_WithFIFO.vhd
96 lines
| 2.3 KiB
| text/x-vhdl
|
VhdlLexer
Alexis Jeandet
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r217 | -- FX2_WithFIFO.vhd | ||
library IEEE; | ||||
use IEEE.std_logic_1164.all; | ||||
use IEEE.numeric_std.all; | ||||
library lpp; | ||||
use lpp.lpp_usb.all; | ||||
use lpp.lpp_memory.all; | ||||
use lpp.iir_filter.all; | ||||
library techmap; | ||||
use techmap.gencomp.all; | ||||
entity FX2_WithFIFO is | ||||
generic( | ||||
tech : integer := 0; | ||||
Mem_use : integer := use_RAM; | ||||
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r245 | Enable_ReUse : std_logic := '0'; | ||
fifoCount : integer range 2 to 100 := 8; | ||||
abits : integer range 2 to 12 := 8 | ||||
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r217 | ); | ||
port( | ||||
clk : in STD_LOGIC; | ||||
if_clk : out STD_LOGIC; | ||||
reset : in std_logic; | ||||
flagb : in STD_LOGIC; | ||||
slwr : out STD_LOGIC; | ||||
slrd : out std_logic; | ||||
pktend : out STD_LOGIC; | ||||
sloe : out STD_LOGIC; | ||||
fdbusw : out std_logic_vector (7 downto 0); | ||||
fifoadr : out std_logic_vector (1 downto 0); | ||||
FULL : out std_logic; | ||||
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r219 | wen : in std_logic; | ||
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r217 | Data : in std_logic_vector(7 downto 0) | ||
); | ||||
end FX2_WithFIFO; | ||||
architecture Ar_FX2_WithFIFO of FX2_WithFIFO is | ||||
type FX2State is (idle); | ||||
Signal USB_DATA : std_logic_vector(7 downto 0); | ||||
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r219 | Signal FIFOfull : std_logic; | ||
Signal USBwe,USBfull : std_logic; | ||||
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r217 | |||
begin | ||||
FULL <= FIFOfull; | ||||
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r219 | --FIFO: lpp_fifo | ||
FIFO: FIFO_pipeline | ||||
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r217 | generic map( | ||
tech => tech, | ||||
Mem_use => Mem_use, | ||||
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r245 | fifoCount => fifoCount, | ||
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r217 | DataSz => 8, | ||
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r245 | abits => abits | ||
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r217 | ) | ||
port map( | ||||
rstn => reset, | ||||
ReUse => '0', | ||||
rclk => clk, | ||||
ren => USBfull, | ||||
rdata => USB_DATA, | ||||
empty => USBwe, | ||||
raddr => open, | ||||
wclk => clk, | ||||
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r219 | wen => wen, | ||
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r217 | wdata => Data, | ||
full => FIFOfull, | ||||
waddr => open | ||||
); | ||||
USB2: entity FX2_Driver | ||||
port map( | ||||
clk => clk, | ||||
if_clk => if_clk, | ||||
reset => reset, | ||||
flagb => flagb, | ||||
slwr => slwr, | ||||
slrd => slrd, | ||||
pktend => pktend, | ||||
sloe => sloe, | ||||
fdbusw => fdbusw, | ||||
fifoadr => fifoadr, | ||||
FULL => USBfull, | ||||
Write => not USBwe, | ||||
Data => USB_DATA | ||||
); | ||||
end ar_FX2_WithFIFO; | ||||