HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-A3PE3kL/Makefile

DAC CAL input data via fifo

Alexis Jeandet - - Load All Authors

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r181:2a5b3fda6e52 alexis


                r262:b51052768d7e

martin

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        jeandet
    
Added ICI4 designs....

              r129
            
      #GRLIB=../..

        Alexis Jeandet
    
Sync

              r181
            
      VHDLIB=../..

        martin
    
Mise a jour Projets blanc

              r100
            
      TOP=top

      BOARD=LeonLPP-A3PE3kL

      include $(GRLIB)/boards/$(BOARD)/Makefile.inc

      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

      UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf

      QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf

      EFFORT=high

      XSTOPT=

      SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"

      VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd

      VHDLSIMFILES=testbench.vhd

      SIMTOP=testbench

      SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc

      SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc

      PDC=$(GRLIB)/boards/$(BOARD)/Projet-Blanc-A3PE3kL.pdc

      BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut

      CLEAN=soft-clean

      TECHLIBS = proasic3

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

      	tmtc openchip hynix ihp gleichmann micron usbhc

      DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \

      	pci grusbhc haps  slink ascs pwm coremp7 spi ac97

      FILESKIP = i2cmst.vhd

      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      ##################  project specific targets ##########################

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jeandet Added ICI4 designs....	r129	#GRLIB=../..
Alexis Jeandet Sync	r181	VHDLIB=../..
martin Mise a jour Projets blanc	r100	TOP=top
		BOARD=LeonLPP-A3PE3kL
		include $(GRLIB)/boards/$(BOARD)/Makefile.inc
		DEVICE=$(PART)-$(PACKAGE)$(SPEED)
		UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
		QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
		EFFORT=high
		XSTOPT=
		SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
		VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
		VHDLSIMFILES=testbench.vhd
		SIMTOP=testbench
		SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
		SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
		PDC=$(GRLIB)/boards/$(BOARD)/Projet-Blanc-A3PE3kL.pdc
		BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
		CLEAN=soft-clean

		TECHLIBS = proasic3
		LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
		tmtc openchip hynix ihp gleichmann micron usbhc
		DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
		pci grusbhc haps slink ascs pwm coremp7 spi ac97

		FILESKIP = i2cmst.vhd

		include $(GRLIB)/bin/Makefile
		include $(GRLIB)/software/leon3/Makefile

		################## project specific targets ##########################