HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_bootloader/bootrom.h

Update SOLO_LFR_LFR-EM timings constraints...

Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)

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r580:f4e8c3120b82 simu_with_Leon3


                r674:b0efa9138022

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             bootrom.h
        
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        pellion
    
BootLoader v1.0.0

              r110
            
      #define MCFG1     0x10380233

      #define MCFG2     0xe6A26e60

      #define MCFG3     0x000ff000

        pellion
    
custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"

              r580
            
      //#define ASDCFG    0xfff00100

      //#define DSDCFG    0xe6A06e60

        pellion
    
BootLoader v1.0.0

              r110
            
      #define L2MCTRLIO 0x80000000

      #define IRQCTRL   0x80000200

        pellion
    
custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"

              r580
            
      #define RAMSTART  0x40000000

      #define DSUADDR   0x90000000

        pellion
    
BootLoader v1.0.0

              r110
            
      #define RAMSTART_RAMSIZE  0x40100000

      #define REG_BOOTLOADER  0x80000D00

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pellion BootLoader v1.0.0	r110	#define MCFG1 0x10380233
		#define MCFG2 0xe6A26e60
		#define MCFG3 0x000ff000
pellion custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"	r580	//#define ASDCFG 0xfff00100
		//#define DSDCFG 0xe6A06e60
pellion BootLoader v1.0.0	r110	#define L2MCTRLIO 0x80000000
		#define IRQCTRL 0x80000200
pellion custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"	r580	#define RAMSTART 0x40000000
		#define DSUADDR 0x90000000
pellion BootLoader v1.0.0	r110	#define RAMSTART_RAMSIZE 0x40100000

		#define REG_BOOTLOADER 0x80000D00