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ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....
ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen. Solved in place design developpment problem on Windows, look at EGSE_ICI makefile.

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r100:fc97c34d69e3 martin
r220:9cd9574d2765 alexis
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default.sdc
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martin
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r100 # Synplicity, Inc. constraint file
# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
# Written on Wed Aug 1 19:29:24 2007
# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
#
# Collections
#
#
# Clocks
#
define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5
#
# Clock to Clock
#
#
# Inputs/Outputs
#
define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
#
# Registers
#
#
# Multicycle Path
#
#
# False Path
#
#
# Path Delay
#
#
# Attributes
#
define_global_attribute syn_useioff {1}
define_global_attribute -disable syn_netlist_hierarchy {0}
define_attribute {etx_clk} syn_noclockbuf {1}
#
# I/O standards
#
#
# Compile Points
#
#
# Other Constraints
#