top_libero.prj
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r100 | KEY LIBERO "9.1" | ||
KEY CAPTURE "9.1.0.18" | ||||
KEY DEFAULT_IMPORT_LOC "D:\Mission_Solar_Orbiteur\Prog_VHDL\Matrice Spec\MATRICE\hdl" | ||||
KEY DEFAULT_OPEN_LOC "" | ||||
KEY ProjectID "105b6a94-08a0-483a-9f39-345e43044ca5" | ||||
KEY HDLTechnology "VHDL" | ||||
KEY VendorTechnology_Family "ProASIC3L" | ||||
KEY VendorTechnology_Die "IT14X14M4LDP" | ||||
KEY VendorTechnology_Package "fg896" | ||||
KEY ProjectLocation "D:\GRLIB_BusAMBA\VHD_Lib\designs\ProjetBlanc-LeonLPP-A3P3K" | ||||
KEY SimulationType "VHDL" | ||||
KEY Vendor "Actel" | ||||
KEY ActiveRoot "leon3mp::work" | ||||
LIST REVISIONS | ||||
VALUE="Impl1",NUM=1 | ||||
VALUE="Impl2",NUM=2 | ||||
CURREV=2 | ||||
ENDLIST | ||||
LIST LIBRARIES | ||||
grlib | ||||
synplify | ||||
techmap | ||||
spw | ||||
eth | ||||
opencores | ||||
gaisler | ||||
esa | ||||
fmf | ||||
spansion | ||||
gsi | ||||
lpp | ||||
cypress | ||||
ENDLIST | ||||
LIST LIBRARY_grlib | ||||
ALIAS=grlib | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_synplify | ||||
ALIAS=synplify | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_techmap | ||||
ALIAS=techmap | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_spw | ||||
ALIAS=spw | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_eth | ||||
ALIAS=eth | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_opencores | ||||
ALIAS=opencores | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_gaisler | ||||
ALIAS=gaisler | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_esa | ||||
ALIAS=esa | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_fmf | ||||
ALIAS=fmf | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_spansion | ||||
ALIAS=spansion | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_gsi | ||||
ALIAS=gsi | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_lpp | ||||
ALIAS=lpp | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST LIBRARY_cypress | ||||
ALIAS=cypress | ||||
COMPILE_OPTION=COMPILE | ||||
ENDLIST | ||||
LIST FileManager | ||||
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\amba_lcd_16x2_ctrlr.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="4857" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\apb_lcd_ctrlr.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="4684" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\FRAME_CLK.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="2063" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_CFG.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="2262" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_DRVR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="4068" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_ENGINE.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="5400" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_2x16_DRIVER.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="4608" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_CLK_GENERATOR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="2035" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\Top_LCD.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="3093" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\APB_IIR_CEL.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1328101750" | ||||
SIZE="8034" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\APB_IIR_Filter.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1347275095" | ||||
SIZE="9037" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FILTER.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1326707253" | ||||
SIZE="3402" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1349782083" | ||||
SIZE="7067" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FilterCTRLR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1326707253" | ||||
SIZE="8493" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FILTER_RAM_CTRLR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1326707253" | ||||
SIZE="5164" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1346936328" | ||||
SIZE="10652" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\IIR_CEL_FILTER.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1346936328" | ||||
SIZE="2708" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1349782071" | ||||
SIZE="9041" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1348571754" | ||||
SIZE="2383" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1326707253" | ||||
SIZE="2276" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\RAM_CTRLR2.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1349786999" | ||||
SIZE="5122" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\Top_Filtre_IIR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1326707253" | ||||
SIZE="1005" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\Top_IIR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1349782055" | ||||
SIZE="2321" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1294746407" | ||||
SIZE="141869" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1294746407" | ||||
SIZE="4032" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\APB_FFT.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1331642027" | ||||
SIZE="5929" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\APB_FFT_half.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1332429937" | ||||
SIZE="5590" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1295516964" | ||||
SIZE="12457" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1333012650" | ||||
SIZE="4721" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1294746408" | ||||
SIZE="25871" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1294746408" | ||||
SIZE="32249" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1294746408" | ||||
SIZE="5049" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\Flag_Extremum.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1328875675" | ||||
SIZE="2574" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1333025894" | ||||
SIZE="4326" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1333024721" | ||||
SIZE="7485" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1294746408" | ||||
SIZE="3997" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1294746408" | ||||
SIZE="12080" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Adder.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="2272" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="1930" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\ALU.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="2278" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="1958" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\general_purpose.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="5897" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\APB_AMR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1313682702" | ||||
SIZE="3577" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\bclk_reg.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1286437702" | ||||
SIZE="685" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\Clock_multi.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1286438714" | ||||
SIZE="1218" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\Dephaseur.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1286455334" | ||||
SIZE="1492" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\Gene_Rz.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1286438978" | ||||
SIZE="1011" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\lpp_AMR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1313679648" | ||||
SIZE="2523" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_balise\APB_Balise.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1308741597" | ||||
SIZE="4392" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_balise\lpp_balise.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1308732390" | ||||
SIZE="1887" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1319721765" | ||||
SIZE="5159" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_delay\lpp_delay.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1319721794" | ||||
SIZE="2254" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_delay\TimerDelay.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1319721593" | ||||
SIZE="1726" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="7280" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="1961" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="1985" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="1710" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="1775" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Multiplier.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="2230" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MUX2.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="1692" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\REG.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="1812" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Shifter.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="2198" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1339079556" | ||||
SIZE="4077" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1338881814" | ||||
SIZE="2577" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="2995" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1339080108" | ||||
SIZE="4220" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\lpp_apb_ad_conv.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="4391" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\WriteGen_ADC.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1338897805" | ||||
SIZE="2748" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1351169981" | ||||
SIZE="1335" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_amba\APB_MULTI_DIODE.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292489754" | ||||
SIZE="3238" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_amba\APB_SIMPLE_DIODE.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292320842" | ||||
SIZE="3455" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292248642" | ||||
SIZE="2548" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\APB_CNA.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1299077829" | ||||
SIZE="4480" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\CNA_TabloC.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292494283" | ||||
SIZE="3111" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\Convertisseur_config.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292494283" | ||||
SIZE="1626" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\Gene_SYNC.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292494284" | ||||
SIZE="2613" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1322489966" | ||||
SIZE="2872" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\Serialize.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292494283" | ||||
SIZE="3956" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\Systeme_Clock.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1292494284" | ||||
SIZE="2338" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="8207" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\ALU_v2.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="2878" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\APB_Matrix.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="4198" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="3738" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="3663" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="7938" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\MAC_v2.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="9200" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="2885" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="2955" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\Starter.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="3521" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\TopMatrix_PDR.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="7268" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\Top_MatrixSpec.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="2328" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\TwoComplementer.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1330093522" | ||||
SIZE="2848" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1338903165" | ||||
SIZE="10851" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1351171433" | ||||
SIZE="3746" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1328013887" | ||||
SIZE="4761" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1351169841" | ||||
SIZE="5717" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1323074753" | ||||
SIZE="5741" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1340968066" | ||||
SIZE="5098" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\BaudGen.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1303904791" | ||||
SIZE="3871" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\lpp_uart.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1340968066" | ||||
SIZE="3903" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\Shift_REG.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1340881501" | ||||
SIZE="3363" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\UART.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1340968066" | ||||
SIZE="4070" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_usb\APB_USB.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1314195515" | ||||
SIZE="4054" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_usb\lpp_usb.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1314194773" | ||||
SIZE="3039" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\..\..\lib\lpp\.\lpp_usb\RWbuf.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1314195515" | ||||
SIZE="5486" | ||||
LIBRARY="lpp" | ||||
ENDFILE | ||||
VALUE "<project>\ahbrom.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1323083228" | ||||
SIZE="8992" | ||||
ENDFILE | ||||
VALUE "<project>\config.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1323083228" | ||||
SIZE="6294" | ||||
ENDFILE | ||||
VALUE "<project>\leon3mp.vhd,hdl" | ||||
STATE="utd" | ||||
TIME="1351504305" | ||||
SIZE="13693" | ||||
ENDFILE | ||||
VALUE "<project>\synthesis\leon3mp.edn,syn_edn" | ||||
STATE="ood" | ||||
TIME="1351171608" | ||||
SIZE="14918342" | ||||
ENDFILE | ||||
VALUE "<project>\synthesis\leon3mp_sdc.sdc,syn_sdc" | ||||
STATE="ood" | ||||
TIME="1351171606" | ||||
SIZE="381" | ||||
ENDFILE | ||||
ENDLIST | ||||
LIST UsedFile | ||||
ENDLIST | ||||
LIST NewModulesInfo | ||||
ENDLIST | ||||
LIST AssociatedStimulus | ||||
ENDLIST | ||||
LIST Other_Association | ||||
ENDLIST | ||||
LIST SimulationOptions | ||||
UseAutomaticDoFile=true | ||||
IncludeWaveDo=false | ||||
Type=max | ||||
RunTime=1000ns | ||||
Resolution=1ps | ||||
VsimOpt= | ||||
EntityName=testbench | ||||
TopInstanceName=<top>_0 | ||||
DoFileName= | ||||
DoFileName2=wave.do | ||||
DoFileParams= | ||||
DisplayDUTWave=false | ||||
LogAllSignals=false | ||||
DumpVCD=false | ||||
VCDFileName=power.vcd | ||||
ENDLIST | ||||
LIST ModelSimLibPath | ||||
UseCustomPath=FALSE | ||||
LibraryPath= | ||||
ENDLIST | ||||
LIST GlobalFlowOptions | ||||
GenerateHDLAfterSynthesis=FALSE | ||||
GenerateHDLAfterPhySynthesis=FALSE | ||||
RunDRCAfterSynthesis=FALSE | ||||
AutoCheckConstraints=TRUE | ||||
UpdateViewDrawIni=TRUE | ||||
UpdateModelSimIni=TRUE | ||||
NoIOMode=FALSE | ||||
GenerateHDLFromSchematic=TRUE | ||||
FlashProInputFile=pdb | ||||
SmartGenCompileReport=T | ||||
ENDLIST | ||||
LIST PhySynthesisOptions | ||||
ENDLIST | ||||
LIST Profiles | ||||
NAME="Synplify AE" | ||||
FUNCTION="Synthesis" | ||||
TOOL="Synplify" | ||||
LOCATION="C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\bin\synplify_pro.exe" | ||||
PARAM="" | ||||
BATCH=0 | ||||
EndProfile | ||||
NAME="ModelSim AE" | ||||
FUNCTION="Simulation" | ||||
TOOL="ModelSim" | ||||
LOCATION="C:\Actel\Libero_v9.1\Model\win32acoem\modelsim.exe" | ||||
PARAM="" | ||||
BATCH=0 | ||||
EndProfile | ||||
NAME="WFL" | ||||
FUNCTION="Stimulus" | ||||
TOOL="WFL" | ||||
LOCATION="syncad.exe" | ||||
PARAM="-pwflite" | ||||
BATCH=0 | ||||
EndProfile | ||||
NAME="FlashPro" | ||||
FUNCTION="Program" | ||||
TOOL="FlashPro" | ||||
LOCATION="C:\Actel\Libero_v9.1\Designer\bin\FlashPro.exe" | ||||
PARAM="" | ||||
BATCH=0 | ||||
EndProfile | ||||
ENDLIST | ||||
LIST ProjectState5.1 | ||||
ENDLIST | ||||
LIST ExcludePackageForSimulation | ||||
ENDLIST | ||||
LIST ExcludePackageForSynthesis | ||||
ENDLIST | ||||
LIST IncludeModuleForSimulation | ||||
ENDLIST | ||||
LIST CDBOrder | ||||
ENDLIST | ||||
LIST UserCustomizedFileList | ||||
ENDLIST | ||||
LIST OpenedFileList | ||||
DESIGNFLOW: | ||||
FILE:<project>\leon3mp.vhd,hdl | ||||
FILE:<project>\..\..\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl | ||||
ACTIVE_VIEW:1 | ||||
ENDLIST | ||||