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      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 3 of the License, or

      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      ------------------------------------------------------------------------------

      --                    Author : Martin Morlot

      --                     Mail : martin.morlot@lpp.polytechnique.fr

      ------------------------------------------------------------------------------

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

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      library lpp;

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      use lpp.lpp_cna.all;

      --! Programme du Convertisseur Num�rique/Analogique

      entity DacDriver is

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      --generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz

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        port(

          clk         : in std_logic;                        --! Horloge du composant

          rst         : in std_logic;                        --! Reset general du composant

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          SysClk      : in std_logic;

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          enable      : in std_logic;                        --! Autorise ou non l'utilisation du composant

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          Data_IN     : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits

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          SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur

          SCLK        : out std_logic;                       --! Horloge systeme du convertisseur

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          Readn       : out std_logic;

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      --    Ready       : out std_logic;                       --! Flag, signale la fin de la s�rialisation d'une donn�e

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          Data        : out std_logic                        --! Donn�e num�rique s�rialis�

          );

      end entity;

      architecture ar_DacDriver of DacDriver is

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      --signal s_SCLK      : std_logic;

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      signal Send    : std_logic;

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      signal Sended : std_logic;

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      begin

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      --SystemCLK : entity work.Clock_Divider

      --    generic map (cpt_serial)

      --    port map (clk,rst,s_SCLK);

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      Signal_sync : Gene_SYNC

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          port map (SysClk,rst,clk,enable,Sended,Send,Readn,SYNC);

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      Serial : serialize

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          port map (clk,rst,clk,Data_IN,Send,Sended,Data);

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      --RenGEN : entity work.ReadFifo_GEN

      --    port map (clk,rst,Send,Readn);

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      SCLK        <= clk;

      --Ready <= s_Rdy;

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      end architecture;

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martin ReName some files	r242	------------------------------------------------------------------------------
		-- This file is a part of the LPP VHDL IP LIBRARY
		-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
		-- the Free Software Foundation; either version 3 of the License, or
		-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		--
		-- You should have received a copy of the GNU General Public License
		-- along with this program; if not, write to the Free Software
		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		------------------------------------------------------------------------------
		-- Author : Martin Morlot
		-- Mail : martin.morlot@lpp.polytechnique.fr
		------------------------------------------------------------------------------
		library IEEE;
		use IEEE.std_logic_1164.all;
		use IEEE.numeric_std.all;
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	library lpp;
martin ReName some files	r242	use lpp.lpp_cna.all;

		--! Programme du Convertisseur Num�rique/Analogique

		entity DacDriver is
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	--generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
martin ReName some files	r242	port(
		clk : in std_logic; --! Horloge du composant
		rst : in std_logic; --! Reset general du composant
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	SysClk : in std_logic;
martin ReName some files	r242	enable : in std_logic; --! Autorise ou non l'utilisation du composant
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
martin ReName some files	r242	SYNC : out std_logic; --! Signal de synchronisation du convertisseur
		SCLK : out std_logic; --! Horloge systeme du convertisseur
martin DAC CAL input data via fifo	r262	Readn : out std_logic;
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	-- Ready : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
martin ReName some files	r242	Data : out std_logic --! Donn�e num�rique s�rialis�
		);
		end entity;


		architecture ar_DacDriver of DacDriver is

martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	--signal s_SCLK : std_logic;
martin DAC CAL input data via fifo	r262	signal Send : std_logic;
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	signal Sended : std_logic;
martin ReName some files	r242
		begin

martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	--SystemCLK : entity work.Clock_Divider
		-- generic map (cpt_serial)
		-- port map (clk,rst,s_SCLK);
martin ReName some files	r242

		Signal_sync : Gene_SYNC
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	port map (SysClk,rst,clk,enable,Sended,Send,Readn,SYNC);
martin ReName some files	r242

		Serial : serialize
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	port map (clk,rst,clk,Data_IN,Send,Sended,Data);
martin ReName some files	r242
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	--RenGEN : entity work.ReadFifo_GEN
		-- port map (clk,rst,Send,Readn);
martin ReName some files	r242
martin DAC CAL input data via fifo + Freq échantillonnage variable	r274	SCLK <= clk;
		--Ready <= s_Rdy;
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		end architecture;