HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd

Added LFR DM board files and miniAMBA design tesed under Libero9.1 sp1

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             FRAME_CLK.vhd
        
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        Alexis
    
aded GRLIB Automated patcher

              r1
            
      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      --  the Free Software Foundation; either version 3 of the License, or

        Alexis
    
aded GRLIB Automated patcher

              r1
            
      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      -------------------------------------------------------------------------------

        Alexis
    
Minor changes

              r38
            
      --                    Author : Alexis Jeandet

      --                     Mail : alexis.jeandet@lpp.polytechnique.fr

      -------------------------------------------------------------------------------

        Alexis
    
aded GRLIB Automated patcher

              r1
            
      library IEEE;

      use IEEE.STD_LOGIC_1164.ALL;

      use IEEE.NUMERIC_STD.ALL;

      library lpp;

      use lpp.amba_lcd_16x2_ctrlr.all;

      entity FRAME_CLK_GEN is

      	generic(OSC_freqKHz	:	integer := 50000);

          Port ( clk : in  STD_LOGIC;

                 reset : in  STD_LOGIC;

                 FRAME_CLK : out  STD_LOGIC);

      end FRAME_CLK_GEN;

      architecture Behavioral of FRAME_CLK_GEN is

        Alexis
    
Cleaned APB_LCD_DRIVER, added C driver for LCD frame buffer and general purpose APB management(PnP). Added example for implementing APB_LCD_DRIVER on digilent xc3s1600e board.

              r14
            
      Constant	Goal_FRAME_CLK_FREQ	:	integer := 25;

        Alexis
    
aded GRLIB Automated patcher

              r1
            
      Constant FRAME_CLK_TRIG	:	integer	:= OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;

      signal	CPT	:	integer := 0;

      signal	FRAME_CLK_reg : std_logic :='0';

      begin

      FRAME_CLK	<=	FRAME_CLK_reg;

      process(reset,clk)

      begin

      	if reset = '0' then

      		CPT <=	0;

      		FRAME_CLK_reg <= '0';

      	elsif clk'event and clk = '1' then

      		if CPT = FRAME_CLK_TRIG then

      			CPT <= 0;

      			FRAME_CLK_reg	<= not FRAME_CLK_reg;

      		else

      			CPT	<=	CPT + 1;

      		end if;

      	end if;

      end process;

      end Behavioral;

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Alexis aded GRLIB Automated patcher	r1	------------------------------------------------------------------------------
		-- This file is a part of the LPP VHDL IP LIBRARY
		-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	-- the Free Software Foundation; either version 3 of the License, or
Alexis aded GRLIB Automated patcher	r1	-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		--
		-- You should have received a copy of the GNU General Public License
		-- along with this program; if not, write to the Free Software
		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		-------------------------------------------------------------------------------
Alexis Minor changes	r38	-- Author : Alexis Jeandet
		-- Mail : alexis.jeandet@lpp.polytechnique.fr
		-------------------------------------------------------------------------------
Alexis aded GRLIB Automated patcher	r1	library IEEE;
		use IEEE.STD_LOGIC_1164.ALL;
		use IEEE.NUMERIC_STD.ALL;
		library lpp;
		use lpp.amba_lcd_16x2_ctrlr.all;

		entity FRAME_CLK_GEN is
		generic(OSC_freqKHz : integer := 50000);
		Port ( clk : in STD_LOGIC;
		reset : in STD_LOGIC;
		FRAME_CLK : out STD_LOGIC);
		end FRAME_CLK_GEN;

		architecture Behavioral of FRAME_CLK_GEN is

Alexis Cleaned APB_LCD_DRIVER, added C driver for LCD frame buffer and general purpose APB management(PnP). Added example for implementing APB_LCD_DRIVER on digilent xc3s1600e board.	r14	Constant Goal_FRAME_CLK_FREQ : integer := 25;
Alexis aded GRLIB Automated patcher	r1
		Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;

		signal CPT : integer := 0;
		signal FRAME_CLK_reg : std_logic :='0';

		begin

		FRAME_CLK <= FRAME_CLK_reg;

		process(reset,clk)
		begin
		if reset = '0' then
		CPT <= 0;
		FRAME_CLK_reg <= '0';
		elsif clk'event and clk = '1' then
		if CPT = FRAME_CLK_TRIG then
		CPT <= 0;
		FRAME_CLK_reg <= not FRAME_CLK_reg;
		else
		CPT <= CPT + 1;
		end if;
		end if;
		end process;
		end Behavioral;