LF_SMPL_CLK.vhd
47 lines
| 799 B
| text/x-vhdl
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VhdlLexer
r129 | -- LF_SMPL_CLK.vhd | ||
library IEEE; | |||
use IEEE.numeric_std.all; | |||
use IEEE.std_logic_1164.all; | |||
r223 | entity LF_SMPL_CLK is | ||
generic(N : integer range 0 to 4096 :=24); | |||
r129 | port( | ||
r223 | reset : in std_logic; | ||
wclk : in std_logic; | |||
r129 | SMPL_CLK : out std_logic | ||
); | |||
end entity; | |||
architecture ar_LF_SMPL_CLK of LF_SMPL_CLK is | |||
r223 | signal cpt : integer range 0 to N-1 := 0; | ||
r129 | begin | ||
r223 | process(reset,wclk) | ||
r129 | begin | ||
r223 | if reset = '0' then | ||
SMPL_CLK <= '1'; | |||
cpt <= 0; | |||
elsif wclk'event and wclk = '1' then | |||
if cpt = (N-1) then | |||
r129 | cpt <= 0; | ||
else | |||
cpt <= cpt+1; | |||
end if; | |||
if cpt = 0 then | |||
SMPL_CLK <= '1'; | |||
r223 | elsif cpt = (N/2) then | ||
r129 | SMPL_CLK <= '0'; | ||
end if; | |||
end if; | |||
end process; | |||
end ar_LF_SMPL_CLK; |