leon3mp_sdc.sdc
25 lines
| 381 B
| application/vnd.stardivision.calc
|
TextLexer
martin
|
r284 | # Top Level Design Parameters | ||
| # Clocks | ||||
| create_clock -period 10.000000 -waveform {0.000000 5.000000} clk50MHz | ||||
| # False Paths Between Clocks | ||||
| # False Path Constraints | ||||
| # Maximum Delay Constraints | ||||
| # Multicycle Constraints | ||||
| # Virtual Clocks | ||||
| # Output Load Constraints | ||||
| # Driving Cell Constraints | ||||
| # Wire Loads | ||||
| # set_wire_load_mode top | ||||
| # Other Constraints | ||||