APB_DAC.vhd
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| 5.0 KiB
| text/x-vhdl
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VhdlLexer
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r242 | ------------------------------------------------------------------------------ | |
-- This file is a part of the LPP VHDL IP LIBRARY | |||
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
-- | |||
-- This program is free software; you can redistribute it and/or modify | |||
-- it under the terms of the GNU General Public License as published by | |||
-- the Free Software Foundation; either version 3 of the License, or | |||
-- (at your option) any later version. | |||
-- | |||
-- This program is distributed in the hope that it will be useful, | |||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
-- GNU General Public License for more details. | |||
-- | |||
-- You should have received a copy of the GNU General Public License | |||
-- along with this program; if not, write to the Free Software | |||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
------------------------------------------------------------------------------ | |||
-- Author : Martin Morlot | |||
-- Mail : martin.morlot@lpp.polytechnique.fr | |||
------------------------------------------------------------------------------ | |||
library ieee; | |||
use ieee.std_logic_1164.all; | |||
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r274 | use IEEE.numeric_std.all; | |
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r242 | library grlib; | |
use grlib.amba.all; | |||
use grlib.stdlib.all; | |||
use grlib.devices.all; | |||
library lpp; | |||
use lpp.lpp_amba.all; | |||
use lpp.apb_devices_list.all; | |||
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r274 | use lpp.general_purpose.all; | |
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r242 | use lpp.lpp_cna.all; | |
--! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba | |||
entity APB_DAC is | |||
generic ( | |||
pindex : integer := 0; | |||
paddr : integer := 0; | |||
pmask : integer := 16#fff#; | |||
pirq : integer := 0; | |||
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r248 | abits : integer := 8; | |
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r284 | Nmax : integer := 7); | |
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r242 | port ( | |
clk : in std_logic; --! Horloge du composant | |||
rst : in std_logic; --! Reset general du composant | |||
apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |||
apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus | |||
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r274 | DataIN : in std_logic_vector(15 downto 0); | |
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r242 | Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL | |
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r262 | Readn : out std_logic; | |
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r242 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur | |
SCLK : out std_logic; --! Horloge systeme du convertisseur | |||
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r274 | CLK_VAR : out std_logic; | |
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r242 | DATA : out std_logic --! Donn�e num�rique s�rialis� | |
); | |||
end entity; | |||
--! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus | |||
--! et les sorties seront cabl�es vers le convertisseur. | |||
architecture ar_APB_DAC of APB_DAC is | |||
constant REVISION : integer := 1; | |||
constant pconfig : apb_config_type := ( | |||
0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), | |||
1 => apb_iobar(paddr, pmask)); | |||
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r274 | signal clkdiv : std_logic; | |
signal clkvar : std_logic; | |||
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r242 | signal enable : std_logic; | |
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r274 | signal Ready : std_logic; | |
signal N : integer range 0 to Nmax; | |||
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r242 | ||
type DAC_ctrlr_Reg is record | |||
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r274 | DAC_Cfg : std_logic_vector(0 downto 0); | |
CLK_Cfg : std_logic_vector(2 downto 0); | |||
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r242 | end record; | |
signal Rec : DAC_ctrlr_Reg; | |||
signal Rdata : std_logic_vector(31 downto 0); | |||
begin | |||
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r261 | enable <= Rec.DAC_Cfg(0); | |
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r274 | ||
N <= to_integer(unsigned(Rec.CLK_Cfg)); | |||
CLK0 : Clock_Divider | |||
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r275 | generic map (308) --clkdiv = 80KHz | |
port map (clk,rst,clkdiv); | |||
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r274 | ||
CLKSET : ClkSetting | |||
generic map(Nmax) | |||
port map(clkdiv,rst,N,clkvar); | |||
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r242 | ||
CONV0 : DacDriver | |||
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r274 | -- generic map (cpt_serial) | |
port map(clk,rst,clkvar,enable,DataIN,SYNC,SCLK,Readn,Data); | |||
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r242 | ||
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r274 | CLK_VAR <= clkvar; | |
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r242 | ||
process(rst,clk) | |||
begin | |||
if(rst='0')then | |||
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r274 | Rec.CLK_Cfg <= (others => '0'); | |
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r242 | ||
elsif(clk'event and clk='1')then | |||
--APB Write OP | |||
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |||
case apbi.paddr(abits-1 downto 2) is | |||
when "000000" => | |||
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r261 | Rec.DAC_Cfg(0) <= apbi.pwdata(0); | |
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r274 | Rec.CLK_Cfg <= apbi.pwdata(6 downto 4); | |
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r242 | when others => | |
null; | |||
end case; | |||
end if; | |||
--APB Read OP | |||
if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |||
case apbi.paddr(abits-1 downto 2) is | |||
when "000000" => | |||
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r274 | Rdata(31 downto 7) <= (others => '0'); | |
Rdata(6 downto 4) <= Rec.CLK_Cfg; | |||
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r284 | Rdata(3 downto 1) <= (others => '0'); | |
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r274 | Rdata(0 downto 0) <= Rec.DAC_Cfg; | |
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r242 | when others => | |
Rdata <= (others => '0'); | |||
end case; | |||
end if; | |||
end if; | |||
apbo.pconfig <= pconfig; | |||
end process; | |||
apbo.prdata <= Rdata when apbi.penable = '1'; | |||
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r261 | Cal_EN <= enable; | |
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r248 | end architecture; |