HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/MINI-LFR_waveformPicker/Makefile

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r286:8b7f4967459c JC


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             Makefile
        
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        JC
    
temp

              r251
            
      VHDLIB=../..

      SCRIPTSDIR=$(VHDLIB)/scripts/

      GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)

      TOP=MINI_LFR_top

      BOARD=MINI-LFR

      include $(VHDLIB)/boards/$(BOARD)/Makefile.inc

      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

      UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf

      QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf

      EFFORT=high

      XSTOPT=

      SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"

        pellion
    
MINI LFR blank project

              r266
            
      VHDLSYNFILES=	MINI_LFR_top.vhd 

        JC
    
temp

              r251
            
      PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc

      BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut

      CLEAN=soft-clean

      TECHLIBS = proasic3e

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

        pellion
    
Correction LPP_DMA - simulation ok avec une RAM externe (CY7C1061DV33)

              r286
            
      	tmtc openchip hynix ihp gleichmann micron usbhc 

        JC
    
temp

              r251
            
      DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \

      	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \

      	./amba_lcd_16x2_ctrlr \

      	./general_purpose/lpp_AMR \

      	./general_purpose/lpp_balise \

      	./general_purpose/lpp_delay \

      	./dsp/lpp_fft \

      	./lpp_bootloader \

      	./lpp_cna \

      	./lpp_demux \

      	./lpp_matrix \

      	./lpp_uart \

      	./lpp_usb \

      	./lpp_Header \

        pellion
    
Correction LPP_DMA - simulation ok avec une RAM externe (CY7C1061DV33)

              r286
            
      	./lpp_sim/CY7C1061DV33 \

        JC
    
temp

              r251
            
        pellion
    
TOP with Leon3 SoC only (no LPP module)

              r260
            
      FILESKIP =lpp_lfr_ms.vhd \

      	i2cmst.vhd \

        JC
    
temp

              r251
            
      	APB_MULTI_DIODE.vhd \

        pellion
    
TOP with Leon3 SoC only (no LPP module)

              r260
            
      	APB_SIMPLE_DIODE.vhd \

      	Top_MatrixSpec.vhd \

      	APB_FFT.vhd

        JC
    
temp

              r251
            
      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      ##################  project specific targets ##########################

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JC temp	r251	VHDLIB=../..
		SCRIPTSDIR=$(VHDLIB)/scripts/
		GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
		TOP=MINI_LFR_top
		BOARD=MINI-LFR
		include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
		DEVICE=$(PART)-$(PACKAGE)$(SPEED)
		UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
		QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
		EFFORT=high
		XSTOPT=
		SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
pellion MINI LFR blank project	r266	VHDLSYNFILES= MINI_LFR_top.vhd
JC temp	r251
		PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
		BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
		CLEAN=soft-clean

		TECHLIBS = proasic3e

		LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
pellion Correction LPP_DMA - simulation ok avec une RAM externe (CY7C1061DV33)	r286	tmtc openchip hynix ihp gleichmann micron usbhc
JC temp	r251
		DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
		pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
		./amba_lcd_16x2_ctrlr \
		./general_purpose/lpp_AMR \
		./general_purpose/lpp_balise \
		./general_purpose/lpp_delay \
		./dsp/lpp_fft \
		./lpp_bootloader \
		./lpp_cna \
		./lpp_demux \
		./lpp_matrix \
		./lpp_uart \
		./lpp_usb \
		./lpp_Header \
pellion Correction LPP_DMA - simulation ok avec une RAM externe (CY7C1061DV33)	r286	./lpp_sim/CY7C1061DV33 \
JC temp	r251
pellion TOP with Leon3 SoC only (no LPP module)	r260	FILESKIP =lpp_lfr_ms.vhd \
		i2cmst.vhd \
JC temp	r251	APB_MULTI_DIODE.vhd \
pellion TOP with Leon3 SoC only (no LPP module)	r260	APB_SIMPLE_DIODE.vhd \
		Top_MatrixSpec.vhd \
		APB_FFT.vhd
JC temp	r251
		include $(GRLIB)/bin/Makefile
		include $(GRLIB)/software/leon3/Makefile

		################## project specific targets ##########################