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LFR-EQM 2.1.82 - b...
LFR-EQM 2.1.82 - b > SMP_CLK @ 24576MHz/25 = 983.03Hz > OEn active during one cycle > sample ADC_DATA one cycle after the OEn SMP_CLK --------|___________ CLK_25Mhz-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_| ADC_OEn ------------|___|----- ADC_DATA ****************{data} ADC_DATA_reg****************{data}
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r129:8459a437c1f1 alexis
r600:1d46c91bda8b simu_with_Leon3
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coregen.cgp
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jeandet
Added ICI4 designs....
 r129 # Date: Thu Dec 29 23:13:08 2011
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatParenNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Synplicity
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: 1691a6bd