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debug EQM...
debug EQM => memory controller and DMA lock W.I.P.
jeandet - - Load All Authors

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r223:006079fa8bed alexis
r570:0b1aedcd4196 JC
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ICI4-Main-BD.ucf
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jeandet
Added cross domain synchronisation blocks.
 r223 NET "CLK" LOC = "B10" | IOSTANDARD = LVCMOS33;
NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
jeandet
ICI rockets designs added
 r168 NET "RESET" LOC = "A5" | IOSTANDARD = LVTTL;
jeandet
Added cross domain synchronisation blocks.
 r223
NET "SCLK" CLOCK_DEDICATED_ROUTE = FALSE;
jeandet
ICI rockets designs added
 r168 NET "SCLK" LOC = "V22" | IOSTANDARD = LVTTL;
jeandet
Added cross domain synchronisation blocks.
 r223
jeandet
ICI rockets designs added
 r168 NET "GATE" LOC = "T22" | IOSTANDARD = LVTTL;
jeandet
Added cross domain synchronisation blocks.
 r223
NET "MINF" CLOCK_DEDICATED_ROUTE = FALSE;
jeandet
ICI rockets designs added
 r168 NET "MINF" LOC = "T21" | IOSTANDARD = LVTTL;
jeandet
Added cross domain synchronisation blocks.
 r223
jeandet
ICI rockets designs added
 r168 NET "MAJF" LOC = "U22" | IOSTANDARD = LVTTL;
jeandet
Added cross domain synchronisation blocks.
 r223 NET "DATA" LOC = "V21" | IOSTANDARD = LVCMOS33;
NET "DC_ADC_SCLK" LOC = "AB17" | IOSTANDARD = LVCMOS33;
jeandet
ICI rockets designs added
 r168 NET "DC_ADC_IN(0)" LOC = "AB19" | IOSTANDARD = LVTTL;
NET "DC_ADC_IN(1)" LOC = "AA18" | IOSTANDARD = LVTTL;
jeandet
Added cross domain synchronisation blocks.
 r223 NET "DC_ADC_FSynch" LOC = "AB18" | IOSTANDARD = LVCMOS33;
NET "LED" LOC = "A3" | IOSTANDARD = LVCMOS33;
NET "SET_RESET0" LOC = "AB21" | IOSTANDARD = LVCMOS33;
NET "SET_RESET1" LOC = "AB20" | IOSTANDARD = LVCMOS33;
NET "LF_SCK" LOC = "W20"| IOSTANDARD = LVCMOS33;
NET "LF_CNV" LOC = "Y18"| IOSTANDARD = LVCMOS33;
NET "LF_SDO1" LOC = "W17" | IOSTANDARD = LVTTL;
NET "LF_SDO2" LOC = "AA21" | IOSTANDARD = LVTTL;
NET "LF_SDO3" LOC = "AA16" | IOSTANDARD = LVTTL;