Bridge.vhd
52 lines
| 1.2 KiB
| text/x-vhdl
|
VhdlLexer
martin
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r103 | -- Bridge.vhd | |
library IEEE; | |||
use IEEE.std_logic_1164.all; | |||
use IEEE.numeric_std.all; | |||
entity Bridge is | |||
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r106 | port( | |
clk : in std_logic; | |||
raz : in std_logic; | |||
EmptyUp : in std_logic; | |||
FullDwn : in std_logic; | |||
WriteDwn : out std_logic; | |||
ReadUp : out std_logic | |||
); | |||
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r103 | end entity; | |
architecture ar_Bridge of Bridge is | |||
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r106 | type etat is (e0,e1); | |
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r103 | signal ect : etat; | |
begin | |||
process(clk,raz) | |||
begin | |||
if(raz='0')then | |||
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r106 | WriteDwn <= '1'; | |
ReadUp <= '1'; | |||
ect <= e0; | |||
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r103 | elsif(clk'event and clk='1')then | |
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r106 | ||
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r103 | case ect is | |
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r106 | ||
when e0 => | |||
WriteDwn <= '1'; | |||
if(EmptyUp='0' and FullDwn='0')then | |||
ReadUp <= '0'; | |||
ect <= e1; | |||
end if; | |||
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r103 | ||
when e1 => | |||
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r106 | ReadUp <= '1'; | |
WriteDwn <= '0'; | |||
ect <= e0; | |||
end case; | |||
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r103 | end if; | |
end process; | |||
end architecture; |